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dgisselq |
#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include "sdramsim.h"
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short SDRAMSIM::operator()(int clk, int cke, int cs_n, int ras_n, int cas_n, int we_n,
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int bs, unsigned addr, int driv, short data) {
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short result = 0;
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dgisselq |
if (driv) // If the bus is going out, reads don't make sense ... but
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result = data; // read what we output anyway
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else if (!clk) // If the clock is zero, return our last value
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return m_last_value; // Always called w/clk=1, thus never here
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dgisselq |
if (!cke) {
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fprintf(stderr, "This simulation only supports CKE high!\n");
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fprintf(stderr, "\tCKE = %d\n", cke);
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fprintf(stderr, "\tCS_n = %d\n", cs_n);
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fprintf(stderr, "\tRAS_n = %d\n", ras_n);
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fprintf(stderr, "\tCAS_n = %d\n", cas_n);
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fprintf(stderr, "\tWE_n = %d\n", we_n);
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assert(cke);
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}
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if (m_pwrup < POWERED_UP_STATE) {
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if (m_clocks_till_idle > 0)
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m_clocks_till_idle--;
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if (m_pwrup == 0) {
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assert((ras_n)&&(cas_n)&&(we_n));
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if (m_clocks_till_idle == 0) {
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m_pwrup++;
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// printf("Successful power up wait, moving to state #1\n");
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dgisselq |
}
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} else if (m_pwrup == 1) {
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if ((!cs_n)&&(!ras_n)&&(cas_n)&&(!we_n)&&(addr&0x0400)) {
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// Wait until a precharge all banks command
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m_pwrup++;
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// printf("Successful precharge command, moving to state #2\n");
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m_clocks_till_idle = 8;
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}
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} else if (m_pwrup == 2) {
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// Need 8 auto refresh cycles before or after the mode
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// set command. We'll insist they be before.
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if (m_clocks_till_idle == 0) {
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m_pwrup++;
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// printf("Successful initial auto-refresh, waiting for mode-set\n");
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for(int i=0; i<m_nrefresh; i++)
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m_refresh_time[i] = MAX_REFRESH_TIME;
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} else
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assert((!cs_n)&&(!ras_n)&&(!cas_n)&&(we_n));
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} else if (m_pwrup == 3) {
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const int tRSC = 2;
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if ((!cs_n)&&(!ras_n)&&(!cas_n)&&(!we_n)){
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// mode set
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// printf("Mode set: %08x\n", addr);
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assert(addr == 0x021);
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m_pwrup++;
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// printf("Successful mode set, moving to state #3, tRSC = %d\n", tRSC);
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m_clocks_till_idle=tRSC;
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}
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} else if (m_pwrup == 4) {
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assert(cs_n);
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if (m_clocks_till_idle == 0) {
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m_pwrup = POWERED_UP_STATE;
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m_clocks_till_idle = 0;
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// printf("Successful settup! SDRAM switching to operational\n");
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} else if (m_clocks_till_idle == 1) {
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;
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} else assert(0 && "Should never get here!");
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} else if (m_pwrup == 5) {
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if ((!cs_n)&&(!ras_n)&&(!cas_n)&&(we_n)) {
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if (m_clocks_till_idle == 0) {
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m_pwrup = POWERED_UP_STATE;
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m_clocks_till_idle = 0;
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for(int i=0; i<m_nrefresh; i++)
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m_refresh_time[i] = MAX_REFRESH_TIME;
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}
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} else {
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assert(0);
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}
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}
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m_next_wr = false;
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} else { // In operation ...
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for(int i=0; i<m_nrefresh; i++)
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m_refresh_time[i]--;
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if (m_refresh_time[m_refresh_loc] < 0) {
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assert(0 && "Failed refresh requirement");
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} for(int i=0; i<NBANKS; i++) {
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m_bank_status[i] >>= 1;
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if (m_bank_status[i]&2)
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m_bank_status[i] |= 4;
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if (m_bank_status[i]&1) { // Bank is open
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m_bank_open_time[i] --;
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if (m_bank_open_time[i] < 0) {
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assert(0 && "Bank held open too long");
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}
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}
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}
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if (m_clocks_till_idle)
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m_clocks_till_idle--;
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if (m_fail > 0) {
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m_fail--;
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if (m_fail == 0) {
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fprintf(stderr, "Failing on schedule\n");
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exit(-3);
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}
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}
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if ((m_clocks_till_idle > 0)&&(m_next_wr)) {
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// printf("SDRAM[%08x] <= %04x\n", m_wr_addr, data & 0x0ffff);
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m_mem[m_wr_addr++] = data;
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result = data;
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m_next_wr = false;
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}
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m_qloc = (m_qloc + 1)&m_qmask;
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result = (driv)?data:m_qdata[(m_qloc)&m_qmask];
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m_qdata[(m_qloc)&m_qmask] = 0;
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dgisselq |
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dgisselq |
// if (result != 0)
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// printf("%d RESULT[%3d] = %04x\n", clk, m_qloc, result&0x0ffff);
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if ((!cs_n)&&(!ras_n)&&(!cas_n)&&(we_n)) {
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// Auto-refresh command
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m_refresh_time[m_refresh_loc] = MAX_REFRESH_TIME;
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m_refresh_loc++;
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if (m_refresh_loc >= m_nrefresh)
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m_refresh_loc = 0;
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assert((m_bank_status[0]&6) == 0);
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assert((m_bank_status[1]&6) == 0);
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assert((m_bank_status[2]&6) == 0);
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assert((m_bank_status[3]&6) == 0);
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} else if ((!cs_n)&&(!ras_n)&&(cas_n)&&(!we_n)) {
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if (addr&0x0400) {
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// Bank/Precharge All CMD
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for(int i=0; i<NBANKS; i++)
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m_bank_status[i] &= 0x03;
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} else {
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// Precharge/close single bank
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assert(0 == (bs & (~3))); // Assert w/in bounds
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m_bank_status[bs] &= 0x03; // Close the bank
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dgisselq |
// printf("Precharging bank %d\n", bs);
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}
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} else if ((!cs_n)&&(!ras_n)&&(cas_n)&&(we_n)) {
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// printf("Activating bank %d\n", bs);
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dgisselq |
// Activate a bank!
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if (0 != (bs & (~3))) {
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m_fail = 2;
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fprintf(stderr, "ERR: Activating a bank w/ more than 2 bits\n");
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// assert(0 == (bs & (~3))); // Assert w/in bounds
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} else if (m_bank_status[bs] != 0) {
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fprintf(stderr, "ERR: Status of bank [bs=%d] = %d != 0\n",
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bs, m_bank_status[bs]);
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m_fail = 4;
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// assert(m_bank_status[bs]==0); // Assert bank was closed
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}
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m_bank_status[bs] |= 4;
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m_bank_open_time[bs] = MAX_BANKOPEN_TIME;
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m_bank_row[bs] = addr;
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} else if ((!cs_n)&&(ras_n)&&(!cas_n)) {
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dgisselq |
// printf("R/W Op\n");
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dgisselq |
if (!we_n) {
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// Initiate a write
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assert(0 == (bs & (~3))); // Assert w/in bounds
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assert(m_bank_status[bs]&1); // Assert bank is open
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m_wr_addr = m_bank_row[bs];
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m_wr_addr <<= 2;
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m_wr_addr |= bs;
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m_wr_addr <<= 9;
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m_wr_addr |= (addr & 0x01ff);
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assert(driv);
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dgisselq |
// printf("SDRAM[%08x] <= %04x\n", m_wr_addr, data & 0x0ffff);
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dgisselq |
m_mem[m_wr_addr++] = data;
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m_clocks_till_idle = 2;
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m_next_wr = true;
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if (addr & 0x0400) { // Auto precharge
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m_bank_status[bs] &= 3;
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m_bank_open_time[bs] = MAX_BANKOPEN_TIME;
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}
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} else { // Initiate a read
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assert(0 == (bs & (~3))); // Assert w/in bounds
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assert(m_bank_status[bs]&1); // Assert bank is open
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unsigned rd_addr;
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rd_addr = m_bank_row[bs] & 0x01fff;
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rd_addr <<= 2;
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rd_addr |= bs;
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rd_addr <<= 9;
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rd_addr |= (addr & 0x01ff);
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assert(!driv);
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dgisselq |
// printf("SDRAM.Q[%2d] %04x <= SDRAM[%08x]\n",
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// (m_qloc+3)&m_qmask,
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// m_mem[rd_addr] & 0x0ffff, rd_addr);
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m_qdata[(m_qloc+3)&m_qmask] = m_mem[rd_addr++];
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// printf("SDRAM.Q[%2d] %04x <= SDRAM[%08x]\n",
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// (m_qloc+4)&m_qmask,
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// m_mem[rd_addr] & 0x0ffff, rd_addr);
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m_qdata[(m_qloc+4)&m_qmask] = m_mem[rd_addr++];
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dgisselq |
m_clocks_till_idle = 2;
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if (addr & 0x0400) { // Auto precharge
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m_bank_status[bs] &= 3;
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m_bank_open_time[bs] = MAX_BANKOPEN_TIME;
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}
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}
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} else if (cs_n) {
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// Chips not asserted, DESELECT CMD equivalent of a NOOP
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} else if ((ras_n)&&(cas_n)&&(we_n)) {
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// NOOP command
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} else {
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fprintf(stderr, "Unrecognized memory command!\n");
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fprintf(stderr, "\tCS_n = %d\n", cs_n);
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fprintf(stderr, "\tRAS_n = %d\n", ras_n);
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fprintf(stderr, "\tCAS_n = %d\n", cas_n);
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fprintf(stderr, "\tWE_n = %d\n", we_n);
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assert(0 && "Unrecognizned command");
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}
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}
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return result & 0x0ffff;
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}
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