OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [bench/] [cpp/] [uartsim.h] - Blame information for rev 112

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 112 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    uartsim.h
4
//
5
// Project:     XuLA2-LX25 SoC based upon the ZipCPU
6
//
7
// Purpose:     
8
//
9
// Creator:     Dan Gisselquist, Ph.D.
10
//              Gisselquist Technology, LLC
11
//
12
////////////////////////////////////////////////////////////////////////////////
13
//
14
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
15
//
16
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// You should have received a copy of the GNU General Public License along
27
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
28
// target there if the PDF file isn't present.)  If not, see
29
// <http://www.gnu.org/licenses/> for a copy.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
#ifndef UARTSIM_H
39
#define UARTSIM_H
40
 
41
#include <stdio.h>
42
#include <stdlib.h>
43
#include <string.h>
44
#include <sys/types.h>
45
#include <sys/socket.h>
46
#include <poll.h>
47
#include <unistd.h>
48
#include <arpa/inet.h>
49
#include <signal.h>
50
 
51
#define TXIDLE  0
52
#define TXDATA  1
53
#define RXIDLE  0
54
#define RXDATA  1
55
 
56
class   UARTSIM {
57
        int     m_skt, m_con;
58
        unsigned m_setup;
59
        int     m_nparity, m_fixdp, m_evenp, m_nbits, m_nstop, m_baud_counts;
60
        int     m_rx_baudcounter, m_rx_state, m_rx_busy,
61
                m_rx_changectr, m_last_tx;
62
        int     m_tx_baudcounter, m_tx_state, m_tx_busy;
63
        unsigned        m_rx_data, m_tx_data;
64
 
65
        void    setup_listener(const int port);
66
        int     tick(const int i_tx);
67
 
68
public:
69
        UARTSIM(const int port);
70
        void    kill(void);
71
        void    setup(unsigned isetup);
72
        int     operator()(int i_tx) {
73
                return tick(i_tx); }
74
        int     operator()(int i_tx, unsigned isetup) {
75
                setup(isetup); return tick(i_tx); }
76
};
77
 
78
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.