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[/] [xulalx25soc/] [trunk/] [doc/] [wishbone.html] - Blame information for rev 116

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1 6 dgisselq 
<HTML><HEAD><TITLE>XuLA2 Wishbone Bus</TITLE></HEAD>
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<BODY>
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<h1 align=center>XuLA2 Wishbone Address Space</H1>
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<TABLE align=center>
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<TR><TH>Wishbone Address</TH><TH align=center>Words</TH><TH align=left>Usage</TH></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0000_xxxx_xxxx</TT></TD><TH align=right>256</TH><TD>Undefined Memory (Bus Error)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0000</TT></TD><TH align=right>1</TH><TD>(Reserved)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0001</TT></TD><TH align=right>1</TH><TD>Version</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0010</TT></TD><TH align=right>1</TH><TD>JTAG Accessible Interrupt Controller</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0011</TT></TD><TH align=right>1</TH><TD>Bus Error (Includes errors induced from JTAG-wishbone controller)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0100</TT></TD><TH align=right>1</TH><TD>ZipTimer</TD></TR>
12 6 dgisselq 
<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0101</TT></TD><TH align=right>1</TH><TD>RTC Date</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0110</TT></TD><TH align=right>1</TH><TD>GPIO control</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_0111</TT></TD><TH align=right>1</TH><TD>UART Control word</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_100x</TT></TD><TH align=right>2</TH><TD>PWM control</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1010</TT></TD><TH align=right>1</TH><TD>Receive UART RX value</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_1011</TT></TD><TH align=right>1</TH><TD>Transmit UART port</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0000_11xx</TT></TD><TH align=right>4</TH><TD>Flash Control Words</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_0xxx</TT></TD><TH align=right>8</TH><TD>RTC Clock</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_0000_0001_0001_1yyx</TT></TD><TH align=right>2</TH><TD>Scope #Y (0..3)</TD></TR>
21 82 dgisselq 
<TR><TD align=right><TT>0_0000_0000_0000_0001_0010_00xx</TT></TD><TH align=right>4</TH><TD>SD Card Registers: Control, Data, FIFO zero and FIFO one</TD></TR>
22 6 dgisselq 
<TR><TD align=right><TT>0_0000_0000_0000_0001_01xx_xxxx</TT></TD><TH align=right>32</TH><TD>(ICAPE Access -- not yet proven)</TD></TR>
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<TR><TD align=right><TT>0_0000_0000_001x_xxxx_xxxx_xxxx</TT></TD><TH align=right>8k</TH><TD>On Chip RAM</TD></TR>
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<TR><TD align=right><TT>0_0000_01xx_xxxx_xxxx_xxxx_xxxx</TT></TD><TH align=right>256k</TH><TD>1 MB SPI Flash (256kW)</TD></TR>
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<TR><TD align=right><TT>0_1rrr_rrrr_rrrr_rrbb_cccc_cccc</TT></TD><TH align=right>8M</TH><TD>32 MB SDRAM (8MW)</TD></TR>
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<TR><TD align=right><TT>1_yyyy_yyyy_yyyy_yyyy_yyyy_yyyx</TT></TD><TH align=right>2</TH><TD>External Zip CPU control (y bits are don't cares, not accessible from ZipCPU)</TD></TR>
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<!-- -->
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_xxxx</TT></TD><TH align=right>20</TH><TD>Zip System registers</TD></TR>
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<!-- -->
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0000</TT></TD><TH align=right>1</TH><TD>Zip Programmable Interrupt Controller</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0001</TT></TD><TH align=right>1</TH><TD>Watchdog Timer</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0010</TT></TD><TH align=right>1</TH><TD>Address of last bus error, as seen by the Zip CPU</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0011</TT></TD><TH align=right>1</TH><TD>Secondary Interrupt Controller</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0100</TT></TD><TH align=right>1</TH><TD>Timer A</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0101</TT></TD><TH align=right>1</TH><TD>Timer B</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0110</TT></TD><TH align=right>1</TH><TD>Timer C</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_0111</TT></TD><TH align=right>1</TH><TD>Jiffies</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1000</TT></TD><TH align=right>1</TH><TD>Master Task Clock Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1001</TT></TD><TH align=right>1</TH><TD>Master Stall Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1010</TT></TD><TH align=right>1</TH><TD>Master Pre-Fetch Stall Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1011</TT></TD><TH align=right>1</TH><TD>Master Instruction Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1100</TT></TD><TH align=right>1</TH><TD>User Task Clock Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1101</TT></TD><TH align=right>1</TH><TD>User Stall Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1110</TT></TD><TH align=right>1</TH><TD>User Pre-Fetch Stall Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0000_1111</TT></TD><TH align=right>1</TH><TD>User Instruction Counter</TD></TR>
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<TR><TD><TT>1100_0000_0000_0000_0000_0000_0001_00xx</TT></TD><TH align=right>1</TH><TD>DMA Controller</TD></TR>
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</TABLE>
48 31 dgisselq 
 
49 6 dgisselq 
<h1 align=center>Primary (ZipSystem) Interrupt Controller Assignments</H1>
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<TABLE align=center>
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<TR><TD><TH align=right>0</TH><TD>DMA controller</TD></TR>
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<TR><TD><TH align=right>1</TH><TD>Jiffies</TD></TR>
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<TR><TD><TH align=right>2</TH><TD>Timer C</TD></TR>
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<TR><TD><TH align=right>3</TH><TD>Timer B</TD></TR>
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<TR><TD><TH align=right>4</TH><TD>Timer A</TD></TR>
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<TR><TD><TH align=right>5</TH><TD>Secondary Interrupt Controller</TD></TR>
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<TR><TD><TH align=right>6</TH><TD>JTAG Accessible Interrupt Controller</TD></TR>
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<TR><TD><TH align=right>7</TH><TD>RTC Clock</TD></TR>
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<TR><TD><TH align=right>8</TH><TD>SPI Flash</TD></TR>
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<TR><TD><TH align=right>9</TH><TD>Scope</TD></TR>
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<TR><TD><TH align=right>10</TH><TD>GPIO</TD></TR>
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<TR><TD><TH align=right>11</TH><TD>PWM</TD></TR>
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<TR><TD><TH align=right>12</TH><TD>RX UART data available (with FIFO, becomes non-empty RX FIFO not empty)</TD></TR>
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<TR><TD><TH align=right>13</TH><TD>TX UART idle (with FIFO, becomes TX FIFO empty)</TD></TR>
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<TR><TD><TH align=right>14</TH><TD>(Unused/reserved)</TD></TR>
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</TABLE>
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<h1 align=center>Secondary (ZipSystem) Interrupt Controller Assignments</H1>
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<TABLE align=center>
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<TR><TD><TH align=right>0</TH><TD>User Instruction Counter</TD></TR>
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<TR><TD><TH align=right>1</TH><TD>User Prefetch stall counter</TD></TR>
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<TR><TD><TH align=right>2</TH><TD>User stall counter</TD></TR>
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<TR><TD><TH align=right>3</TH><TD>User task counter</TD></TR>
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<TR><TD><TH align=right>4</TH><TD>Master instruction counter rollover</TD></TR>
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<TR><TD><TH align=right>5</TH><TD>Master prefetch stall counter rollover</TD></TR>
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<TR><TD><TH align=right>6</TH><TD>Master stall counter rollover</TD></TR>
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<TR><TD><TH align=right>7</TH><TD>Master task counter rollover</TD></TR>
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<TR><TD><TH align=right>8-14</TH><TD>(Unused / reserved)</TD></TR>
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</TABLE>
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<h1 align=center>JTAG Accessible Interrupt Controller Assignments</H1>
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<TABLE align=center>
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<TR><TD><TH align=right>0</TH><TD>Zip CPU Halted</TD></TR>
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<TR><TD><TH align=right>1</TH><TD>RTC Clock</TD></TR>
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<TR><TD><TH align=right>2</TH><TD>SPI Flash</TD></TR>
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<TR><TD><TH align=right>3</TH><TD>Scope</TD></TR>
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<TR><TD><TH align=right>4</TH><TD>GPIO</TD></TR>
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<TR><TD><TH align=right>5</TH><TD>PWM</TD></TR>
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<TR><TD><TH align=right>6</TH><TD>RX UART</TD></TR>
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<TR><TD><TH align=right>7</TH><TD>TX UART</TD></TR>
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<TR><TD><TH align=right>8</TH><TD>Bus Timer (A Zip Timer, just on the bus)</TD></TR>
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<TR><TD><TH align=right>9-14</TH><TD>(Unused / reserved)</TD></TR>
91 6 dgisselq 
</TABLE>
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</BODY></HTML>

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