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[/] [xulalx25soc/] [trunk/] [rtl/] [busmaster.v] - Blame information for rev 21

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    busmaster.v
4
//
5
// Project:     XuLA2 board
6
//
7
// Purpose:     This is the highest level, Verilator simulatable, portion of
8
//              the XuLA2 core.  You should be able to successfully Verilate 
9
//      this file, and then build a test bench that tests and proves the
10
//      capability of anything within here.
11
//
12
//      In general, this means the file is little more than a wishbone
13
//      interconnect that connects multiple devices together.  User-JTAG
14
//      commands come in via i_rx_stb and i_rx_data.  These are converted into
15
//      wishbone bus interactions, the results of which come back out via
16
//      o_tx_data and o_tx_stb.
17
//
18
//
19
// Creator:     Dan Gisselquist, Ph.D.
20
//              Gisselquist Technology, LLC
21
//
22
///////////////////////////////////////////////////////////////////////////
23
//
24
// Copyright (C) 2015, Gisselquist Technology, LLC
25
//
26
// This program is free software (firmware): you can redistribute it and/or
27
// modify it under the terms of  the GNU General Public License as published
28
// by the Free Software Foundation, either version 3 of the License, or (at
29
// your option) any later version.
30
//
31
// This program is distributed in the hope that it will be useful, but WITHOUT
32
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
33
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
34
// for more details.
35
//
36
// License:     GPL, v3, as defined and found on www.gnu.org,
37
//              http://www.gnu.org/licenses/gpl.html
38
//
39
//
40
///////////////////////////////////////////////////////////////////////////
41
//
42
`define INCLUDE_ZIPCPU
43
// `define      NO_ZIP_WBU_DELAY
44
`define IMPLEMENT_ONCHIP_RAM
45
`define FANCY_ICAP_ACCESS
46
`define FLASH_ACCESS
47 18 dgisselq
// `define SDCARD_ACCESS        // Not built yet ...
48
//
49
//
50 2 dgisselq
// `define      FLASH_SCOPE
51 18 dgisselq
`ifdef  FANCY_ICAP_ACCESS
52 9 dgisselq
`define CFG_SCOPE
53 18 dgisselq
`endif
54 9 dgisselq
// `define      SDRAM_SCOPE
55 2 dgisselq
`define ZIP_SCOPE
56
module  busmaster(i_clk, i_rst,
57
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
58
                // The SPI Flash lines
59
                o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
60
                // The SDRAM lines
61
                o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n,
62
                        o_ram_we_n, o_ram_bs, o_ram_addr,
63
                        o_ram_drive_data, i_ram_data, o_ram_data,
64
                        o_ram_dqm,
65
                // Generic GPIO
66
                i_gpio, o_gpio, o_pwm,
67
                i_rx_uart, o_tx_uart);
68
        parameter       ZIP_ADDRESS_WIDTH=24, NGPO=15, NGPI=15,
69
                        ZA=ZIP_ADDRESS_WIDTH;
70
        input                   i_clk, i_rst;
71
        // The bus commander, via an external JTAG port
72
        input                   i_rx_stb;
73
        input           [7:0]    i_rx_data;
74
        output  wire            o_tx_stb;
75
        output  wire    [7:0]    o_tx_data;
76
        input                   i_tx_busy;
77
        // SPI flash control
78
        output  wire            o_sf_cs_n, o_sd_cs_n;
79
        output  wire            o_spi_sck, o_spi_mosi;
80
        input                   i_spi_miso;
81
        // SDRAM control
82
        output  wire            o_ram_cs_n, o_ram_cke;
83
        output  wire            o_ram_ras_n, o_ram_cas_n, o_ram_we_n;
84
        output  wire    [12:0]   o_ram_addr;
85
        output  wire    [1:0]    o_ram_bs;
86
        output  wire            o_ram_drive_data;
87
        input           [15:0]   i_ram_data;
88
        output  wire    [15:0]   o_ram_data;
89
        output  wire    [1:0]    o_ram_dqm;
90
        input   [(NGPI-1):0]     i_gpio;
91
        output wire [(NGPO-1):0] o_gpio;
92
        output  wire            o_pwm;
93
        input                   i_rx_uart;
94
        output  wire            o_tx_uart;
95
 
96
 
97
        //
98
        //
99
        // Master wishbone wires
100
        //
101
        //
102
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
103
        wire    [31:0]   wb_data, wb_idata, wb_addr;
104
 
105
        //
106
        //
107
        // First BUS master source: The JTAG
108
        //
109
        //
110
        wire    [31:0]   dwb_idata;
111
 
112
        // Wires going to devices
113
        wire            wbu_cyc, wbu_stb, wbu_we;
114
        wire    [31:0]   wbu_addr, wbu_data;
115
        // and then coming from devices
116
        wire            wbu_ack, wbu_stall, wbu_err;
117
        wire    [31:0]   wbu_idata;
118
        // And then headed back home
119
        wire    w_interrupt;
120
        // Oh, and the debug control for the ZIP CPU
121
        wire            wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
122 9 dgisselq
        assign  wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
123 2 dgisselq
        wire    [31:0]   zip_dbg_data;
124
        wbubus  genbus(i_clk, i_rx_stb, i_rx_data,
125
                        wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
126
`ifdef  INCLUDE_ZIPCPU
127
                        ((~wbu_zip_sel)&&(wbu_ack))
128
                                ||((wbu_zip_sel)&&(zip_dbg_ack)),
129
                        ((~wbu_zip_sel)&&(wbu_stall))
130
                                ||((wbu_zip_sel)&&(zip_dbg_stall)),
131
                                wbu_err, (wbu_zip_sel)?zip_dbg_data:dwb_idata,
132
`else
133
                        wbu_ack, wbu_stall,
134
                                wbu_err, dwb_idata,
135
`endif
136
                        w_interrupt,
137
                        o_tx_stb, o_tx_data, i_tx_busy);
138
 
139
 
140
        //
141
        //
142
        // Second BUS master source: The ZipCPU
143
        //
144
        //
145
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
146
        wire    [(ZA-1):0]       w_zip_addr;
147
        wire    [31:0]   zip_addr, zip_data;
148
        // and then coming from devices
149
        wire            zip_ack, zip_stall, zip_err;
150
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
151
        wire    [31:0]   dwb_addr, dwb_odata;
152
        wire    [7:0]    w_ints_to_zip_cpu;
153
`ifdef  INCLUDE_ZIPCPU
154
        wire    [31:0]   zip_debug;
155
        zipsystem #(24'h2000,ZA,8,1,8)
156
                zippy(i_clk, 1'b0,
157
                        // Zippys wishbone interface
158
                        zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
159
                                zip_ack, zip_stall, dwb_idata, zip_err,
160
                        w_ints_to_zip_cpu, zip_cpu_int,
161
                        // Debug wishbone interface
162
                        ((wbu_cyc)&&(wbu_zip_sel)),
163
                                ((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
164
                                wbu_data,
165
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
166
                        zip_debug);
167
        generate
168
        if (ZA < 32)
169
                assign  zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
170
        else
171
                assign  zip_addr = w_zip_addr;
172
        endgenerate
173
 
174
 
175
        //
176
        //
177
        // And an arbiter to decide who gets to access the bus
178
        //
179
        //
180
        /*
181
        wbarbiter #(32,32) wbu_zip_arbiter(i_clk, i_rst,
182
                // The UART interface Master
183
                wbu_addr, wbu_data, wbu_we, (wbu_stb)&&(~wbu_zip_sel),
184
                        (wbu_cyc)&&(~wbu_zip_sel), wbu_ack, wbu_stall, wbu_err,
185
                // The ZIP CPU Master
186
                zip_addr, zip_data, zip_we, zip_stb,
187
                        zip_cyc, zip_ack, zip_stall, zip_err,
188
                // Common bus returns
189
                dwb_addr,dwb_odata,dwb_we,dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err);
190
        */
191
        wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
192
                // The ZIP CPU Master -- gets priority in the arbiter
193
                zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
194
                        zip_ack, zip_stall, zip_err,
195
                // The JTAG interface Master, secondary priority,
196
                // will suffer a 1clk delay in arbitration
197
                (wbu_cyc)&&(~wbu_zip_sel), (wbu_stb)&&(~wbu_zip_sel), wbu_we,
198
                        wbu_addr, wbu_data,
199
                        wbu_ack, wbu_stall, wbu_err,
200
                // Common bus returns
201
                dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
202
                        dwb_ack, dwb_stall, dwb_err);
203
 
204
`else
205
        assign  zip_cyc = 1'b0;
206
        assign  zip_stb = 1'b0;
207
        assign  zip_we  = 1'b0;
208
        assign  zip_cpu_int = 1'b0;
209
        assign  zip_addr = 32'h000;
210
        assign  zip_data = 32'h000;
211
 
212
        reg     r_zip_dbg_ack;
213
        initial r_zip_dbg_ack = 1'b0;
214
        always @(posedge i_clk)
215
                r_zip_dbg_ack <= ((wbu_cyc)&&(wbu_zip_sel)&(wbu_stb));
216
        assign  zip_dbg_ack = r_zip_dbg_ack;
217
        assign  zip_dbg_stall = 1'b0;
218
        assign  zip_dbg_data = 32'h000;
219
 
220
        assign  dwb_addr = wbu_addr;
221
        assign  dwb_odata = wbu_data;
222
        assign  dwb_we = wbu_we;
223
        assign  dwb_stb = (wbu_stb);
224
        assign  dwb_cyc = (wbu_cyc);
225
        assign  wbu_ack = dwb_ack;
226
        assign  wbu_stall = dwb_stall;
227
        assign  dwb_idata = wb_idata;
228
        assign  wbu_err = dwb_err;
229
`endif
230
 
231
 
232
        // 
233
        // 
234
        // And because the ZIP CPU and the Arbiter create an unacceptable
235
        // delay, we fail timing.  So we add in a delay cycle ...
236
        // 
237
        // 
238
`ifdef  NO_ZIP_WBU_DELAY
239
        assign  wb_cyc    = dwb_cyc;
240
        assign  wb_stb    = dwb_stb;
241
        assign  wb_we     = dwb_we;
242
        assign  wb_addr   = dwb_addr;
243
        assign  wb_data   = dwb_odata;
244
        assign  dwb_idata = wb_idata;
245
        assign  dwb_ack   = wb_ack;
246
        assign  dwb_stall = wb_stall;
247
        assign  dwb_err   = wb_err;
248
`else
249
        busdelay        wbu_zip_delay(i_clk,
250
                        dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
251
                                dwb_ack, dwb_stall, dwb_idata, dwb_err,
252
                        wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
253
                                wb_ack, wb_stall, wb_idata, wb_err);
254
`endif
255
 
256
 
257
 
258
        wire    io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel,
259
                        cfg_sel, mem_sel, sdram_sel, sdcard_sel,
260
                        none_sel, many_sel, io_bank;
261
        wire    io_ack, flash_ack, scop_ack, cfg_ack, mem_ack,
262
                        sdram_ack, sdcard_ack, uart_ack, pwm_ack;
263
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall,
264
                        sdram_stall, sdcard_stall, uart_stall, pwm_stall;
265
 
266
        wire    [31:0]   io_data, flash_data, scop_data, cfg_data, mem_data,
267
                        sdram_data, sdcard_data, uart_data, pwm_data;
268
        reg     [31:0]   bus_err_addr;
269
 
270
        assign  wb_ack = (wb_cyc)&&((io_ack)||(uart_ack)||(pwm_ack)
271
                                ||(scop_ack)||(cfg_ack)
272
                                ||(mem_ack)||(flash_ack)||(sdram_ack)
273
                                ||(sdcard_ack)
274
                                ||((none_sel)&&(1'b1)));
275
        assign  wb_stall = ((io_sel)&&(io_stall))
276
                        ||((uart_sel)&&(uart_stall))
277
                        ||((pwm_sel)&&(pwm_stall))
278
                        ||((scop_sel)&&(scop_stall))
279
                        ||((cfg_sel)&&(cfg_stall))
280
                        ||((mem_sel)&&(mem_stall))
281
                        ||((sdram_sel)&&(sdram_stall))
282
                        ||((sdcard_sel)&&(sdcard_stall))
283
                        ||((flash_sel||flctl_sel)&&(flash_stall));
284
                        // (none_sel)&&(1'b0)
285
 
286
        /*
287
        assign  wb_idata = (io_ack)?io_data
288
                        : ((scop_ack)?scop_data
289
                        : ((cfg_ack)?cfg_data
290
                        : ((mem_ack)?mem_data
291
                        : ((flash_ack)?flash_data
292
                        : 32'h00))));
293
        */
294
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
295
                        : ((uart_ack|pwm_ack)?((uart_ack)?uart_data: pwm_data)
296
                        : ((cfg_ack) ? cfg_data
297
                        : ((sdram_ack|sdcard_ack)
298
                                        ?((sdram_ack)? sdram_data : sdcard_data)
299
                        : ((mem_ack)?mem_data:flash_data)))); // if (flash_ack)
300
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
301
 
302
        // Addresses ...
303
        //      0000 xxxx       configuration/control registers
304
        //      001x xxxx       Down-sampler taps       (64 taps, 2 at a time)
305
        //      1xxx xxxx       Up-sampler taps
306
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
307
        assign  io_bank  = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
308
        assign  io_sel   = (io_bank)&&(~flctl_sel)
309
                                &&(~pwm_sel)&&(~uart_sel)&&(~scop_sel);
310
        assign  pwm_sel  =((io_bank)&&(wb_addr[4: 1]== 4'h4));
311
        assign  uart_sel =((io_bank)&&((wb_addr[4:1]== 4'h5)||(wb_addr[4:0]==5'h7)));
312
        assign  flctl_sel=((io_bank)&&(wb_addr[4: 2]== 3'h3));
313
        assign  scop_sel =((io_bank)&&(wb_addr[4: 3]== 2'h3));
314
        assign  cfg_sel  =((wb_cyc)&&(wb_addr[31: 6]== 26'h05));
315
        // zip_sel is not on the bus at this point
316
        assign  mem_sel  =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
317
        assign  flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
318
        assign  sdcard_sel=1'b0;
319
        assign  sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
320
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(~(io_sel||flctl_sel||scop_sel||cfg_sel||mem_sel||sdram_sel||sdcard_sel||flash_sel)));
321
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
322
                         {3'h0, io_sel}
323
                        +{3'h0, uart_sel}
324
                        +{3'h0, pwm_sel}
325
                        +{3'h0, flctl_sel}
326
                        +{3'h0, scop_sel}
327
                        +{3'h0, cfg_sel}
328
                        +{3'h0, mem_sel}
329
                        +{3'h0, sdram_sel}
330
                        +{3'h0, sdcard_sel}
331
                        +{3'h0, flash_sel} > 1));
332
 
333
        wire    many_ack;
334
        assign  many_ack =((wb_cyc)&&(
335
                         {3'h0, io_ack}
336
                        +{3'h0, uart_ack}
337
                        +{3'h0, pwm_ack}
338
                        +{3'h0, scop_ack}
339
                        +{3'h0, cfg_ack}
340
                        +{3'h0, mem_ack}
341
                        +{3'h0, sdram_ack}
342
                        +{3'h0, sdcard_ack}
343
                        +{3'h0, flash_ack} > 1));
344
 
345
        always @(posedge i_clk)
346
                if (wb_err)
347
                        bus_err_addr <= wb_addr;
348
 
349
        wire            flash_interrupt, scop_interrupt,
350
                        uart_rx_int, uart_tx_int, pwm_int;
351
        // The I/O processor, herein called an ioslave
352
        ioslave #(NGPO, NGPI) runio(i_clk,
353
                        wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
354
                                wb_data, io_ack, io_stall, io_data,
355
                        i_gpio, o_gpio,
356
                        bus_err_addr,
357
                        { uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
358
                                flash_interrupt, zip_cpu_int },
359
                        w_ints_to_zip_cpu,
360
                        w_interrupt);
361
                // 8684
362
                // 1'bx, 4'h0, scop_sel, scop_ack, ~scop_stall, 
363
                //      wb_err, ~vga_interrupt, 2'b00, flash_interrupt
364
        //
365
 
366
        //
367
        //      UART device
368
        //
369
        uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
370
                        wb_cyc, (wb_stb)&&(uart_sel), wb_we,
371 9 dgisselq
                                        { ~wb_addr[2], wb_addr[0]}, wb_data,
372
                        uart_ack, uart_stall, uart_data,
373 2 dgisselq
                        uart_rx_int, uart_tx_int);
374
 
375
        //
376
        //      PWM (audio) device
377
        //
378
        wbpwmaudio      pwmdev(i_clk,
379
                        wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
380
                        wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
381
 
382
 
383
        //
384
        //      FLASH MEMORY CONFIGURATION ACCESS
385
        //
386
        wire    flash_cs_n, flash_sck, flash_mosi;
387
`ifdef  FLASH_ACCESS
388
        wbspiflash      flashmem(i_clk,
389
                wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
390
                        wb_addr[17:0], wb_data,
391
                flash_ack, flash_stall, flash_data,
392
                flash_sck, flash_cs_n, o_sf_cs_n, flash_mosi, i_spi_miso,
393
                flash_interrupt);
394
`else
395
        reg     r_flash_ack;
396
        initial r_flash_ack = 1'b0;
397
        always @(posedge i_clk)
398
                r_flash_ack <= (wb_cyc)&&(wb_stb)&&((flash_sel)||(flctl_sel));
399
 
400
        assign  flash_ack = r_flash_ack;
401
        assign  flash_stall = 1'b0;
402
        assign  flash_data = 32'h0000;
403
        assign  flash_interrupt = 1'b0;
404
 
405
        assign  flash_cs_n = 1'b1;
406
        assign  flash_sck  = 1'b1;
407
        assign  flash_mosi = 1'b1;
408
 
409
        This is an error
410
`endif
411
 
412
`ifdef  FLASH_ACCESS
413
`ifdef  SDCARD_ACCESS
414
        spiarbiter      spichk(i_clk,
415
                flash_cs_n, flash_sck, flash_mosi,
416
                sdcard_cs_n, sdcard_sck, sdcard_mosi,
417
                o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi);
418
        This is an error
419
`else
420
        // Flash access, but no SD card access
421
        assign  o_sf_cs_n  = flash_cs_n;
422
        assign  o_sd_cs_n  = 1'b1;
423
        assign  o_spi_sck  = flash_sck;
424
        assign  o_spi_mosi = flash_mosi;
425
`endif // SDCARD_ACCESS && FLASH_ACCESS
426
`else // FLASH_ACCESS
427
`ifdef  SDCARD_ACCESS
428
        // SDCard access, but no flash access
429
        assign  o_sf_cs_n  = 1'b1;
430
        assign  o_sd_cs_n  = sdcard_cs_n;
431
        assign  o_spi_sck  = sdcard_sck;
432
        assign  o_spi_mosi = sdcard_mosi;
433
`else
434
        // No SPI access ...
435
        assign  o_sf_cs_n  = 1'b1;
436
        assign  o_sd_cs_n  = 1'b1;
437
        assign  o_spi_sck  = 1'b1;
438
        assign  o_spi_mosi = 1'b1;
439
`endif // SDCARD_ACCESS, w/o FLASH_ACCESS
440
`endif // !FLASH_ACCESS
441
 
442
 
443
        //
444
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
445
        //
446
        wire    [31:0]   cfg_scope;
447
`ifdef  FANCY_ICAP_ACCESS
448
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
449
                                wb_addr[5:0], wb_data,
450
                                cfg_ack, cfg_stall, cfg_data,
451
                                cfg_scope);
452
`else
453
        assign  cfg_scope = 32'h0000;
454
        reg     r_cfg_ack;
455
        initial r_cfg_ack = 1'b0;
456
        always @(posedge i_clk)
457
                r_cfg_ack <= ((wb_cyc)&&(cfg_sel)&&(wb_stb)&&(~cfg_stall));
458
        assign  cfg_ack = r_cfg_ack;
459
        assign  cfg_stall = 1'b0;
460
        assign  cfg_data = 32'h0000;
461
`endif
462
 
463
 
464
        //
465
        //      RAM MEMORY ACCESS
466
        //
467
`ifdef  IMPLEMENT_ONCHIP_RAM
468
        memdev  #(13) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
469
                        wb_addr[12:0], wb_data, mem_ack, mem_stall, mem_data);
470
`else
471
        reg     r_mem_ack;
472
        always @(posedge i_clk)
473
                r_mem_ack = (wb_cyc)&&(wb_stb)&&(mem_sel);
474
        assign  mem_data = 32'h000;
475
        assign  mem_stall = 1'b0;
476
        assign  mem_ack = r_mem_ack;
477
`endif
478
 
479
 
480
        //
481
        //      SDRAM Memory Access
482
        //
483
        wire    [31:0]   sdram_debug;
484
`ifndef BYPASS_SDRAM_ACCESS
485
        wbsdram sdram(i_clk,
486
                wb_cyc, (wb_stb)&&(sdram_sel),
487
                        wb_we, wb_addr[22:0], wb_data,
488
                        sdram_ack, sdram_stall, sdram_data,
489
                o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n, o_ram_we_n,
490
                        o_ram_bs, o_ram_addr,
491
                        o_ram_drive_data, i_ram_data, o_ram_data, o_ram_dqm,
492
                sdram_debug);
493
`else
494
        reg     r_sdram_ack;
495
        initial r_sdram_ack = 1'b0;
496
        always @(posedge i_clk)
497
                r_sdram_ack <= (wb_cyc)&&(wb_stb)&&(sdram_sel);
498
        assign  sdram_ack = r_sdram_ack;
499
        assign  sdram_stall = 1'b0;
500
        assign  sdram_data = 32'h0000;
501
 
502
        assign  o_ram_ce_n  = 1'b1;
503
        assign  o_ram_ras_n = 1'b1;
504
        assign  o_ram_cas_n = 1'b1;
505
        assign  o_ram_we_n  = 1'b1;
506
 
507
        assign  sdram_debug = 32'h0000;
508
`endif
509
 
510
        //
511
        //
512
        //      WISHBONE SCOPES
513
        //
514
        //
515
        //
516
        //
517
`ifdef  FLASH_SCOPE
518
        reg     [31:0]   r_flash_debug, last_flash_debug;
519
        wire    [31:0]   scop_flash_data;
520
        wire    scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
521
        always @(posedge i_clk)
522
                r_flash_debug <= flash_debug;
523
        always @(posedge i_clk)
524
                last_flash_debug <= r_flash_debug;
525
        wbscope spiscope(i_clk, 1'b1, (~o_spi_cs_n), r_flash_debug,
526
                // Wishbone interface
527
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
528
                        wb_data,
529
                        scop_flash_ack, scop_flash_stall, scop_flash_data,
530
                scop_flash_interrupt);
531
`else
532
        wire    [31:0]   scop_flash_data;
533
        wire    scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
534
        assign  scop_flash_data = 32'h00;
535
        assign  scop_flash_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
536
        assign scop_flash_stall = 1'b0;
537
        assign scop_flash_interrupt = 1'b0;
538
`endif
539
 
540
 
541
        wire    [31:0]   scop_cfg_data;
542
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
543
`ifdef  CFG_SCOPE
544
        wire            scop_cfg_trigger;
545
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
546 18 dgisselq
        wbscope #(5'h7) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
547 2 dgisselq
                // Wishbone interface
548
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
549
                                wb_we, wb_addr[0], wb_data,
550
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
551
                scop_cfg_interrupt);
552
`else
553
        assign  scop_cfg_data = 32'h00;
554
        assign  scop_cfg_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01);
555
        assign  scop_cfg_stall = 1'b0;
556
        assign  scop_cfg_interrupt = 1'b0;
557
`endif
558
 
559
        wire    [31:0]   scop_ram_data;
560
        wire            scop_ram_ack, scop_ram_stall, scop_ram_interrupt;
561
`ifdef  SDRAM_SCOPE
562
        wire            sdram_trigger;
563
        assign  sdram_trigger = sdram_sel;
564
        // assign sdram_trigger = ((wbu_cyc)&&(wbu_zip_sel)&&(wbu_stb)&&(~wbu_addr[0])),
565
        wire    sdram_write;
566
        assign  sdram_write = ((wb_cyc)&&(sdram_sel)&&(wb_stb)&&(wb_we)&&(~sdram_stall));
567
        /*
568
        reg     r_trigger;
569
        reg     [31:0]  last_data;
570
        always @(posedge i_clk)
571
                if (sdram_write)
572
                        last_data <= wb_data;
573
        initial r_trigger = 1'b0;
574
        always @(posedge i_clk)
575
                if ((sdram_write)&&(last_data == wb_data))
576
                        r_trigger <= 1'b1;
577
                else
578
                        r_trigger <= 1'b0;
579
        */
580
 
581 9 dgisselq
        wbscope #(5'ha) sdramscope(i_clk, 1'b1, sdram_trigger,
582 2 dgisselq
                        sdram_debug,
583
                        // zip_debug,
584
                // Wishbone interface
585
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
586
                        wb_data,
587
                        scop_ram_ack, scop_ram_stall, scop_ram_data,
588
                scop_ram_interrupt);
589
`else
590
        assign  scop_ram_data = 32'h00;
591
        assign  scop_ram_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10);
592
        assign  scop_ram_stall = 1'b0;
593
        assign  scop_ram_interrupt = 1'b0;
594
`endif
595
 
596
        wire    [31:0]   scop_zip_data;
597
        wire            scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
598
`ifdef  ZIP_SCOPE
599
        wire            zip_trigger;
600
        assign  zip_trigger=(wbu_zip_sel)&&(wbu_we)&&(wbu_stb)&&(~wbu_addr[0]);
601 9 dgisselq
        wbscope #(5'ha) zipscope(i_clk, 1'b1, zip_trigger,
602 2 dgisselq
                        zip_debug,
603
                // Wishbone interface
604
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
605
                        wb_data,
606
                        scop_zip_ack, scop_zip_stall, scop_zip_data,
607
                scop_zip_interrupt);
608
`else
609
        assign  scop_zip_data = 32'h00;
610
        assign  scop_zip_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11);
611
        assign  scop_zip_stall = 1'b0;
612
        assign  scop_zip_interrupt = 1'b0;
613
`endif
614
 
615
 
616
        assign  scop_interrupt = scop_flash_interrupt || scop_cfg_interrupt
617
                                || scop_ram_interrupt || scop_zip_interrupt;
618
        assign  scop_ack   = scop_cfg_ack | scop_flash_ack | scop_ram_ack | scop_zip_ack;
619
        assign  scop_stall = ((~wb_addr[2])?
620
                                ((wb_addr[1])?scop_flash_stall:scop_cfg_stall)
621
                                : ((wb_addr[1])?scop_ram_stall:scop_zip_stall));
622
        assign  scop_data  = ((scop_cfg_ack)?scop_cfg_data
623
                                : ((scop_flash_ack) ? scop_flash_data
624
                                : ((scop_ram_ack) ? scop_ram_data
625
                                : scop_zip_data)));
626
 
627
 
628
        reg     r_sdcard_ack;
629
        initial r_sdcard_ack = 1'b0;
630
        always @(posedge i_clk)
631
                r_sdcard_ack <= (wb_cyc)&&(wb_stb)&&(sdcard_sel);
632
        assign  sdcard_stall = 1'b0;
633
        assign  sdcard_ack = r_sdcard_ack;
634
        assign  sdcard_data = 32'h0000;
635
endmodule
636
 
637
// 0x8684 interrupts ...???

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