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[/] [xulalx25soc/] [trunk/] [rtl/] [busmaster.v] - Blame information for rev 6

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    busmaster.v
4
//
5
// Project:     XuLA2 board
6
//
7
// Purpose:     This is the highest level, Verilator simulatable, portion of
8
//              the XuLA2 core.  You should be able to successfully Verilate 
9
//      this file, and then build a test bench that tests and proves the
10
//      capability of anything within here.
11
//
12
//      In general, this means the file is little more than a wishbone
13
//      interconnect that connects multiple devices together.  User-JTAG
14
//      commands come in via i_rx_stb and i_rx_data.  These are converted into
15
//      wishbone bus interactions, the results of which come back out via
16
//      o_tx_data and o_tx_stb.
17
//
18
//
19
// Creator:     Dan Gisselquist, Ph.D.
20
//              Gisselquist Technology, LLC
21
//
22
///////////////////////////////////////////////////////////////////////////
23
//
24
// Copyright (C) 2015, Gisselquist Technology, LLC
25
//
26
// This program is free software (firmware): you can redistribute it and/or
27
// modify it under the terms of  the GNU General Public License as published
28
// by the Free Software Foundation, either version 3 of the License, or (at
29
// your option) any later version.
30
//
31
// This program is distributed in the hope that it will be useful, but WITHOUT
32
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
33
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
34
// for more details.
35
//
36
// License:     GPL, v3, as defined and found on www.gnu.org,
37
//              http://www.gnu.org/licenses/gpl.html
38
//
39
//
40
///////////////////////////////////////////////////////////////////////////
41
//
42
`define INCLUDE_ZIPCPU
43
// `define      NO_ZIP_WBU_DELAY
44
`define IMPLEMENT_ONCHIP_RAM
45
`define FANCY_ICAP_ACCESS
46
`define FLASH_ACCESS
47
// `define      FLASH_SCOPE
48
// `define      CFG_SCOPE
49
`define SDRAM_SCOPE
50
`define ZIP_SCOPE
51
// `define SDCARD_ACCESS
52
module  busmaster(i_clk, i_rst,
53
                i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
54
                // The SPI Flash lines
55
                o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
56
                // The SDRAM lines
57
                o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n,
58
                        o_ram_we_n, o_ram_bs, o_ram_addr,
59
                        o_ram_drive_data, i_ram_data, o_ram_data,
60
                        o_ram_dqm,
61
                // Generic GPIO
62
                i_gpio, o_gpio, o_pwm,
63
                i_rx_uart, o_tx_uart);
64
        parameter       ZIP_ADDRESS_WIDTH=24, NGPO=15, NGPI=15,
65
                        ZA=ZIP_ADDRESS_WIDTH;
66
        input                   i_clk, i_rst;
67
        // The bus commander, via an external JTAG port
68
        input                   i_rx_stb;
69
        input           [7:0]    i_rx_data;
70
        output  wire            o_tx_stb;
71
        output  wire    [7:0]    o_tx_data;
72
        input                   i_tx_busy;
73
        // SPI flash control
74
        output  wire            o_sf_cs_n, o_sd_cs_n;
75
        output  wire            o_spi_sck, o_spi_mosi;
76
        input                   i_spi_miso;
77
        // SDRAM control
78
        output  wire            o_ram_cs_n, o_ram_cke;
79
        output  wire            o_ram_ras_n, o_ram_cas_n, o_ram_we_n;
80
        output  wire    [12:0]   o_ram_addr;
81
        output  wire    [1:0]    o_ram_bs;
82
        output  wire            o_ram_drive_data;
83
        input           [15:0]   i_ram_data;
84
        output  wire    [15:0]   o_ram_data;
85
        output  wire    [1:0]    o_ram_dqm;
86
        input   [(NGPI-1):0]     i_gpio;
87
        output wire [(NGPO-1):0] o_gpio;
88
        output  wire            o_pwm;
89
        input                   i_rx_uart;
90
        output  wire            o_tx_uart;
91
 
92
 
93
        //
94
        //
95
        // Master wishbone wires
96
        //
97
        //
98
        wire            wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
99
        wire    [31:0]   wb_data, wb_idata, wb_addr;
100
 
101
        //
102
        //
103
        // First BUS master source: The JTAG
104
        //
105
        //
106
        wire    [31:0]   dwb_idata;
107
 
108
        // Wires going to devices
109
        wire            wbu_cyc, wbu_stb, wbu_we;
110
        wire    [31:0]   wbu_addr, wbu_data;
111
        // and then coming from devices
112
        wire            wbu_ack, wbu_stall, wbu_err;
113
        wire    [31:0]   wbu_idata;
114
        // And then headed back home
115
        wire    w_interrupt;
116
        // Oh, and the debug control for the ZIP CPU
117
        wire            wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
118 6 dgisselq
        assign  wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]);
119 2 dgisselq
        wire    [31:0]   zip_dbg_data;
120
        wbubus  genbus(i_clk, i_rx_stb, i_rx_data,
121
                        wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
122
`ifdef  INCLUDE_ZIPCPU
123
                        ((~wbu_zip_sel)&&(wbu_ack))
124
                                ||((wbu_zip_sel)&&(zip_dbg_ack)),
125
                        ((~wbu_zip_sel)&&(wbu_stall))
126
                                ||((wbu_zip_sel)&&(zip_dbg_stall)),
127
                                wbu_err, (wbu_zip_sel)?zip_dbg_data:dwb_idata,
128
`else
129
                        wbu_ack, wbu_stall,
130
                                wbu_err, dwb_idata,
131
`endif
132
                        w_interrupt,
133
                        o_tx_stb, o_tx_data, i_tx_busy);
134
 
135
 
136
        //
137
        //
138
        // Second BUS master source: The ZipCPU
139
        //
140
        //
141
        wire            zip_cyc, zip_stb, zip_we, zip_cpu_int;
142
        wire    [(ZA-1):0]       w_zip_addr;
143
        wire    [31:0]   zip_addr, zip_data;
144
        // and then coming from devices
145
        wire            zip_ack, zip_stall, zip_err;
146
        wire    dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
147
        wire    [31:0]   dwb_addr, dwb_odata;
148
        wire    [7:0]    w_ints_to_zip_cpu;
149
`ifdef  INCLUDE_ZIPCPU
150
        wire    [31:0]   zip_debug;
151
        zipsystem #(24'h2000,ZA,8,1,8)
152
                zippy(i_clk, 1'b0,
153
                        // Zippys wishbone interface
154
                        zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
155
                                zip_ack, zip_stall, dwb_idata, zip_err,
156
                        w_ints_to_zip_cpu, zip_cpu_int,
157
                        // Debug wishbone interface
158
                        ((wbu_cyc)&&(wbu_zip_sel)),
159
                                ((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
160
                                wbu_data,
161
                                zip_dbg_ack, zip_dbg_stall, zip_dbg_data,
162
                        zip_debug);
163
        generate
164
        if (ZA < 32)
165
                assign  zip_addr = { {(32-ZA){1'b0}}, w_zip_addr };
166
        else
167
                assign  zip_addr = w_zip_addr;
168
        endgenerate
169
 
170
 
171
        //
172
        //
173
        // And an arbiter to decide who gets to access the bus
174
        //
175
        //
176
        /*
177
        wbarbiter #(32,32) wbu_zip_arbiter(i_clk, i_rst,
178
                // The UART interface Master
179
                wbu_addr, wbu_data, wbu_we, (wbu_stb)&&(~wbu_zip_sel),
180
                        (wbu_cyc)&&(~wbu_zip_sel), wbu_ack, wbu_stall, wbu_err,
181
                // The ZIP CPU Master
182
                zip_addr, zip_data, zip_we, zip_stb,
183
                        zip_cyc, zip_ack, zip_stall, zip_err,
184
                // Common bus returns
185
                dwb_addr,dwb_odata,dwb_we,dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err);
186
        */
187
        wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
188
                // The ZIP CPU Master -- gets priority in the arbiter
189
                zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
190
                        zip_ack, zip_stall, zip_err,
191
                // The JTAG interface Master, secondary priority,
192
                // will suffer a 1clk delay in arbitration
193
                (wbu_cyc)&&(~wbu_zip_sel), (wbu_stb)&&(~wbu_zip_sel), wbu_we,
194
                        wbu_addr, wbu_data,
195
                        wbu_ack, wbu_stall, wbu_err,
196
                // Common bus returns
197
                dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
198
                        dwb_ack, dwb_stall, dwb_err);
199
 
200
`else
201
        assign  zip_cyc = 1'b0;
202
        assign  zip_stb = 1'b0;
203
        assign  zip_we  = 1'b0;
204
        assign  zip_cpu_int = 1'b0;
205
        assign  zip_addr = 32'h000;
206
        assign  zip_data = 32'h000;
207
 
208
        reg     r_zip_dbg_ack;
209
        initial r_zip_dbg_ack = 1'b0;
210
        always @(posedge i_clk)
211
                r_zip_dbg_ack <= ((wbu_cyc)&&(wbu_zip_sel)&(wbu_stb));
212
        assign  zip_dbg_ack = r_zip_dbg_ack;
213
        assign  zip_dbg_stall = 1'b0;
214
        assign  zip_dbg_data = 32'h000;
215
 
216
        assign  dwb_addr = wbu_addr;
217
        assign  dwb_odata = wbu_data;
218
        assign  dwb_we = wbu_we;
219
        assign  dwb_stb = (wbu_stb);
220
        assign  dwb_cyc = (wbu_cyc);
221
        assign  wbu_ack = dwb_ack;
222
        assign  wbu_stall = dwb_stall;
223
        assign  dwb_idata = wb_idata;
224
        assign  wbu_err = dwb_err;
225
`endif
226
 
227
 
228
        // 
229
        // 
230
        // And because the ZIP CPU and the Arbiter create an unacceptable
231
        // delay, we fail timing.  So we add in a delay cycle ...
232
        // 
233
        // 
234
`ifdef  NO_ZIP_WBU_DELAY
235
        assign  wb_cyc    = dwb_cyc;
236
        assign  wb_stb    = dwb_stb;
237
        assign  wb_we     = dwb_we;
238
        assign  wb_addr   = dwb_addr;
239
        assign  wb_data   = dwb_odata;
240
        assign  dwb_idata = wb_idata;
241
        assign  dwb_ack   = wb_ack;
242
        assign  dwb_stall = wb_stall;
243
        assign  dwb_err   = wb_err;
244
`else
245
        busdelay        wbu_zip_delay(i_clk,
246
                        dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
247
                                dwb_ack, dwb_stall, dwb_idata, dwb_err,
248
                        wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
249
                                wb_ack, wb_stall, wb_idata, wb_err);
250
`endif
251
 
252
 
253
 
254
        wire    io_sel, pwm_sel, uart_sel, flash_sel, flctl_sel, scop_sel,
255
                        cfg_sel, mem_sel, sdram_sel, sdcard_sel,
256
                        none_sel, many_sel, io_bank;
257
        wire    io_ack, flash_ack, scop_ack, cfg_ack, mem_ack,
258
                        sdram_ack, sdcard_ack, uart_ack, pwm_ack;
259
        wire    io_stall, flash_stall, scop_stall, cfg_stall, mem_stall,
260
                        sdram_stall, sdcard_stall, uart_stall, pwm_stall;
261
 
262
        wire    [31:0]   io_data, flash_data, scop_data, cfg_data, mem_data,
263
                        sdram_data, sdcard_data, uart_data, pwm_data;
264
        reg     [31:0]   bus_err_addr;
265
 
266
        assign  wb_ack = (wb_cyc)&&((io_ack)||(uart_ack)||(pwm_ack)
267
                                ||(scop_ack)||(cfg_ack)
268
                                ||(mem_ack)||(flash_ack)||(sdram_ack)
269
                                ||(sdcard_ack)
270
                                ||((none_sel)&&(1'b1)));
271
        assign  wb_stall = ((io_sel)&&(io_stall))
272
                        ||((uart_sel)&&(uart_stall))
273
                        ||((pwm_sel)&&(pwm_stall))
274
                        ||((scop_sel)&&(scop_stall))
275
                        ||((cfg_sel)&&(cfg_stall))
276
                        ||((mem_sel)&&(mem_stall))
277
                        ||((sdram_sel)&&(sdram_stall))
278
                        ||((sdcard_sel)&&(sdcard_stall))
279
                        ||((flash_sel||flctl_sel)&&(flash_stall));
280
                        // (none_sel)&&(1'b0)
281
 
282
        /*
283
        assign  wb_idata = (io_ack)?io_data
284
                        : ((scop_ack)?scop_data
285
                        : ((cfg_ack)?cfg_data
286
                        : ((mem_ack)?mem_data
287
                        : ((flash_ack)?flash_data
288
                        : 32'h00))));
289
        */
290
        assign  wb_idata =  (io_ack|scop_ack)?((io_ack )? io_data  : scop_data)
291
                        : ((uart_ack|pwm_ack)?((uart_ack)?uart_data: pwm_data)
292
                        : ((cfg_ack) ? cfg_data
293
                        : ((sdram_ack|sdcard_ack)
294
                                        ?((sdram_ack)? sdram_data : sdcard_data)
295
                        : ((mem_ack)?mem_data:flash_data)))); // if (flash_ack)
296
        assign  wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
297
 
298
        // Addresses ...
299
        //      0000 xxxx       configuration/control registers
300
        //      001x xxxx       Down-sampler taps       (64 taps, 2 at a time)
301
        //      1xxx xxxx       Up-sampler taps
302
        //      1 xxxx xxxx xxxx xxxx xxxx      Up-sampler taps
303
        assign  io_bank  = (wb_cyc)&&(wb_addr[31:5] == 27'h8);
304
        assign  io_sel   = (io_bank)&&(~flctl_sel)
305
                                &&(~pwm_sel)&&(~uart_sel)&&(~scop_sel);
306
        assign  pwm_sel  =((io_bank)&&(wb_addr[4: 1]== 4'h4));
307
        assign  uart_sel =((io_bank)&&((wb_addr[4:1]== 4'h5)||(wb_addr[4:0]==5'h7)));
308
        assign  flctl_sel=((io_bank)&&(wb_addr[4: 2]== 3'h3));
309
        assign  scop_sel =((io_bank)&&(wb_addr[4: 3]== 2'h3));
310
        assign  cfg_sel  =((wb_cyc)&&(wb_addr[31: 6]== 26'h05));
311
        // zip_sel is not on the bus at this point
312
        assign  mem_sel  =((wb_cyc)&&(wb_addr[31:13]== 19'h01));
313
        assign  flash_sel=((wb_cyc)&&(wb_addr[31:18]== 14'h01));
314
        assign  sdcard_sel=1'b0;
315
        assign  sdram_sel=((wb_cyc)&&(wb_addr[31:23]== 9'h01));
316
        assign  none_sel =((wb_cyc)&&(wb_stb)&&(~(io_sel||flctl_sel||scop_sel||cfg_sel||mem_sel||sdram_sel||sdcard_sel||flash_sel)));
317
        assign  many_sel =((wb_cyc)&&(wb_stb)&&(
318
                         {3'h0, io_sel}
319
                        +{3'h0, uart_sel}
320
                        +{3'h0, pwm_sel}
321
                        +{3'h0, flctl_sel}
322
                        +{3'h0, scop_sel}
323
                        +{3'h0, cfg_sel}
324
                        +{3'h0, mem_sel}
325
                        +{3'h0, sdram_sel}
326
                        +{3'h0, sdcard_sel}
327
                        +{3'h0, flash_sel} > 1));
328
 
329
        wire    many_ack;
330
        assign  many_ack =((wb_cyc)&&(
331
                         {3'h0, io_ack}
332
                        +{3'h0, uart_ack}
333
                        +{3'h0, pwm_ack}
334
                        +{3'h0, scop_ack}
335
                        +{3'h0, cfg_ack}
336
                        +{3'h0, mem_ack}
337
                        +{3'h0, sdram_ack}
338
                        +{3'h0, sdcard_ack}
339
                        +{3'h0, flash_ack} > 1));
340
 
341
        always @(posedge i_clk)
342
                if (wb_err)
343
                        bus_err_addr <= wb_addr;
344
 
345
        wire            flash_interrupt, scop_interrupt,
346
                        uart_rx_int, uart_tx_int, pwm_int;
347
        // The I/O processor, herein called an ioslave
348
        ioslave #(NGPO, NGPI) runio(i_clk,
349
                        wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
350
                                wb_data, io_ack, io_stall, io_data,
351
                        i_gpio, o_gpio,
352
                        bus_err_addr,
353
                        { uart_tx_int, uart_rx_int, pwm_int, scop_interrupt,
354
                                flash_interrupt, zip_cpu_int },
355
                        w_ints_to_zip_cpu,
356
                        w_interrupt);
357
                // 8684
358
                // 1'bx, 4'h0, scop_sel, scop_ack, ~scop_stall, 
359
                //      wb_err, ~vga_interrupt, 2'b00, flash_interrupt
360
        //
361
 
362
        //
363
        //      UART device
364
        //
365
        uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
366
                        wb_cyc, (wb_stb)&&(uart_sel), wb_we,
367
                                        { ~wb_addr[2], wb_addr[0]},
368
                        wb_data, uart_ack, uart_stall, uart_data,
369
                        uart_rx_int, uart_tx_int);
370
 
371
        //
372
        //      PWM (audio) device
373
        //
374
        wbpwmaudio      pwmdev(i_clk,
375
                        wb_cyc, (wb_stb)&&(pwm_sel), wb_we, wb_addr[0],
376
                        wb_data, pwm_ack, pwm_stall, pwm_data, o_pwm, pwm_int);
377
 
378
 
379
        //
380
        //      FLASH MEMORY CONFIGURATION ACCESS
381
        //
382
        wire    flash_cs_n, flash_sck, flash_mosi;
383
`ifdef  FLASH_ACCESS
384
        wbspiflash      flashmem(i_clk,
385
                wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
386
                        wb_addr[17:0], wb_data,
387
                flash_ack, flash_stall, flash_data,
388
                flash_sck, flash_cs_n, o_sf_cs_n, flash_mosi, i_spi_miso,
389
                flash_interrupt);
390
`else
391
        reg     r_flash_ack;
392
        initial r_flash_ack = 1'b0;
393
        always @(posedge i_clk)
394
                r_flash_ack <= (wb_cyc)&&(wb_stb)&&((flash_sel)||(flctl_sel));
395
 
396
        assign  flash_ack = r_flash_ack;
397
        assign  flash_stall = 1'b0;
398
        assign  flash_data = 32'h0000;
399
        assign  flash_interrupt = 1'b0;
400
 
401
        assign  flash_cs_n = 1'b1;
402
        assign  flash_sck  = 1'b1;
403
        assign  flash_mosi = 1'b1;
404
 
405
        This is an error
406
`endif
407
 
408
`ifdef  FLASH_ACCESS
409
`ifdef  SDCARD_ACCESS
410
        spiarbiter      spichk(i_clk,
411
                flash_cs_n, flash_sck, flash_mosi,
412
                sdcard_cs_n, sdcard_sck, sdcard_mosi,
413
                o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi);
414
        This is an error
415
`else
416
        // Flash access, but no SD card access
417
        assign  o_sf_cs_n  = flash_cs_n;
418
        assign  o_sd_cs_n  = 1'b1;
419
        assign  o_spi_sck  = flash_sck;
420
        assign  o_spi_mosi = flash_mosi;
421
`endif // SDCARD_ACCESS && FLASH_ACCESS
422
`else // FLASH_ACCESS
423
`ifdef  SDCARD_ACCESS
424
        // SDCard access, but no flash access
425
        assign  o_sf_cs_n  = 1'b1;
426
        assign  o_sd_cs_n  = sdcard_cs_n;
427
        assign  o_spi_sck  = sdcard_sck;
428
        assign  o_spi_mosi = sdcard_mosi;
429
`else
430
        // No SPI access ...
431
        assign  o_sf_cs_n  = 1'b1;
432
        assign  o_sd_cs_n  = 1'b1;
433
        assign  o_spi_sck  = 1'b1;
434
        assign  o_spi_mosi = 1'b1;
435
`endif // SDCARD_ACCESS, w/o FLASH_ACCESS
436
`endif // !FLASH_ACCESS
437
 
438
 
439
        //
440
        //      MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
441
        //
442
        wire    [31:0]   cfg_scope;
443
`ifdef  FANCY_ICAP_ACCESS
444
        wbicape6        fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
445
                                wb_addr[5:0], wb_data,
446
                                cfg_ack, cfg_stall, cfg_data,
447
                                cfg_scope);
448
`else
449
        assign  cfg_scope = 32'h0000;
450
        reg     r_cfg_ack;
451
        initial r_cfg_ack = 1'b0;
452
        always @(posedge i_clk)
453
                r_cfg_ack <= ((wb_cyc)&&(cfg_sel)&&(wb_stb)&&(~cfg_stall));
454
        assign  cfg_ack = r_cfg_ack;
455
        assign  cfg_stall = 1'b0;
456
        assign  cfg_data = 32'h0000;
457
`endif
458
 
459
 
460
        //
461
        //      RAM MEMORY ACCESS
462
        //
463
`ifdef  IMPLEMENT_ONCHIP_RAM
464
        memdev  #(13) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
465
                        wb_addr[12:0], wb_data, mem_ack, mem_stall, mem_data);
466
`else
467
        reg     r_mem_ack;
468
        always @(posedge i_clk)
469
                r_mem_ack = (wb_cyc)&&(wb_stb)&&(mem_sel);
470
        assign  mem_data = 32'h000;
471
        assign  mem_stall = 1'b0;
472
        assign  mem_ack = r_mem_ack;
473
`endif
474
 
475
 
476
        //
477
        //      SDRAM Memory Access
478
        //
479
        wire    [31:0]   sdram_debug;
480
`ifndef BYPASS_SDRAM_ACCESS
481
        wbsdram sdram(i_clk,
482
                wb_cyc, (wb_stb)&&(sdram_sel),
483
                        wb_we, wb_addr[22:0], wb_data,
484
                        sdram_ack, sdram_stall, sdram_data,
485
                o_ram_cs_n, o_ram_cke, o_ram_ras_n, o_ram_cas_n, o_ram_we_n,
486
                        o_ram_bs, o_ram_addr,
487
                        o_ram_drive_data, i_ram_data, o_ram_data, o_ram_dqm,
488
                sdram_debug);
489
`else
490
        reg     r_sdram_ack;
491
        initial r_sdram_ack = 1'b0;
492
        always @(posedge i_clk)
493
                r_sdram_ack <= (wb_cyc)&&(wb_stb)&&(sdram_sel);
494
        assign  sdram_ack = r_sdram_ack;
495
        assign  sdram_stall = 1'b0;
496
        assign  sdram_data = 32'h0000;
497
 
498
        assign  o_ram_ce_n  = 1'b1;
499
        assign  o_ram_ras_n = 1'b1;
500
        assign  o_ram_cas_n = 1'b1;
501
        assign  o_ram_we_n  = 1'b1;
502
 
503
        assign  sdram_debug = 32'h0000;
504
`endif
505
 
506
        //
507
        //
508
        //      WISHBONE SCOPES
509
        //
510
        //
511
        //
512
        //
513
`ifdef  FLASH_SCOPE
514
        reg     [31:0]   r_flash_debug, last_flash_debug;
515
        wire    [31:0]   scop_flash_data;
516
        wire    scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
517
        always @(posedge i_clk)
518
                r_flash_debug <= flash_debug;
519
        always @(posedge i_clk)
520
                last_flash_debug <= r_flash_debug;
521
        wbscope spiscope(i_clk, 1'b1, (~o_spi_cs_n), r_flash_debug,
522
                // Wishbone interface
523
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
524
                        wb_data,
525
                        scop_flash_ack, scop_flash_stall, scop_flash_data,
526
                scop_flash_interrupt);
527
`else
528
        wire    [31:0]   scop_flash_data;
529
        wire    scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
530
        assign  scop_flash_data = 32'h00;
531
        assign  scop_flash_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00);
532
        assign scop_flash_stall = 1'b0;
533
        assign scop_flash_interrupt = 1'b0;
534
`endif
535
 
536
 
537
        wire    [31:0]   scop_cfg_data;
538
        wire            scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
539
`ifdef  CFG_SCOPE
540
        wire            scop_cfg_trigger;
541
        assign  scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
542
        wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
543
                // Wishbone interface
544
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
545
                                wb_we, wb_addr[0], wb_data,
546
                        scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
547
                scop_cfg_interrupt);
548
`else
549
        assign  scop_cfg_data = 32'h00;
550
        assign  scop_cfg_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01);
551
        assign  scop_cfg_stall = 1'b0;
552
        assign  scop_cfg_interrupt = 1'b0;
553
`endif
554
 
555
        wire    [31:0]   scop_ram_data;
556
        wire            scop_ram_ack, scop_ram_stall, scop_ram_interrupt;
557
`ifdef  SDRAM_SCOPE
558
        wire            sdram_trigger;
559
        assign  sdram_trigger = sdram_sel;
560
        // assign sdram_trigger = ((wbu_cyc)&&(wbu_zip_sel)&&(wbu_stb)&&(~wbu_addr[0])),
561
        wire    sdram_write;
562
        assign  sdram_write = ((wb_cyc)&&(sdram_sel)&&(wb_stb)&&(wb_we)&&(~sdram_stall));
563
        /*
564
        reg     r_trigger;
565
        reg     [31:0]  last_data;
566
        always @(posedge i_clk)
567
                if (sdram_write)
568
                        last_data <= wb_data;
569
        initial r_trigger = 1'b0;
570
        always @(posedge i_clk)
571
                if ((sdram_write)&&(last_data == wb_data))
572
                        r_trigger <= 1'b1;
573
                else
574
                        r_trigger <= 1'b0;
575
        */
576
 
577
        wbscope #(5'hd) sdramscope(i_clk, 1'b1, sdram_trigger,
578
                        sdram_debug,
579
                        // zip_debug,
580
                // Wishbone interface
581
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)), wb_we, wb_addr[0],
582
                        wb_data,
583
                        scop_ram_ack, scop_ram_stall, scop_ram_data,
584
                scop_ram_interrupt);
585
`else
586
        assign  scop_ram_data = 32'h00;
587
        assign  scop_ram_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10);
588
        assign  scop_ram_stall = 1'b0;
589
        assign  scop_ram_interrupt = 1'b0;
590
`endif
591
 
592
        wire    [31:0]   scop_zip_data;
593
        wire            scop_zip_ack, scop_zip_stall, scop_zip_interrupt;
594
`ifdef  ZIP_SCOPE
595
        wire            zip_trigger;
596
        assign  zip_trigger=(wbu_zip_sel)&&(wbu_we)&&(wbu_stb)&&(~wbu_addr[0]);
597
        wbscope #(5'hd) zipscope(i_clk, 1'b1, zip_trigger,
598
                        zip_debug,
599
                // Wishbone interface
600
                i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
601
                        wb_data,
602
                        scop_zip_ack, scop_zip_stall, scop_zip_data,
603
                scop_zip_interrupt);
604
`else
605
        assign  scop_zip_data = 32'h00;
606
        assign  scop_zip_ack  = (wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11);
607
        assign  scop_zip_stall = 1'b0;
608
        assign  scop_zip_interrupt = 1'b0;
609
`endif
610
 
611
 
612
        assign  scop_interrupt = scop_flash_interrupt || scop_cfg_interrupt
613
                                || scop_ram_interrupt || scop_zip_interrupt;
614
        assign  scop_ack   = scop_cfg_ack | scop_flash_ack | scop_ram_ack | scop_zip_ack;
615
        assign  scop_stall = ((~wb_addr[2])?
616
                                ((wb_addr[1])?scop_flash_stall:scop_cfg_stall)
617
                                : ((wb_addr[1])?scop_ram_stall:scop_zip_stall));
618
        assign  scop_data  = ((scop_cfg_ack)?scop_cfg_data
619
                                : ((scop_flash_ack) ? scop_flash_data
620
                                : ((scop_ram_ack) ? scop_ram_data
621
                                : scop_zip_data)));
622
 
623
 
624
        reg     r_sdcard_ack;
625
        initial r_sdcard_ack = 1'b0;
626
        always @(posedge i_clk)
627
                r_sdcard_ack <= (wb_cyc)&&(wb_stb)&&(sdcard_sel);
628
        assign  sdcard_stall = 1'b0;
629
        assign  sdcard_ack = r_sdcard_ack;
630
        assign  sdcard_data = 32'h0000;
631
endmodule
632
 
633
// 0x8684 interrupts ...???

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