OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [cpudefs.v] - Blame information for rev 72

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 72 dgisselq
`define XULA25
2 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
3
//
4
// Filename:    cpudefs.v
5
//
6
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
7
//
8
// Purpose:     Some architectures have some needs, others have other needs.
9
//              Some of my projects need a Zip CPU with pipelining, others
10
//      can't handle the timing required to get the answer from the ALU
11
//      back into the input for the ALU.  As each different projects has
12
//      different needs, I can either 1) reconfigure my entire baseline prior
13
//      to building each project, or 2) host a configuration file which contains
14
//      the information regarding each baseline.  This file is that
15
//      configuration file.  It controls how the CPU (not the system,
16
//      peripherals, or other) is defined and implemented.  Several options
17
//      are available within here, making the Zip CPU pipelined or not,
18
//      able to handle a faster clock with more stalls or a slower clock with
19
//      no stalls, etc.
20
//
21
//      This file encapsulates those control options.
22
//
23
//      The number of LUTs the Zip CPU uses varies dramatically with the
24
//      options defined in this file.
25
//
26
//
27
// Creator:     Dan Gisselquist, Ph.D.
28
//              Gisselquist Technology, LLC
29
//
30
///////////////////////////////////////////////////////////////////////////////
31
//
32
// Copyright (C) 2015, Gisselquist Technology, LLC
33
//
34
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// License:     GPL, v3, as defined and found on www.gnu.org,
45
//              http://www.gnu.org/licenses/gpl.html
46
//
47
//
48
///////////////////////////////////////////////////////////////////////////////
49
`ifndef CPUDEFS_H
50
`define CPUDEFS_H
51
//
52
//
53
// The first couple options control the Zip CPU instruction set, and how
54
// it handles various instructions within the set:
55
//
56
//
57
// OPT_ILLEGAL_INSTRUCTION is part of a new section of code that is supposed
58
// to recognize illegal instructions and interrupt the CPU whenever one such
59
// instruction is encountered.  The goal is to create a soft floating point
60
// unit via this approach, that can then be replaced with a true floating point
61
// unit.  As I'm not there yet, it just catches illegal instructions and
62
// interrupts the CPU on any such instruction--when defined.  Otherwise,
63
// illegal instructions are quietly ignored and their behaviour is ...
64
// undefined. (Many get treated like NOOPs ...)
65
//
66
// I recommend setting this flag, although it can be taken out if area is
67
// critical ...
68
//
69
`define OPT_ILLEGAL_INSTRUCTION
70
//
71
//
72
//
73
// OPT_MULTIPLY controls whether or not the multiply is built and included
74
// in the ALU by default.  Set this option and a parameter will be set that
75
// includes the multiply.  (This parameter may still be overridden, as with
76
// any parameter ...)  If the multiply is not included and
77
// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
78
// instruction that will then trip the illegal instruction trap.
79
//
80
//
81 52 dgisselq
`define OPT_MULTIPLY    2
82 2 dgisselq
//
83
//
84
//
85
// OPT_DIVIDE controls whether or not the divide instruction is built and
86
// included into the ZipCPU by default.  Set this option and a parameter will
87
// be set that causes the divide unit to be included.  (This parameter may
88
// still be overridden, as with any parameter ...)  If the divide is not
89
// included and OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create
90
// an illegal instruction exception that will send the CPU into supervisor
91
// mode.
92
//
93
//
94 31 dgisselq
`ifdef  XULA25
95 2 dgisselq
`define OPT_DIVIDE
96 31 dgisselq
`endif
97 2 dgisselq
//
98
//
99
//
100
// OPT_IMPLEMENT_FPU will (one day) control whether or not the floating point
101
// unit (once I have one) is built and included into the ZipCPU by default. 
102
// At that time, if this option is set then a parameter will be set that
103
// causes the floating point unit to be included.  (This parameter may
104
// still be overridden, as with any parameter ...)  If the floating point unit
105
// is not included and OPT_ILLEGAL_INSTRUCTION is set, then as with the
106
// multiply and divide any floating point instruction will result in an illegal
107
// instruction exception that will send the CPU into supervisor mode.
108
//
109
//
110
// `define      OPT_IMPLEMENT_FPU
111
//
112
//
113
//
114
// OPT_NEW_INSTRUCTION_SET controls whether or not the new instruction set
115
// is in use.  The new instruction set contains space for floating point
116
// operations, signed and unsigned divide instructions, as well as bit reversal
117
// and ... at least two other operations yet to be defined.  The decoder alone
118
// uses about 70 fewer LUTs, although in practice this works out to 12 fewer
119
// when all works out in the wash.  Further, floating point and divide
120
// instructions will cause an illegal instruction exception if they are not
121
// implemented--so software capability can be built to use these instructions
122
// immediately, even if the hardware is not yet ready.
123
//
124
// This option is likely to go away in the future, obsoleting the previous
125
// instruction set, so I recommend setting this option and switching to the
126
// new instruction set as soon as possible.
127
//
128
`define OPT_NEW_INSTRUCTION_SET
129
//
130
//
131
//
132
//
133
//
134
//
135
// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and 
136
// whether or not it can issue one instruction per clock.  When set, the
137
// prefetch has no cache, and only one instruction is fetched at a time.
138
// This effectively sets the CPU so that only one instruction is ever 
139
// in the pipeline at once, and hence you may think of this as a "kill 
140
// pipeline" option.  However, since the pipelined fetch component uses so
141
// much area on the FPGA, this is an important option to use in trimming down
142
// used area if necessary.  Hence, it needs to be maintained for that purpose.
143
// Be aware, though, it will drop your performance by a factor between 2x and
144
// 3x.
145
//
146
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
147
// fetches are more complicated and therefore use more FPGA resources, while
148
// single fetches will cause the CPU to stall for about 5 stalls each 
149
// instruction cycle, effectively reducing the instruction count per clock to
150
// about 0.2.  However, the area cost may be worth it.  Consider:
151
//
152
//      Slice LUTs              ZipSystem       ZipCPU
153
//      Single Fetching         2521            1734
154
//      Pipelined fetching      2796            2046
155
//      (These numbers may be dated, but should still be representative ...)
156
//
157
// I recommend only defining this if you "need" to, if area is tight and
158
// speed isn't as important.  Otherwise, just leave this undefined.
159
//
160
// `define      OPT_SINGLE_FETCH
161
//
162
//
163
//
164
// The next several options are pipeline optimization options.  They make no
165
// sense in a single instruction fetch mode, hence we #ifndef them so they
166
// are only defined if we are in a full pipelined mode (i.e. OPT_SINGLE_FETCH
167
// is not defined).
168
//
169
`ifndef OPT_SINGLE_FETCH
170
//
171
//
172
//
173
// OPT_PIPELINED is the natural result and opposite of using the single 
174
// instruction fetch unit.  If you are not using that unit, the ZipCPU will
175
// be pipelined.  The option is defined here more for readability than 
176
// anything else, since OPT_PIPELINED makes more sense than OPT_SINGLE_FETCH,
177
// well ... that and it does a better job of explaining what is going on.
178
//
179
// In other words, leave this define alone--lest you break the ZipCPU.
180
//
181
`define OPT_PIPELINED
182
//
183
//
184
//
185
// OPT_TRADITIONAL_PFCACHE allows you to switch between one of two prefetch
186
// caches.  If enabled, a more traditional cache is implemented.  This more
187
// traditional cache (currently) uses many more LUTs, but it also reduces
188
// the stall count tremendously over the alternative hacked pipeline cache.
189
// (The traditional pfcache is also pipelined, whereas the pipeline cache
190
// implements a windowed approach to caching.)
191
//
192
// If you have the fabric to support this option, I recommend including it.
193
//
194 31 dgisselq
`ifdef  XULA25
195 2 dgisselq
`define OPT_TRADITIONAL_PFCACHE
196 31 dgisselq
`endif
197 2 dgisselq
//
198
//
199
//
200
// OPT_EARLY_BRANCHING is an attempt to execute a BRA statement as early
201
// as possible, to avoid as many pipeline stalls on a branch as possible.
202
// It's not tremendously successful yet--BRA's still suffer stalls,
203
// but I intend to keep working on this approach until the number of stalls
204
// gets down to one or (ideally) zero.  (With the OPT_TRADITIONAL_PFCACHE, this
205
// gets down to a single stall cycle ...)  That way a "BRA" can be used as the
206
// compiler's branch prediction optimizer: BRA's barely stall, while branches
207
// on conditions will always suffer about 4 stall cycles or so.
208
//
209
// I recommend setting this flag, so as to turn early branching on.
210
//
211
`define OPT_EARLY_BRANCHING
212
//
213
//
214
//
215
// OPT_PIPELINED_BUS_ACCESS controls whether or not LOD/STO instructions
216
// can take advantaged of pipelined bus instructions.  To be eligible, the
217
// operations must be identical (cannot pipeline loads and stores, just loads
218
// only or stores only), and the addresses must either be identical or one up
219
// from the previous address.  Further, the load/store string must all have
220
// the same conditional.  This approach gains the must use, in my humble
221
// opinion, when saving registers to or restoring registers from the stack
222
// at the beginning/end of a procedure, or when doing a context swap.
223
//
224
// I recommend setting this flag, for performance reasons, especially if your
225
// wishbone bus can handle pipelined bus accesses.
226
//
227
`define OPT_PIPELINED_BUS_ACCESS
228
//
229
//
230
//
231
`ifdef  OPT_NEW_INSTRUCTION_SET
232
//
233
//
234
//
235
// The new instruction set also defines a set of very long instruction words.
236
// Well, calling them "very long" instruction words is probably a misnomer,
237
// although we're going to do it.  They're really 2x16-bit instructions---
238
// instruction words that pack two instructions into one word.  (2x14 bit
239
// really--'cause you need a bit to note the instruction is a 2x instruction,
240
// and then 3-bits for the condition codes ...)  Set OPT_VLIW to include these
241
// double instructions as part of the new instruction set.  These allow a single
242
// instruction to contain two instructions within.   These instructions are
243
// designed to get more code density from the instruction set, and to hopefully
244
// take some pain off of the performance of the pre-fetch and instruction cache.
245
//
246
// These new instructions, however, also necessitate a change in the Zip
247
// CPU--the Zip CPU can no longer execute instructions atomically.  It must
248
// now execute non-VLIW instructions, or VLIW instruction pairs, atomically. 
249
// This logic has been added into the ZipCPU, but it has not (yet) been
250
// tested thoroughly.
251
//
252
// Oh, and the assembler, the debugger, and the object file dumper, and the
253
// simulator all need to be updated as well ....
254
//
255
`define OPT_VLIW
256
//
257
//
258
`endif // OPT_NEW_INSTRUCTION_SET
259
//
260
//
261
`endif  // OPT_SINGLE_FETCH
262
//
263
//
264
//
265
// Now let's talk about peripherals for a moment.  These next two defines
266
// control whether the DMA controller is included in the Zip System, and
267
// whether or not the 8 accounting timers are also included.  Set these to
268
// include the respective peripherals, comment them out not to.
269
//
270 31 dgisselq
`ifdef  XULA25
271 2 dgisselq
`define INCLUDE_DMA_CONTROLLER
272
`define INCLUDE_ACCOUNTING_COUNTERS
273
//
274
//
275
`define DEBUG_SCOPE
276 31 dgisselq
`endif
277 2 dgisselq
//
278
`endif  // CPUDEFS_H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.