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1 21 dgisselq 
///////////////////////////////////////////////////////////////////////////////
2 
//
3 
// Filename:    zipcpu.v
4 
//
5 
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6 
//
7 
// Purpose:     This is the top level module holding the core of the Zip CPU
8 
//              together.  The Zip CPU is designed to be as simple as possible.
9 
//      (actual implementation aside ...)  The instruction set is about as
10 
//      RISC as you can get, there are only 16 instruction types supported.
11 
//      Please see the accompanying spec.pdf file for a description of these
12 
//      instructions.
13 
//
14 
//      All instructions are 32-bits wide.  All bus accesses, both address and
15 
//      data, are 32-bits over a wishbone bus.
16 
//
17 
//      The Zip CPU is fully pipelined with the following pipeline stages:
18 
//
19 
//              1. Prefetch, returns the instruction from memory.
20 
//
21 
//              2. Instruction Decode
22 
//
23 
//              3. Read Operands
24 
//
25 
//              4. Apply Instruction
26 
//
27 
//              4. Write-back Results
28 
//
29 
//      Further information about the inner workings of this CPU may be
30 
//      found in the spec.pdf file.  (The documentation within this file
31 
//      had become out of date and out of sync with the spec.pdf, so look
32 
//      to the spec.pdf for accurate and up to date information.)
33 
//
34 
//
35 
//      In general, the pipelining is controlled by three pieces of logic
36 
//      per stage: _ce, _stall, and _valid.  _valid means that the stage
37 
//      holds a valid instruction.  _ce means that the instruction from the
38 
//      previous stage is to move into this one, and _stall means that the
39 
//      instruction from the previous stage may not move into this one.
40 
//      The difference between these control signals allows individual stages
41 
//      to propagate instructions independently.  In general, the logic works
42 
//      as:
43 
//
44 
//
45 
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
46 
//
47 
//
48 
//      always @(posedge i_clk)
49 
//              if ((i_rst)||(clear_pipeline))
50 
//                      (n)_valid = 0
51 
//              else if (n)_ce
52 
//                      (n)_valid = 1
53 
//              else if (n+1)_ce
54 
//                      (n)_valid = 0
55 
//
56 
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
57 
//                      || (  (n)_valid && (n+1)_stall );
58 
//
59 
//      and ...
60 
//
61 
//      always @(posedge i_clk)
62 
//              if (n)_ce
63 
//                      (n)_variable = ... whatever logic for this stage
64 
//
65 
//      Note that a stage can stall even if no instruction is loaded into
66 
//      it.
67 
//
68 
//
69 
// Creator:     Dan Gisselquist, Ph.D.
70 
//              Gisselquist Technology, LLC
71 
//
72 
///////////////////////////////////////////////////////////////////////////////
73 
//
74 
// Copyright (C) 2015, Gisselquist Technology, LLC
75 
//
76 
// This program is free software (firmware): you can redistribute it and/or
77 
// modify it under the terms of  the GNU General Public License as published
78 
// by the Free Software Foundation, either version 3 of the License, or (at
79 
// your option) any later version.
80 
//
81 
// This program is distributed in the hope that it will be useful, but WITHOUT
82 
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
83 
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
84 
// for more details.
85 
//
86 
// License:     GPL, v3, as defined and found on www.gnu.org,
87 
//              http://www.gnu.org/licenses/gpl.html
88 
//
89 
//
90 
///////////////////////////////////////////////////////////////////////////////
91 
//
92 
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
93 
// fetches are more complicated and therefore use more FPGA resources, while
94 
// single fetches will cause the CPU to stall for about 5 stalls each
95 
// instruction cycle, effectively reducing the instruction count per clock to
96 
// about 0.2.  However, the area cost may be worth it.  Consider:
97 
//
98 
//      Slice LUTs              ZipSystem       ZipCPU
99 
//      Single Fetching         2521            1734
100 
//      Pipelined fetching      2796            2046
101 
//
102 
//
103 
//
104 
`define CPU_CC_REG      4'he
105 
`define CPU_PC_REG      4'hf
106 
`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107 
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108 
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109 
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110 
`define CPU_ILL_BIT     8       // Illegal instruction
111 
`define CPU_BREAK_BIT   7
112 
`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
113 
`define CPU_GIE_BIT     5
114 
`define CPU_SLEEP_BIT   4
115 
// Compile time defines
116 
//
117 
`include "cpudefs.v"
118 
//
119 
//
120 
module  zipcpu(i_clk, i_rst, i_interrupt,
121 
                // Debug interface
122 
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123 
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
124 
                        o_break,
125 
                // CPU interface to the wishbone bus
126 
                o_wb_gbl_cyc, o_wb_gbl_stb,
127 
                        o_wb_lcl_cyc, o_wb_lcl_stb,
128 
                        o_wb_we, o_wb_addr, o_wb_data,
129 
                        i_wb_ack, i_wb_stall, i_wb_data,
130 
                        i_wb_err,
131 
                // Accounting/CPU usage interface
132 
                o_op_stall, o_pf_stall, o_i_count
133 
`ifdef  DEBUG_SCOPE
134 
                , o_debug
135 
`endif
136 
                );
137 
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
138 
                        LGICACHE=6;
139 
`ifdef  OPT_MULTIPLY
140 52 dgisselq 
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
141 21 dgisselq 
`else
142 
        parameter       IMPLEMENT_MPY = 0;
143 
`endif
144 
`ifdef  OPT_DIVIDE
145 
        parameter       IMPLEMENT_DIVIDE = 1;
146 
`else
147 
        parameter       IMPLEMENT_DIVIDE = 0;
148 
`endif
149 
`ifdef  OPT_IMPLEMENT_FPU
150 
        parameter       IMPLEMENT_FPU = 1,
151 
`else
152 
        parameter       IMPLEMENT_FPU = 0,
153 
`endif
154 
                        IMPLEMENT_LOCK=1;
155 
`ifdef  OPT_EARLY_BRANCHING
156 
        parameter       EARLY_BRANCHING = 1;
157 
`else
158 
        parameter       EARLY_BRANCHING = 0;
159 
`endif
160 
        parameter       AW=ADDRESS_WIDTH;
161 
        input                   i_clk, i_rst, i_interrupt;
162 
        // Debug interface -- inputs
163 
        input                   i_halt, i_clear_pf_cache;
164 
        input           [4:0]    i_dbg_reg;
165 
        input                   i_dbg_we;
166 
        input           [31:0]   i_dbg_data;
167 
        // Debug interface -- outputs
168 
        output  reg             o_dbg_stall;
169 
        output  reg     [31:0]   o_dbg_reg;
170 
        output  reg     [3:0]    o_dbg_cc;
171 
        output  wire            o_break;
172 
        // Wishbone interface -- outputs
173 
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
174 
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
175 
        output  wire    [(AW-1):0]       o_wb_addr;
176 
        output  wire    [31:0]   o_wb_data;
177 
        // Wishbone interface -- inputs
178 
        input                   i_wb_ack, i_wb_stall;
179 
        input           [31:0]   i_wb_data;
180 
        input                   i_wb_err;
181 
        // Accounting outputs ... to help us count stalls and usage
182 
        output  wire            o_op_stall;
183 
        output  wire            o_pf_stall;
184 
        output  wire            o_i_count;
185 
        //
186 
`ifdef  DEBUG_SCOPE
187 
        output  reg     [31:0]   o_debug;
188 
`endif
189 
 
190 
 
191 
        // Registers
192 
        //
193 
        //      The distributed RAM style comment is necessary on the
194 
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
195 
        // set and in the process ruining everything else.  It basically
196 
        // optimizes logic away, to where it no longer works.  The logic
197 
        // as described herein will work, this just makes sure XST implements
198 
        // that logic.
199 
        //
200 
        (* ram_style = "distributed" *)
201 
        reg     [31:0]   regset [0:31];
202 
 
203 
        // Condition codes
204 
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
205 
        reg     [3:0]    flags, iflags;
206 
        wire    [13:0]   w_uflags, w_iflags;
207 
        reg             trap, break_en, step, gie, sleep;
208 
`ifdef  OPT_ILLEGAL_INSTRUCTION
209 
        reg             ill_err_u, ill_err_i;
210 
`else
211 
        wire            ill_err_u, ill_err_i;
212 
`endif
213 
        reg             ibus_err_flag, ubus_err_flag;
214 
        wire            idiv_err_flag, udiv_err_flag;
215 
        wire            ifpu_err_flag, ufpu_err_flag;
216 
        wire            ihalt_phase, uhalt_phase;
217 
 
218 
        // The master chip enable
219 
        wire            master_ce;
220 
 
221 
        //
222 
        //
223 
        //      PIPELINE STAGE #1 :: Prefetch
224 
        //              Variable declarations
225 
        //
226 
        reg     [(AW-1):0]       pf_pc;
227 
        reg     new_pc;
228 
        wire    clear_pipeline;
229 
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
230 
 
231 
        wire            dcd_stalled;
232 
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
233 
        wire    [(AW-1):0]       pf_addr;
234 
        wire    [31:0]           pf_data;
235 
        wire    [31:0]           instruction;
236 
        wire    [(AW-1):0]       instruction_pc;
237 
        wire    pf_valid, instruction_gie, pf_illegal;
238 
 
239 
        //
240 
        //
241 
        //      PIPELINE STAGE #2 :: Instruction Decode
242 
        //              Variable declarations
243 
        //
244 
        //
245 
        reg             opvalid, opvalid_mem, opvalid_alu;
246 
        reg             opvalid_div, opvalid_fpu;
247 
        wire            op_stall, dcd_ce, dcd_phase;
248 
        wire    [3:0]    dcdOp;
249 
        wire    [4:0]    dcdA, dcdB, dcdR;
250 
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
251 
        wire    [3:0]    dcdF;
252 
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
253 
                                dcdALU, dcdM, dcdDV, dcdFP,
254 
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
255 26 dgisselq 
                                dcd_pipe, dcd_ljmp;
256 21 dgisselq 
        reg             r_dcdvalid;
257 
        wire            dcdvalid;
258 
        wire    [(AW-1):0]       dcd_pc;
259 
        wire    [31:0]   dcdI;
260 
        wire            dcd_zI; // true if dcdI == 0
261 
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
262 
 
263 
        wire    dcd_illegal;
264 
        wire                    dcd_early_branch;
265 
        wire    [(AW-1):0]       dcd_branch_pc;
266 
 
267 
 
268 
        //
269 
        //
270 
        //      PIPELINE STAGE #3 :: Read Operands
271 
        //              Variable declarations
272 
        //
273 
        //
274 
        //
275 
        // Now, let's read our operands
276 
        reg     [4:0]    alu_reg;
277 
        reg     [3:0]    opn;
278 
        reg     [4:0]    opR;
279 
        reg     [31:0]   r_opA, r_opB;
280 
        reg     [(AW-1):0]       op_pc;
281 
        wire    [31:0]   w_opA, w_opB;
282 
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
283 
        reg             opR_wr, opR_cc, opF_wr, op_gie;
284 
        wire    [13:0]   opFl;
285 
        reg     [5:0]    r_opF;
286 
        wire    [7:0]    opF;
287 51 dgisselq 
        wire            op_ce, op_phase, op_pipe;
288 21 dgisselq 
        // Some pipeline control wires
289 
`ifdef  OPT_PIPELINED
290 
        reg     opA_alu, opA_mem;
291 
        reg     opB_alu, opB_mem;
292 
`endif
293 
`ifdef  OPT_ILLEGAL_INSTRUCTION
294 
        reg     op_illegal;
295 
`endif
296 
        reg     op_break;
297 
        wire    op_lock;
298 
 
299 
 
300 
        //
301 
        //
302 
        //      PIPELINE STAGE #4 :: ALU / Memory
303 
        //              Variable declarations
304 
        //
305 
        //
306 
        reg     [(AW-1):0]       alu_pc;
307 51 dgisselq 
        reg             alu_pc_valid, mem_pc_valid;
308 21 dgisselq 
        wire            alu_phase;
309 
        wire            alu_ce, alu_stall;
310 
        wire    [31:0]   alu_result;
311 
        wire    [3:0]    alu_flags;
312 
        wire            alu_valid, alu_busy;
313 
        wire            set_cond;
314 
        reg             alu_wr, alF_wr, alu_gie;
315 
        wire            alu_illegal_op;
316 
        wire            alu_illegal;
317 
 
318 
 
319 
 
320 
        wire    mem_ce, mem_stalled;
321 
`ifdef  OPT_PIPELINED_BUS_ACCESS
322 
        wire    mem_pipe_stalled;
323 
`endif
324 
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
325 
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
326 
        wire    [4:0]            mem_wreg;
327 
 
328 
        wire                    mem_busy, mem_rdbusy;
329 
        wire    [(AW-1):0]       mem_addr;
330 
        wire    [31:0]           mem_data, mem_result;
331 
 
332 
        wire    div_ce, div_error, div_busy, div_valid;
333 
        wire    [31:0]   div_result;
334 
        wire    [3:0]    div_flags;
335 
 
336 
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
337 
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
338 
                                &&(set_cond);
339 
 
340 
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
341 
        wire    [31:0]   fpu_result;
342 
        wire    [3:0]    fpu_flags;
343 
 
344 
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
345 
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
346 
                                &&(set_cond);
347 
 
348 
 
349 
        //
350 
        //
351 
        //      PIPELINE STAGE #5 :: Write-back
352 
        //              Variable declarations
353 
        //
354 
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
355 
        wire    [4:0]    wr_reg_id;
356 
        wire    [31:0]   wr_reg_vl;
357 
        wire    w_switch_to_interrupt, w_release_from_interrupt;
358 
        reg     [(AW-1):0]       upc, ipc;
359 
 
360 
 
361 
 
362 
        //
363 
        //      MASTER: clock enable.
364 
        //
365 
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
366 
 
367 
 
368 
        //
369 
        //      PIPELINE STAGE #1 :: Prefetch
370 
        //              Calculate stall conditions
371 
        //
372 
        //      These are calculated externally, within the prefetch module.
373 
        //
374 
 
375 
        //
376 
        //      PIPELINE STAGE #2 :: Instruction Decode
377 
        //              Calculate stall conditions
378 
`ifdef  OPT_PIPELINED
379 
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
380 
`else
381 
        assign          dcd_ce = 1'b1;
382 
`endif
383 
`ifdef  OPT_PIPELINED
384 
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
385 
`else
386 
        // If not pipelined, there will be no opvalid_ anything, and the
387 
        // op_stall will be false, dcdX_stall will be false, thus we can simply
388 
        // do a ...
389 
        assign          dcd_stalled = 1'b0;
390 
`endif
391 
        //
392 
        //      PIPELINE STAGE #3 :: Read Operands
393 
        //              Calculate stall conditions
394 
        wire    op_lock_stall;
395 
`ifdef  OPT_PIPELINED
396 
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
397 
                        // Stall if we're stopped, and not allowed to execute
398 
                        // an instruction
399 
                        // (~master_ce)         // Already captured in alu_stall
400 
                        //
401 
                        // Stall if going into the ALU and the ALU is stalled
402 
                        //      i.e. if the memory is busy, or we are single
403 
                        //      stepping.  This also includes our stalls for
404 
                        //      op_break and op_lock, so we don't need to
405 
                        //      include those as well here.
406 
                        // This also includes whether or not the divide or
407 
                        // floating point units are busy.
408 
                        (alu_stall)
409 
                        //
410 
                        // Stall if we are going into memory with an operation
411 
                        //      that cannot be pipelined, and the memory is
412 
                        //      already busy
413 
                        ||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
414 
                        )
415 
                        ||(dcdvalid)&&(
416 
                                // Stall if we need to wait for an operand A
417 
                                // to be ready to read
418 
                                (dcdA_stall)
419 
                                // Likewise for B, also includes logic
420 
                                // regarding immediate offset (register must
421 
                                // be in register file if we need to add to
422 
                                // an immediate)
423 
                                ||(dcdB_stall)
424 
                                // Or if we need to wait on flags to work on the
425 
                                // CC register
426 
                                ||(dcdF_stall)
427 
                        );
428 
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
429 
`else
430 
        assign  op_stall = (opvalid)&&(~master_ce);
431 
        assign  op_ce = ((dcdvalid)||(dcd_illegal));
432 
`endif
433 
 
434 
        //
435 
        //      PIPELINE STAGE #4 :: ALU / Memory
436 
        //              Calculate stall conditions
437 
        //
438 
        // 1. Basic stall is if the previous stage is valid and the next is
439 
        //      busy.
440 
        // 2. Also stall if the prior stage is valid and the master clock enable
441 
        //      is de-selected
442 
        // 3. Stall if someone on the other end is writing the CC register,
443 
        //      since we don't know if it'll put us to sleep or not.
444 
        // 4. Last case: Stall if we would otherwise move a break instruction
445 
        //      through the ALU.  Break instructions are not allowed through
446 
        //      the ALU.
447 
`ifdef  OPT_PIPELINED
448 
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
449 
                        // Old case #3--this isn't an ALU stall though ...
450 
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
451 
                                &&(wr_write_cc)) // Case 3
452 
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
453 
                        ||((opvalid)&&(op_break))
454 
                        ||(div_busy)||(fpu_busy);
455 
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))
456 
                                &&(~alu_stall)
457 
                                &&(~clear_pipeline);
458 
`else
459 
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
460 
                                ||((opvalid_alu)&&(op_break));
461 
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall);
462 
`endif
463 
        //
464 
 
465 
        //
466 
        // Note: if you change the conditions for mem_ce, you must also change
467 
        // alu_pc_valid.
468 
        //
469 
`ifdef  OPT_PIPELINED
470 
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
471 
                        &&(~clear_pipeline);
472 
`else
473 
        // If we aren't pipelined, then no one will be changing what's in the
474 
        // pipeline (i.e. clear_pipeline), while our only instruction goes
475 
        // through the ... pipeline.
476 
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled);
477 
`endif
478 
`ifdef  OPT_PIPELINED_BUS_ACCESS
479 
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
480 
                                (mem_pipe_stalled)
481 
                                ||((~op_pipe)&&(mem_busy))
482 
                                ||(div_busy)
483 
                                ||(fpu_busy)
484 
                                // Stall waiting for flags to be valid
485 
                                // Or waiting for a write to the PC register
486 
                                // Or CC register, since that can change the
487 
                                //  PC as well
488 
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
489 
                                        &&((wr_write_pc)||(wr_write_cc)))));
490 
`else
491 
`ifdef  OPT_PIPELINED
492 
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
493 
                                (~master_ce)
494 
                                // Stall waiting for flags to be valid
495 
                                // Or waiting for a write to the PC register
496 
                                // Or CC register, since that can change the
497 
                                //  PC as well
498 
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
499 
`else
500 
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
501 
`endif
502 
`endif
503 
 
504 
 
505 
        //
506 
        //
507 
        //      PIPELINE STAGE #1 :: Prefetch
508 
        //
509 
        //
510 
`ifdef  OPT_SINGLE_FETCH
511 
        wire            pf_ce;
512 
 
513 
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
514 
        prefetch        #(ADDRESS_WIDTH)
515 
                        pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
516 
                                instruction, instruction_pc, instruction_gie,
517 
                                        pf_valid, pf_illegal,
518 
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
519 
                                pf_ack, pf_stall, pf_err, i_wb_data);
520 
 
521 
        initial r_dcdvalid = 1'b0;
522 
        always @(posedge i_clk)
523 
                if (i_rst)
524 
                        r_dcdvalid <= 1'b0;
525 
                else if (dcd_ce)
526 26 dgisselq 
                        r_dcdvalid <= (pf_valid);
527 
                else if (op_ce)
528 21 dgisselq 
                        r_dcdvalid <= 1'b0;
529 
        assign  dcdvalid = r_dcdvalid;
530 
 
531 
`else // Pipe fetch
532 
 
533 
`ifdef  OPT_TRADITIONAL_PFCACHE
534 
        pfcache #(LGICACHE, ADDRESS_WIDTH)
535 26 dgisselq 
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
536 21 dgisselq 
                                        i_clear_pf_cache,
537 
                                // dcd_pc,
538 
                                ~dcd_stalled,
539 26 dgisselq 
                                ((dcd_early_branch)&&(~clear_pipeline))
540 21 dgisselq 
                                        ? dcd_branch_pc:pf_pc,
541 
                                instruction, instruction_pc, pf_valid,
542 
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
543 
                                        pf_ack, pf_stall, pf_err, i_wb_data,
544 
                                pf_illegal);
545 
`else
546 
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
547 26 dgisselq 
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
548 21 dgisselq 
                                        i_clear_pf_cache, ~dcd_stalled,
549 
                                        (new_pc)?pf_pc:dcd_branch_pc,
550 
                                        instruction, instruction_pc, pf_valid,
551 
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
552 
                                        pf_ack, pf_stall, pf_err, i_wb_data,
553 
//`ifdef        OPT_PRECLEAR_BUS
554 
                                //((dcd_clear_bus)&&(dcdvalid))
555 
                                //||((op_clear_bus)&&(opvalid))
556 
                                //||
557 
//`endif
558 
                                (mem_cyc_lcl)||(mem_cyc_gbl),
559 
                                pf_illegal);
560 
`endif
561 
        assign  instruction_gie = gie;
562 
 
563 
        initial r_dcdvalid = 1'b0;
564 
        always @(posedge i_clk)
565 
                if ((i_rst)||(clear_pipeline))
566 
                        r_dcdvalid <= 1'b0;
567 
                else if (dcd_ce)
568 26 dgisselq 
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
569 21 dgisselq 
                else if (op_ce)
570 
                        r_dcdvalid <= 1'b0;
571 
        assign  dcdvalid = r_dcdvalid;
572 
`endif
573 
 
574 
`ifdef  OPT_NEW_INSTRUCTION_SET
575 
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
576 
                        IMPLEMENT_FPU)
577 
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
578 
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
579 
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
580 
                        dcd_illegal, dcd_pc, dcd_gie,
581 
                        { dcdR_cc, dcdR_pc, dcdR },
582 
                        { dcdA_cc, dcdA_pc, dcdA },
583 
                        { dcdB_cc, dcdB_pc, dcdB },
584 
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
585 
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
586 
                        dcdR_wr,dcdA_rd, dcdB_rd,
587 
                        dcd_early_branch,
588 26 dgisselq 
                        dcd_branch_pc, dcd_ljmp,
589 21 dgisselq 
                        dcd_pipe);
590 
`else
591 
        idecode_deprecated
592 
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
593 
                        IMPLEMENT_FPU)
594 
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
595 
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
596 
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
597 
                        dcd_illegal, dcd_pc, dcd_gie,
598 
                        { dcdR_cc, dcdR_pc, dcdR },
599 
                        { dcdA_cc, dcdA_pc, dcdA },
600 
                        { dcdB_cc, dcdB_pc, dcdB },
601 
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
602 
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
603 
                        dcdR_wr,dcdA_rd, dcdB_rd,
604 
                        dcd_early_branch,
605 
                        dcd_branch_pc,
606 
                        dcd_pipe);
607 26 dgisselq 
        assign  dcd_ljmp = 1'b0;
608 21 dgisselq 
`endif
609 
 
610 
`ifdef  OPT_PIPELINED_BUS_ACCESS
611 51 dgisselq 
        reg             r_op_pipe;
612 21 dgisselq 
 
613 51 dgisselq 
        initial r_op_pipe = 1'b0;
614 21 dgisselq 
        // To be a pipeable operation, there must be
615 
        //      two valid adjacent instructions
616 
        //      Both must be memory instructions
617 
        //      Both must be writes, or both must be reads
618 
        //      Both operations must be to the same identical address,
619 
        //              or at least a single (one) increment above that address
620 
        //
621 
        // However ... we need to know this before this clock, hence this is
622 
        // calculated in the instruction decoder.
623 
        always @(posedge i_clk)
624 
                if (op_ce)
625 51 dgisselq 
                        r_op_pipe <= dcd_pipe;
626 
        assign  op_pipe = r_op_pipe;
627 
`else
628 
        assign  op_pipe = 1'b0;
629 21 dgisselq 
`endif
630 
 
631 
        //
632 
        //
633 
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
634 
        //
635 
        //
636 
        assign  w_opA = regset[dcdA];
637 
        assign  w_opB = regset[dcdB];
638 
 
639 51 dgisselq 
        wire    [8:0]    w_cpu_info;
640 
        assign  w_cpu_info = {
641 
`ifdef  OPT_ILLEGAL_INSTRUCTION
642 
        1'b1,
643 
`else
644 
        1'b0,
645 
`endif
646 
`ifdef  OPT_MULTIPLY
647 
        1'b1,
648 
`else
649 
        1'b0,
650 
`endif
651 
`ifdef  OPT_DIVIDE
652 
        1'b1,
653 
`else
654 
        1'b0,
655 
`endif
656 
`ifdef  OPT_IMPLEMENT_FPU
657 
        1'b1,
658 
`else
659 
        1'b0,
660 
`endif
661 
`ifdef  OPT_PIPELINED
662 
        1'b1,
663 
`else
664 
        1'b0,
665 
`endif
666 
`ifdef  OPT_TRADITIONAL_CACHE
667 
        1'b1,
668 
`else
669 
        1'b0,
670 
`endif
671 
`ifdef  OPT_EARLY_BRANCHING
672 
        1'b1,
673 
`else
674 
        1'b0,
675 
`endif
676 
`ifdef  OPT_PIPELINED_BUS_ACCESS
677 
        1'b1,
678 
`else
679 
        1'b0,
680 
`endif
681 
`ifdef  OPT_VLIW
682 
        1'b1
683 
`else
684 
        1'b0
685 
`endif
686 
        };
687 
 
688 21 dgisselq 
        wire    [31:0]   w_pcA_v;
689 
        generate
690 
        if (AW < 32)
691 
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
692 
        else
693 
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
694 
        endgenerate
695 
 
696 
`ifdef  OPT_PIPELINED
697 
        reg     [4:0]    opA_id, opB_id;
698 
        reg             opA_rd, opB_rd;
699 
        always @(posedge i_clk)
700 
                if (op_ce)
701 
                begin
702 
                        opA_id <= dcdA;
703 
                        opB_id <= dcdB;
704 
                        opA_rd <= dcdA_rd;
705 
                        opB_rd <= dcdB_rd;
706 
                end
707 
`endif
708 
 
709 
        always @(posedge i_clk)
710 
                if (op_ce) // &&(dcdvalid))
711 
                begin
712 
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
713 
                                r_opA <= wr_reg_vl;
714 
                        else if (dcdA_pc)
715 
                                r_opA <= w_pcA_v;
716 
                        else if (dcdA_cc)
717 51 dgisselq 
                                r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };
718 21 dgisselq 
                        else
719 
                                r_opA <= w_opA;
720 
`ifdef  OPT_PIPELINED
721 
                end else
722 
                begin // We were going to pick these up when they became valid,
723 
                        // but for some reason we're stuck here as they became
724 
                        // valid.  Pick them up now anyway
725 
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
726 
                                // r_opA <= wr_reg_vl;
727 
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
728 
                                r_opA <= wr_reg_vl;
729 
`endif
730 
                end
731 
 
732 
        wire    [31:0]   w_opBnI, w_pcB_v;
733 
        generate
734 
        if (AW < 32)
735 
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
736 
        else
737 
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
738 
        endgenerate
739 
 
740 
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
741 
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
742 
                : ((dcdB_pc) ? w_pcB_v
743 51 dgisselq 
                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
744 
                        (dcdB[4])?w_uflags:w_iflags}
745 21 dgisselq 
                : w_opB)));
746 
 
747 
        always @(posedge i_clk)
748 
                if (op_ce) // &&(dcdvalid))
749 
                        r_opB <= w_opBnI + dcdI;
750 
`ifdef  OPT_PIPELINED
751 
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
752 
                        r_opB <= wr_reg_vl;
753 
`endif
754 
 
755 
        // The logic here has become more complex than it should be, no thanks
756 
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
757 
        // be two sets of four bits: the top bits specify what bits matter, the
758 
        // bottom specify what those top bits must equal.  However, two of
759 
        // conditions check whether bits are on, and those are the only two
760 
        // conditions checking those bits.  Therefore, Vivado complains that
761 
        // these two bits are redundant.  Hence the convoluted expression
762 
        // below, arriving at what we finally want in the (now wire net)
763 
        // opF.
764 
        always @(posedge i_clk)
765 
                if (op_ce)
766 
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
767 
                        case(dcdF[2:0])
768 
                        3'h0:   r_opF <= 6'h00; // Always
769 
`ifdef  OPT_NEW_INSTRUCTION_SET
770 
                        // These were remapped as part of the new instruction
771 
                        // set in order to make certain that the low order
772 
                        // two bits contained the most commonly used
773 
                        // conditions: Always, LT, Z, and NZ.
774 
                        3'h1:   r_opF <= 6'h24; // LT
775 
                        3'h2:   r_opF <= 6'h11; // Z
776 
                        3'h3:   r_opF <= 6'h10; // NE
777 
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
778 
                        3'h5:   r_opF <= 6'h20; // GE (!N)
779 
`else
780 
                        3'h1:   r_opF <= 6'h11; // Z
781 
                        3'h2:   r_opF <= 6'h10; // NE
782 
                        3'h3:   r_opF <= 6'h20; // GE (!N)
783 
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
784 
                        3'h5:   r_opF <= 6'h24; // LT
785 
`endif
786 
                        3'h6:   r_opF <= 6'h02; // C
787 
                        3'h7:   r_opF <= 6'h08; // V
788 
                        endcase
789 
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
790 
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
791 
 
792 
        wire    w_opvalid;
793 26 dgisselq 
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
794 21 dgisselq 
        initial opvalid     = 1'b0;
795 
        initial opvalid_alu = 1'b0;
796 
        initial opvalid_mem = 1'b0;
797 26 dgisselq 
        initial opvalid_div = 1'b0;
798 
        initial opvalid_fpu = 1'b0;
799 21 dgisselq 
        always @(posedge i_clk)
800 
                if (i_rst)
801 
                begin
802 
                        opvalid     <= 1'b0;
803 
                        opvalid_alu <= 1'b0;
804 
                        opvalid_mem <= 1'b0;
805 
                end else if (op_ce)
806 
                begin
807 
                        // Do we have a valid instruction?
808 
                        //   The decoder may vote to stall one of its
809 
                        //   instructions based upon something we currently
810 
                        //   have in our queue.  This instruction must then
811 
                        //   move forward, and get a stall cycle inserted.
812 
                        //   Hence, the test on dcd_stalled here.  If we must
813 
                        //   wait until our operands are valid, then we aren't
814 
                        //   valid yet until then.
815 
                        opvalid<= w_opvalid;
816 
`ifdef  OPT_ILLEGAL_INSTRUCTION
817 
                        opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
818 
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
819 
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
820 
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
821 
`else
822 
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
823 
                        opvalid_mem <= (dcdM)&&(w_opvalid);
824 
                        opvalid_div <= (dcdDV)&&(w_opvalid);
825 
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
826 
`endif
827 
                end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
828 
                begin
829 
                        opvalid     <= 1'b0;
830 
                        opvalid_alu <= 1'b0;
831 
                        opvalid_mem <= 1'b0;
832 
                        opvalid_div <= 1'b0;
833 
                        opvalid_fpu <= 1'b0;
834 
                end
835 
 
836 
        // Here's part of our debug interface.  When we recognize a break
837 
        // instruction, we set the op_break flag.  That'll prevent this
838 
        // instruction from entering the ALU, and cause an interrupt before
839 
        // this instruction.  Thus, returning to this code will cause the
840 
        // break to repeat and continue upon return.  To get out of this
841 
        // condition, replace the break instruction with what it is supposed
842 
        // to be, step through it, and then replace it back.  In this fashion,
843 
        // a debugger can step through code.
844 
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
845 
        initial op_break = 1'b0;
846 
        always @(posedge i_clk)
847 
                if (i_rst)      op_break <= 1'b0;
848 
                else if (op_ce) op_break <= (dcd_break);
849 
                else if ((clear_pipeline)||(~opvalid))
850 
                                op_break <= 1'b0;
851 
 
852 
`ifdef  OPT_PIPELINED
853 
        generate
854 
        if (IMPLEMENT_LOCK != 0)
855 
        begin
856 
                reg     r_op_lock, r_op_lock_stall;
857 
 
858 
                initial r_op_lock_stall = 1'b0;
859 
                always @(posedge i_clk)
860 
                        if (i_rst)
861 
                                r_op_lock_stall <= 1'b0;
862 
                        else
863 
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
864 
                                                ||(~dcdvalid)||(~pf_valid);
865 
 
866 
                assign  op_lock_stall = r_op_lock_stall;
867 
 
868 
                initial r_op_lock = 1'b0;
869 
                always @(posedge i_clk)
870 
                        if (i_rst)
871 
                                r_op_lock <= 1'b0;
872 52 dgisselq 
                        else if (op_ce)
873 
                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);
874 21 dgisselq 
                assign  op_lock = r_op_lock;
875 
 
876 
        end else begin
877 
                assign  op_lock_stall = 1'b0;
878 
                assign  op_lock = 1'b0;
879 
        end endgenerate
880 
 
881 
`else
882 
        assign op_lock_stall = 1'b0;
883 
        assign op_lock       = 1'b0;
884 
`endif
885 
 
886 
`ifdef  OPT_ILLEGAL_INSTRUCTION
887 
        initial op_illegal = 1'b0;
888 
        always @(posedge i_clk)
889 
                if ((i_rst)||(clear_pipeline))
890 
                        op_illegal <= 1'b0;
891 
                else if(op_ce)
892 
`ifdef  OPT_PIPELINED
893 
                        op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
894 
`else
895 
                        op_illegal <= (dcd_illegal)||(dcd_lock);
896 
`endif
897 
`endif
898 
 
899 
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
900 
        // set, dcd_early_branch will simply be a wire connected to zero and
901 
        // this logic should just optimize.
902 
        always @(posedge i_clk)
903 
                if (op_ce)
904 
                begin
905 
                        opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
906 
                                &&(~dcd_early_branch)&&(~dcd_illegal);
907 
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
908 
                end
909 
 
910 
        always @(posedge i_clk)
911 
                if (op_ce)
912 
                begin
913 
                        opn    <= dcdOp;        // Which ALU operation?
914 
                        // opM  <= dcdM;        // Is this a memory operation?
915 
                        // What register will these results be written into?
916 
                        opR    <= dcdR;
917 
                        opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
918 
                        // User level (1), vs supervisor (0)/interrupts disabled
919 
                        op_gie <= dcd_gie;
920 
 
921 
 
922 
                        //
923 
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
924 
                end
925 
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
926 
 
927 
`ifdef  OPT_VLIW
928 
        reg     r_op_phase;
929 
        initial r_op_phase = 1'b0;
930 
        always @(posedge i_clk)
931 
                if ((i_rst)||(clear_pipeline))
932 
                        r_op_phase <= 1'b0;
933 
                else if (op_ce)
934 
                        r_op_phase <= dcd_phase;
935 
        assign  op_phase = r_op_phase;
936 
`else
937 
        assign  op_phase = 1'b0;
938 
`endif
939 
 
940 
        // This is tricky.  First, the PC and Flags registers aren't kept in
941 
        // register set but in special registers of their own.  So step one
942 
        // is to select the right register.  Step to is to replace that
943 
        // register with the results of an ALU or memory operation, if such
944 
        // results are now available.  Otherwise, we'd need to insert a wait
945 
        // state of some type.
946 
        //
947 
        // The alternative approach would be to define some sort of
948 
        // op_stall wire, which would stall any upstream stage.
949 
        // We'll create a flag here to start our coordination.  Once we
950 
        // define this flag to something other than just plain zero, then
951 
        // the stalls will already be in place.
952 
`ifdef  OPT_PIPELINED
953 
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
954 
                        ?  wr_reg_vl : r_opA;
955 
`else
956 
        assign  opA = r_opA;
957 
`endif
958 
 
959 
`ifdef  OPT_PIPELINED
960 
        // Stall if we have decoded an instruction that will read register A
961 
        //      AND ... something that may write a register is running
962 
        //      AND (series of conditions here ...)
963 
        //              The operation might set flags, and we wish to read the
964 
        //                      CC register
965 
        //              OR ... (No other conditions)
966 
        assign  dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
967 
                                &&((opvalid)||(mem_rdbusy)
968 
                                        ||(div_busy)||(fpu_busy))
969 
                                &&((opF_wr)&&(dcdA_cc));
970 
`else
971 
        // There are no pipeline hazards, if we aren't pipelined
972 
        assign  dcdA_stall = 1'b0;
973 
`endif
974 
 
975 
`ifdef  OPT_PIPELINED
976 
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
977 
                        ? wr_reg_vl: r_opB;
978 
`else
979 
        assign  opB = r_opB;
980 
`endif
981 
 
982 
`ifdef  OPT_PIPELINED
983 
        // Stall if we have decoded an instruction that will read register B
984 
        //      AND ... something that may write a (unknown) register is running
985 
        //      AND (series of conditions here ...)
986 
        //              The operation might set flags, and we wish to read the
987 
        //                      CC register
988 
        //              OR the operation might set register B, and we still need
989 
        //                      a clock to add the offset to it
990 
        assign  dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
991 
                                // If the op stage isn't valid, yet something
992 
                                // is running, then it must have been valid.
993 
                                // We'll use the last values from that stage
994 
                                // (opR_wr, opF_wr, opR) in our logic below.
995 
                                &&((opvalid)||(mem_rdbusy)
996 51 dgisselq 
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
997 21 dgisselq 
                                &&(
998 
                                // Stall on memory ops writing to my register
999 
                                //      (i.e. loads), or on any write to my
1000 
                                //      register if I have an immediate offset
1001 51 dgisselq 
                                //      Actually, this is worse.  I can't tell
1002 
                                //      whether or not my register is going to
1003 
                                //      be written to, so
1004 21 dgisselq 
                                // Note the exception for writing to the PC:
1005 
                                //      if I write to the PC, the whole next
1006 
                                //      instruction is invalid, not just the
1007 
                                //      operand.  That'll get wiped in the
1008 
                                //      next operation anyway, so don't stall
1009 
                                //      here.  This keeps a BC X, BNZ Y from
1010 
                                //      stalling between the two branches.
1011 
                                //      BC X, BRA Y is still clear, since BRA Y
1012 
                                //      is an early branch instruction.
1013 
                                //      (This exception is commented out in
1014 
                                //      order to help keep our logic simple, and
1015 
                                //      because multiple conditional branches
1016 
                                //      following each other constitutes a
1017 
                                //      fairly unusualy code structure.)
1018 
                                //
1019 51 dgisselq 
                                ((~dcd_zI)&&(
1020 
                                        ((opR == dcdB)&&(opR_wr))
1021 
                                        ||(((opvalid_mem)||(mem_rdbusy))
1022 
                                        &&(op_pipe))))
1023 21 dgisselq 
                                // Stall following any instruction that will
1024 
                                // set the flags, if we're going to need the
1025 
                                // flags (CC) register for opB.
1026 
                                ||((opF_wr)&&(dcdB_cc))
1027 
                                // Stall on any ongoing memory operation that
1028 
                                // will write to opB -- captured above
1029 
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
1030 
                                );
1031 26 dgisselq 
        assign  dcdF_stall = ((~dcdF[3])
1032 
                                        ||((dcdA_rd)&&(dcdA_cc))
1033 
                                        ||((dcdB_rd)&&(dcdB_cc)))
1034 
                                        &&(opvalid)&&(opR_cc);
1035 
                                // &&(dcdvalid) is checked for elsewhere
1036 21 dgisselq 
`else
1037 
        // No stalls without pipelining, 'cause how can you have a pipeline
1038 
        // hazard without the pipeline?
1039 
        assign  dcdB_stall = 1'b0;
1040 26 dgisselq 
        assign  dcdF_stall = 1'b0;
1041 21 dgisselq 
`endif
1042 
        //
1043 
        //
1044 
        //      PIPELINE STAGE #4 :: Apply Instruction
1045 
        //
1046 
        //
1047 
`ifdef  OPT_NEW_INSTRUCTION_SET
1048 
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1049 
                        (opvalid_alu), opn, opA, opB,
1050 
                        alu_result, alu_flags, alu_valid, alu_illegal_op,
1051 
                        alu_busy);
1052 
`else
1053 
        cpuops_deprecated       #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1054 
                        (opvalid_alu), opn, opA, opB,
1055 
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
1056 
        assign  alu_busy = 1'b0;
1057 
`endif
1058 
 
1059 
        generate
1060 
        if (IMPLEMENT_DIVIDE != 0)
1061 
        begin
1062 
                div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
1063 
                        opA, opB, div_busy, div_valid, div_error, div_result,
1064 
                        div_flags);
1065 
        end else begin
1066 
                assign  div_error = 1'b1;
1067 
                assign  div_busy  = 1'b0;
1068 
                assign  div_valid = 1'b0;
1069 
                assign  div_result= 32'h00;
1070 
                assign  div_flags = 4'h0;
1071 
        end endgenerate
1072 
 
1073 
        generate
1074 
        if (IMPLEMENT_FPU != 0)
1075 
        begin
1076 
                //
1077 
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1078 
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
1079 
                //      fpu_flags);
1080 
                //
1081 
                assign  fpu_error = 1'b1;
1082 
                assign  fpu_busy  = 1'b0;
1083 
                assign  fpu_valid = 1'b0;
1084 
                assign  fpu_result= 32'h00;
1085 
                assign  fpu_flags = 4'h0;
1086 
        end else begin
1087 
                assign  fpu_error = 1'b1;
1088 
                assign  fpu_busy  = 1'b0;
1089 
                assign  fpu_valid = 1'b0;
1090 
                assign  fpu_result= 32'h00;
1091 
                assign  fpu_flags = 4'h0;
1092 
        end endgenerate
1093 
 
1094 
 
1095 
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
1096 
        initial alF_wr   = 1'b0;
1097 
        initial alu_wr   = 1'b0;
1098 
        always @(posedge i_clk)
1099 
                if (i_rst)
1100 
                begin
1101 
                        alu_wr   <= 1'b0;
1102 
                        alF_wr   <= 1'b0;
1103 
                end else if (alu_ce)
1104 
                begin
1105 
                        // alu_reg <= opR;
1106 
                        alu_wr  <= (opR_wr)&&(set_cond);
1107 
                        alF_wr  <= (opF_wr)&&(set_cond);
1108 
                end else if (~alu_busy) begin
1109 
                        // These are strobe signals, so clear them if not
1110 
                        // set for any particular clock
1111 
                        alu_wr <= (i_halt)&&(i_dbg_we);
1112 
                        alF_wr <= 1'b0;
1113 
                end
1114 
 
1115 
`ifdef  OPT_VLIW
1116 
        reg     r_alu_phase;
1117 
        initial r_alu_phase = 1'b0;
1118 
        always @(posedge i_clk)
1119 
                if (i_rst)
1120 
                        r_alu_phase <= 1'b0;
1121 
                else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
1122 
                        r_alu_phase <= op_phase;
1123 
        assign  alu_phase = r_alu_phase;
1124 
`else
1125 
        assign  alu_phase = 1'b0;
1126 
`endif
1127 
 
1128 
        always @(posedge i_clk)
1129 
                if ((alu_ce)||(div_ce)||(fpu_ce))
1130 
                        alu_reg <= opR;
1131 
                else if ((i_halt)&&(i_dbg_we))
1132 
                        alu_reg <= i_dbg_reg;
1133 
 
1134 51 dgisselq 
        //
1135 
        // DEBUG Register write access starts here
1136 
        //
1137 21 dgisselq 
        reg             dbgv;
1138 
        initial dbgv = 1'b0;
1139 
        always @(posedge i_clk)
1140 
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
1141 51 dgisselq 
        reg     [31:0]   dbg_val;
1142 21 dgisselq 
        always @(posedge i_clk)
1143 51 dgisselq 
                dbg_val <= i_dbg_data;
1144 
        always @(posedge i_clk)
1145 21 dgisselq 
                if ((alu_ce)||(mem_ce))
1146 
                        alu_gie  <= op_gie;
1147 
        always @(posedge i_clk)
1148 
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1149 
                                &&(~mem_stalled)))
1150 
                        alu_pc  <= op_pc;
1151 
 
1152 
`ifdef  OPT_ILLEGAL_INSTRUCTION
1153 
        reg     r_alu_illegal;
1154 
        initial r_alu_illegal = 0;
1155 
        always @(posedge i_clk)
1156 
                if (clear_pipeline)
1157 
                        r_alu_illegal <= 1'b0;
1158 
                else if ((alu_ce)||(mem_ce))
1159 
                        r_alu_illegal <= op_illegal;
1160 50 dgisselq 
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1161 21 dgisselq 
`endif
1162 
 
1163 
        initial alu_pc_valid = 1'b0;
1164 51 dgisselq 
        initial mem_pc_valid = 1'b0;
1165 21 dgisselq 
        always @(posedge i_clk)
1166 51 dgisselq 
                if (i_rst)
1167 
                        alu_pc_valid <= 1'b0;
1168 
                else
1169 
                        alu_pc_valid <= (alu_ce);
1170 
        always @(posedge i_clk)
1171 
                if (i_rst)
1172 
                        mem_pc_valid <= 1'b0;
1173 
                else
1174 
                        mem_pc_valid <= (mem_ce);
1175 21 dgisselq 
 
1176 
        wire    bus_lock;
1177 
`ifdef  OPT_PIPELINED
1178 
        generate
1179 
        if (IMPLEMENT_LOCK != 0)
1180 
        begin
1181 52 dgisselq 
                reg     [1:0]    r_bus_lock;
1182 
                initial r_bus_lock = 2'b00;
1183 21 dgisselq 
                always @(posedge i_clk)
1184 
                        if (i_rst)
1185 52 dgisselq 
                                r_bus_lock <= 2'b00;
1186 21 dgisselq 
                        else if ((op_ce)&&(op_lock))
1187 52 dgisselq 
                                r_bus_lock <= 2'b11;
1188 
                        else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
1189 
                                r_bus_lock <= r_bus_lock + 2'b11;
1190 
                assign  bus_lock = |r_bus_lock;
1191 21 dgisselq 
        end else begin
1192 
                assign  bus_lock = 1'b0;
1193 
        end endgenerate
1194 
`else
1195 
        assign  bus_lock = 1'b0;
1196 
`endif
1197 
 
1198 
`ifdef  OPT_PIPELINED_BUS_ACCESS
1199 
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1200 
                                (opn[0]), opB, opA, opR,
1201 
                                mem_busy, mem_pipe_stalled,
1202 
                                mem_valid, bus_err, mem_wreg, mem_result,
1203 
                        mem_cyc_gbl, mem_cyc_lcl,
1204 
                                mem_stb_gbl, mem_stb_lcl,
1205 
                                mem_we, mem_addr, mem_data,
1206 
                                mem_ack, mem_stall, mem_err, i_wb_data);
1207 
 
1208 
`else // PIPELINED_BUS_ACCESS
1209 
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1210 
                                (opn[0]), opB, opA, opR,
1211 
                                mem_busy,
1212 
                                mem_valid, bus_err, mem_wreg, mem_result,
1213 
                        mem_cyc_gbl, mem_cyc_lcl,
1214 
                                mem_stb_gbl, mem_stb_lcl,
1215 
                                mem_we, mem_addr, mem_data,
1216 
                                mem_ack, mem_stall, mem_err, i_wb_data);
1217 
`endif // PIPELINED_BUS_ACCESS
1218 
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1219 
 
1220 
        // Either the prefetch or the instruction gets the memory bus, but
1221 
        // never both.
1222 
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1223 
                // Memory access to the arbiter, priority position
1224 
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1225 
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1226 
                // Prefetch access to the arbiter
1227 
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1228 
                        pf_ack, pf_stall, pf_err,
1229 
                // Common wires, in and out, of the arbiter
1230 
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1231 
                        o_wb_we, o_wb_addr, o_wb_data,
1232 
                        i_wb_ack, i_wb_stall, i_wb_err);
1233 
 
1234 51 dgisselq 
 
1235 
 
1236 21 dgisselq 
        //
1237 
        //
1238 51 dgisselq 
        //
1239 
        //
1240 
        //
1241 
        //
1242 
        //
1243 
        //
1244 21 dgisselq 
        //      PIPELINE STAGE #5 :: Write-back results
1245 
        //
1246 
        //
1247 
        // This stage is not allowed to stall.  If results are ready to be
1248 
        // written back, they are written back at all cost.  Sleepy CPU's
1249 
        // won't prevent write back, nor debug modes, halting the CPU, nor
1250 
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1251 
        // as knowinig something is available for writeback.
1252 
 
1253 
        //
1254 
        // Write back to our generic register set ...
1255 
        // When shall we write back?  On one of two conditions
1256 
        //      Note that the flags needed to be checked before issuing the
1257 
        //      bus instruction, so they don't need to be checked here.
1258 
        //      Further, alu_wr includes (set_cond), so we don't need to
1259 
        //      check for that here either.
1260 
`ifdef  OPT_ILLEGAL_INSTRUCTION
1261 51 dgisselq 
        assign  wr_reg_ce = (dbgv)||(~alu_illegal)&&
1262 50 dgisselq 
                        (((alu_wr)&&(~clear_pipeline)
1263 21 dgisselq 
                                &&((alu_valid)||(div_valid)||(fpu_valid)))
1264 
                        ||(mem_valid));
1265 
`else
1266 51 dgisselq 
        assign  wr_reg_ce = (dbgv)||((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
1267 21 dgisselq 
`endif
1268 
        // Which register shall be written?
1269 
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1270 
        //              One or PC, one for CC, and one for GIE match
1271 
        //      Note that the alu_reg is the register to write on a divide or
1272 
        //      FPU operation.
1273 
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1274 
        // Are we writing to the CC register?
1275 
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1276 
        // Are we writing to the PC?
1277 
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1278 
        // What value to write?
1279 
        assign  wr_reg_vl = ((mem_valid) ? mem_result
1280 
                                :((div_valid|fpu_valid))
1281 
                                        ? ((div_valid) ? div_result:fpu_result)
1282 
                                :((dbgv) ? dbg_val : alu_result));
1283 
        always @(posedge i_clk)
1284 
                if (wr_reg_ce)
1285 
                        regset[wr_reg_id] <= wr_reg_vl;
1286 
 
1287 
        //
1288 
        // Write back to the condition codes/flags register ...
1289 
        // When shall we write to our flags register?  alF_wr already
1290 
        // includes the set condition ...
1291 
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1292 
        assign  w_uflags = { uhalt_phase, ufpu_err_flag,
1293 
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1294 
                        1'b0, step, 1'b1, sleep,
1295 
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1296 
        assign  w_iflags = { ihalt_phase, ifpu_err_flag,
1297 
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1298 
                        break_en, 1'b0, 1'b0, sleep,
1299 
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1300 
 
1301 
 
1302 
        // What value to write?
1303 
        always @(posedge i_clk)
1304 
                // If explicitly writing the register itself
1305 
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1306 
                        flags <= wr_reg_vl[3:0];
1307 
                // Otherwise if we're setting the flags from an ALU operation
1308 
                else if ((wr_flags_ce)&&(alu_gie))
1309 
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1310 
                                : alu_flags);
1311 
 
1312 
        always @(posedge i_clk)
1313 
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1314 
                        iflags <= wr_reg_vl[3:0];
1315 
                else if ((wr_flags_ce)&&(~alu_gie))
1316 
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1317 
                                : alu_flags);
1318 
 
1319 
        // The 'break' enable  bit.  This bit can only be set from supervisor
1320 
        // mode.  It control what the CPU does upon encountering a break
1321 
        // instruction.
1322 
        //
1323 
        // The goal, upon encountering a break is that the CPU should stop and
1324 
        // not execute the break instruction, choosing instead to enter into
1325 
        // either interrupt mode or halt first.
1326 
        //      if ((break_en) AND (break_instruction)) // user mode or not
1327 
        //              HALT CPU
1328 
        //      else if (break_instruction) // only in user mode
1329 
        //              set an interrupt flag, go to supervisor mode
1330 
        //              allow supervisor to step the CPU.
1331 
        //      Upon a CPU halt, any break condition will be reset.  The
1332 
        //      external debugger will then need to deal with whatever
1333 
        //      condition has taken place.
1334 
        initial break_en = 1'b0;
1335 
        always @(posedge i_clk)
1336 
                if ((i_rst)||(i_halt))
1337 
                        break_en <= 1'b0;
1338 
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1339 
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1340 
`ifdef  OPT_ILLEGAL_INSTRUCTION
1341 
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1342 
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1343 
                                &&(~div_busy)&&(~fpu_busy)
1344 
                                &&(~clear_pipeline)
1345 
                        ||((~alu_gie)&&(bus_err))
1346 
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1347 
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
1348 
                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
1349 
`else
1350 
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1351 
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1352 
                                &&(~clear_pipeline))
1353 50 dgisselq 
                        ||((~alu_gie)&&(bus_err))
1354 
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1355 
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));
1356 21 dgisselq 
`endif
1357 
 
1358 
 
1359 
        // The sleep register.  Setting the sleep register causes the CPU to
1360 
        // sleep until the next interrupt.  Setting the sleep register within
1361 
        // interrupt mode causes the processor to halt until a reset.  This is
1362 
        // a panic/fault halt.  The trick is that you cannot be allowed to
1363 
        // set the sleep bit and switch to supervisor mode in the same
1364 
        // instruction: users are not allowed to halt the CPU.
1365 
        always @(posedge i_clk)
1366 
                if ((i_rst)||(w_switch_to_interrupt))
1367 
                        sleep <= 1'b0;
1368 
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1369 
                        // In supervisor mode, we have no protections.  The
1370 
                        // supervisor can set the sleep bit however he wants.
1371 
                        // Well ... not quite.  Switching to user mode and
1372 
                        // sleep mode shouold only be possible if the interrupt
1373 
                        // flag isn't set.
1374 
                        //      Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
1375 
                        //              don't set the sleep bit
1376 
                        //      otherwise however it would o.w. be set
1377 
                        sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
1378 
                                &&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
1379 
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1380 
                        // In user mode, however, you can only set the sleep
1381 
                        // mode while remaining in user mode.  You can't switch
1382 
                        // to sleep mode *and* supervisor mode at the same
1383 
                        // time, lest you halt the CPU.
1384 
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1385 
 
1386 
        always @(posedge i_clk)
1387 
                if ((i_rst)||(w_switch_to_interrupt))
1388 
                        step <= 1'b0;
1389 
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1390 
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1391 51 dgisselq 
                else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
1392 21 dgisselq 
                        step <= 1'b0;
1393 
 
1394 
        // The GIE register.  Only interrupts can disable the interrupt register
1395 
        assign  w_switch_to_interrupt = (gie)&&(
1396 
                        // On interrupt (obviously)
1397 
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1398 
                        // If we are stepping the CPU
1399 51 dgisselq 
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
1400 21 dgisselq 
                        // If we encounter a break instruction, if the break
1401 
                        //      enable isn't set.
1402 
                        ||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
1403 
                                &&(op_break)&&(~break_en))
1404 
`ifdef  OPT_ILLEGAL_INSTRUCTION
1405 
                        // On an illegal instruction
1406 
                        ||((alu_pc_valid)&&(alu_illegal))
1407 
`endif
1408 
                        // On division by zero.  If the divide isn't
1409 
                        // implemented, div_valid and div_error will be short
1410 
                        // circuited and that logic will be bypassed
1411 
                        ||((div_valid)&&(div_error))
1412 
                        // Same thing on a floating point error.
1413 
                        ||((fpu_valid)&&(fpu_error))
1414 
                        //
1415 
                        ||(bus_err)
1416 
                        // If we write to the CC register
1417 
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1418 
                                &&(wr_reg_id[4])&&(wr_write_cc))
1419 
                        );
1420 
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1421 
                        // Then if we write the CC register
1422 
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1423 
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1424 
                        );
1425 
        always @(posedge i_clk)
1426 
                if (i_rst)
1427 
                        gie <= 1'b0;
1428 
                else if (w_switch_to_interrupt)
1429 
                        gie <= 1'b0;
1430 
                else if (w_release_from_interrupt)
1431 
                        gie <= 1'b1;
1432 
 
1433 
        initial trap = 1'b0;
1434 
        always @(posedge i_clk)
1435 
                if (i_rst)
1436 
                        trap <= 1'b0;
1437 51 dgisselq 
                else if (w_release_from_interrupt)
1438 
                        trap <= 1'b0;
1439 21 dgisselq 
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1440 
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
1441 
                        trap <= 1'b1;
1442 51 dgisselq 
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
1443 
                        trap <= wr_reg_vl[`CPU_TRAP_BIT];
1444 21 dgisselq 
 
1445 
`ifdef  OPT_ILLEGAL_INSTRUCTION
1446 
        initial ill_err_i = 1'b0;
1447 
        always @(posedge i_clk)
1448 
                if (i_rst)
1449 
                        ill_err_i <= 1'b0;
1450 52 dgisselq 
                // Only the debug interface can clear this bit
1451 21 dgisselq 
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1452 
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
1453 
                        ill_err_i <= 1'b0;
1454 
                else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
1455 
                        ill_err_i <= 1'b1;
1456 
        initial ill_err_u = 1'b0;
1457 
        always @(posedge i_clk)
1458 
                if (i_rst)
1459 
                        ill_err_u <= 1'b0;
1460 
                // The bit is automatically cleared on release from interrupt
1461 
                else if (w_release_from_interrupt)
1462 
                        ill_err_u <= 1'b0;
1463 
                // If the supervisor writes to this register, clearing the
1464 
                // bit, then clear it
1465 
                else if (((~alu_gie)||(dbgv))
1466 
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
1467 
                                &&(wr_reg_id[4])&&(wr_write_cc))
1468 
                        ill_err_u <= 1'b0;
1469 
                else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
1470 
                        ill_err_u <= 1'b1;
1471 
`else
1472 
        assign ill_err_u = 1'b0;
1473 
        assign ill_err_i = 1'b0;
1474 
`endif
1475 
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1476 
        // ever set.
1477 
        initial ibus_err_flag = 1'b0;
1478 
        always @(posedge i_clk)
1479 
                if (i_rst)
1480 
                        ibus_err_flag <= 1'b0;
1481 
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1482 
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
1483 
                        ibus_err_flag <= 1'b0;
1484 
                else if ((bus_err)&&(~alu_gie))
1485 
                        ibus_err_flag <= 1'b1;
1486 
        // User bus error flag -- if ever set, it will cause an interrupt to
1487 
        // supervisor mode.
1488 
        initial ubus_err_flag = 1'b0;
1489 
        always @(posedge i_clk)
1490 
                if (i_rst)
1491 
                        ubus_err_flag <= 1'b0;
1492 
                else if (w_release_from_interrupt)
1493 
                        ubus_err_flag <= 1'b0;
1494 
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1495 
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
1496 
                                &&(wr_reg_id[4])&&(wr_write_cc))
1497 
                        ubus_err_flag <= 1'b0;
1498 
                else if ((bus_err)&&(alu_gie))
1499 
                        ubus_err_flag <= 1'b1;
1500 
 
1501 
        generate
1502 
        if (IMPLEMENT_DIVIDE != 0)
1503 
        begin
1504 
                reg     r_idiv_err_flag, r_udiv_err_flag;
1505 
 
1506 
                // Supervisor/interrupt divide (by zero) error flag -- this will
1507 
                // crash the CPU if ever set.  This bit is thus available for us
1508 
                // to be able to tell if/why the CPU crashed.
1509 
                initial r_idiv_err_flag = 1'b0;
1510 
                always @(posedge i_clk)
1511 
                        if (i_rst)
1512 
                                r_idiv_err_flag <= 1'b0;
1513 
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1514 
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT]))
1515 
                                r_idiv_err_flag <= 1'b0;
1516 
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
1517 
                                r_idiv_err_flag <= 1'b1;
1518 
                // User divide (by zero) error flag -- if ever set, it will
1519 
                // cause a sudden switch interrupt to supervisor mode.
1520 
                initial r_udiv_err_flag = 1'b0;
1521 
                always @(posedge i_clk)
1522 
                        if (i_rst)
1523 
                                r_udiv_err_flag <= 1'b0;
1524 
                        else if (w_release_from_interrupt)
1525 
                                r_udiv_err_flag <= 1'b0;
1526 
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1527 
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT])
1528 
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1529 
                                r_udiv_err_flag <= 1'b0;
1530 
                        else if ((div_error)&&(alu_gie)&&(div_valid))
1531 
                                r_udiv_err_flag <= 1'b1;
1532 
 
1533 
                assign  idiv_err_flag = r_idiv_err_flag;
1534 
                assign  udiv_err_flag = r_udiv_err_flag;
1535 
        end else begin
1536 
                assign  idiv_err_flag = 1'b0;
1537 
                assign  udiv_err_flag = 1'b0;
1538 
        end endgenerate
1539 
 
1540 
        generate
1541 
        if (IMPLEMENT_FPU !=0)
1542 
        begin
1543 
                // Supervisor/interrupt floating point error flag -- this will
1544 
                // crash the CPU if ever set.
1545 
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1546 
                initial r_ifpu_err_flag = 1'b0;
1547 
                always @(posedge i_clk)
1548 
                        if (i_rst)
1549 
                                r_ifpu_err_flag <= 1'b0;
1550 
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1551 
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT]))
1552 
                                r_ifpu_err_flag <= 1'b0;
1553 
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1554 
                                r_ifpu_err_flag <= 1'b1;
1555 
                // User floating point error flag -- if ever set, it will cause
1556 
                // a sudden switch interrupt to supervisor mode.
1557 
                initial r_ufpu_err_flag = 1'b0;
1558 
                always @(posedge i_clk)
1559 
                        if (i_rst)
1560 
                                r_ufpu_err_flag <= 1'b0;
1561 
                        else if (w_release_from_interrupt)
1562 
                                r_ufpu_err_flag <= 1'b0;
1563 
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1564 
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT])
1565 
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1566 
                                r_ufpu_err_flag <= 1'b0;
1567 
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1568 
                                r_ufpu_err_flag <= 1'b1;
1569 
 
1570 
                assign  ifpu_err_flag = r_ifpu_err_flag;
1571 
                assign  ufpu_err_flag = r_ufpu_err_flag;
1572 
        end else begin
1573 
                assign  ifpu_err_flag = 1'b0;
1574 
                assign  ufpu_err_flag = 1'b0;
1575 
        end endgenerate
1576 
 
1577 
`ifdef  OPT_VLIW
1578 
        reg             r_ihalt_phase, r_uhalt_phase;
1579 
 
1580 
        initial r_ihalt_phase = 0;
1581 
        initial r_uhalt_phase = 0;
1582 
        always @(posedge i_clk)
1583 
                if (~alu_gie)
1584 
                        r_ihalt_phase <= alu_phase;
1585 
        always @(posedge i_clk)
1586 
                if (alu_gie)
1587 
                        r_uhalt_phase <= alu_phase;
1588 
                else if (w_release_from_interrupt)
1589 
                        r_uhalt_phase <= 1'b0;
1590 
 
1591 
        assign  ihalt_phase = r_ihalt_phase;
1592 
        assign  uhalt_phase = r_uhalt_phase;
1593 
`else
1594 
        assign  ihalt_phase = 1'b0;
1595 
        assign  uhalt_phase = 1'b0;
1596 
`endif
1597 
 
1598 
        //
1599 
        // Write backs to the PC register, and general increments of it
1600 
        //      We support two: upc and ipc.  If the instruction is normal,
1601 
        // we increment upc, if interrupt level we increment ipc.  If
1602 
        // the instruction writes the PC, we write whichever PC is appropriate.
1603 
        //
1604 
        // Do we need to all our partial results from the pipeline?
1605 
        // What happens when the pipeline has gie and ~gie instructions within
1606 
        // it?  Do we clear both?  What if a gie instruction tries to clear
1607 
        // a non-gie instruction?
1608 
        always @(posedge i_clk)
1609 
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1610 
                        upc <= wr_reg_vl[(AW-1):0];
1611 51 dgisselq 
                else if ((alu_gie)&&
1612 
                                (((alu_pc_valid)&&(~clear_pipeline))
1613 
                                ||(mem_pc_valid)))
1614 21 dgisselq 
                        upc <= alu_pc;
1615 
 
1616 
        always @(posedge i_clk)
1617 
                if (i_rst)
1618 
                        ipc <= RESET_ADDRESS;
1619 
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1620 
                        ipc <= wr_reg_vl[(AW-1):0];
1621 51 dgisselq 
                else if ((~alu_gie)&&
1622 
                                (((alu_pc_valid)&&(~clear_pipeline))
1623 
                                ||(mem_pc_valid)))
1624 21 dgisselq 
                        ipc <= alu_pc;
1625 
 
1626 
        always @(posedge i_clk)
1627 
                if (i_rst)
1628 
                        pf_pc <= RESET_ADDRESS;
1629 
                else if (w_switch_to_interrupt)
1630 
                        pf_pc <= ipc;
1631 
                else if (w_release_from_interrupt)
1632 
                        pf_pc <= upc;
1633 
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1634 
                        pf_pc <= wr_reg_vl[(AW-1):0];
1635 
`ifdef  OPT_PIPELINED
1636 26 dgisselq 
                else if ((dcd_early_branch)&&(~clear_pipeline))
1637 21 dgisselq 
                        pf_pc <= dcd_branch_pc + 1;
1638 
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
1639 
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1640 
`else
1641 
                else if ((alu_pc_valid)&&(~clear_pipeline))
1642 
                        pf_pc <= alu_pc;
1643 
`endif
1644 
 
1645 
        initial new_pc = 1'b1;
1646 
        always @(posedge i_clk)
1647 
                if ((i_rst)||(i_clear_pf_cache))
1648 
                        new_pc <= 1'b1;
1649 
                else if (w_switch_to_interrupt)
1650 
                        new_pc <= 1'b1;
1651 
                else if (w_release_from_interrupt)
1652 
                        new_pc <= 1'b1;
1653 
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1654 
                        new_pc <= 1'b1;
1655 
                else
1656 
                        new_pc <= 1'b0;
1657 
 
1658 
        //
1659 
        // The debug interface
1660 
        generate
1661 
        if (AW<32)
1662 
        begin
1663 
                always @(posedge i_clk)
1664 
                begin
1665 
                        o_dbg_reg <= regset[i_dbg_reg];
1666 
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1667 
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1668 
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1669 
                        begin
1670 
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1671 
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1672 
                        end
1673 
                end
1674 
        end else begin
1675 
                always @(posedge i_clk)
1676 
                begin
1677 
                        o_dbg_reg <= regset[i_dbg_reg];
1678 
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1679 
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1680 
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1681 
                        begin
1682 
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1683 
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1684 
                        end
1685 
                end
1686 
        end endgenerate
1687 
 
1688 
        always @(posedge i_clk)
1689 
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1690 
 
1691 
        always @(posedge i_clk)
1692 
                o_dbg_stall <= (i_halt)&&(
1693 
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1694 51 dgisselq 
                        ||((~opvalid)&&(~i_rst)&&(~dcd_illegal))
1695 
                        ||((~dcdvalid)&&(~i_rst)&&(~pf_illegal)));
1696 21 dgisselq 
 
1697 
        //
1698 
        //
1699 
        // Produce accounting outputs: Account for any CPU stalls, so we can
1700 
        // later evaluate how well we are doing.
1701 
        //
1702 
        //
1703 
        assign  o_op_stall = (master_ce)&&(op_stall);
1704 
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1705 
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1706 
 
1707 
`ifdef  DEBUG_SCOPE
1708 
        always @(posedge i_clk)
1709 
                o_debug <= {
1710 52 dgisselq 
                        o_break, i_wb_err, pf_pc[1:0],
1711 51 dgisselq 
                        flags,
1712 21 dgisselq 
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1713 
                        op_ce, alu_ce, mem_ce,
1714 
                        //
1715 
                        master_ce, opvalid_alu, opvalid_mem,
1716 
                        //
1717 
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1718 
                        mem_we,
1719 
                        // ((opvalid_alu)&&(alu_stall))
1720 
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1721 
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1722 
                        // opA[23:20], opA[3:0],
1723 51 dgisselq 
                        gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
1724 21 dgisselq 
                /*
1725 
                        i_rst, master_ce, (new_pc),
1726 
                        ((dcd_early_branch)&&(dcdvalid)),
1727 
                        pf_valid, pf_illegal,
1728 
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
1729 
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1730 
                        pf_pc[7:0], pf_addr[7:0]
1731 
                */
1732 51 dgisselq 
                /*
1733 
                        i_wb_err, gie, alu_illegal,
1734 
                              (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
1735 
                        mem_busy,
1736 
                                (mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
1737 
                                        o_wb_addr[8:0] }
1738 
                                        : { instruction[31:21] },
1739 
                        pf_valid, (pf_valid) ? alu_pc[14:0]
1740 
                                :{ pf_cyc, pf_stb, pf_pc[12:0] }
1741 
                */
1742 52 dgisselq 
                /*
1743 51 dgisselq 
                        i_wb_err, gie, new_pc, dcd_early_branch,        // 4
1744 
                        pf_valid, pf_cyc, pf_stb, instruction_pc[0],    // 4
1745 
                        instruction[30:27],                             // 4
1746 
                        dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb,  // 4
1747 
                        dcdvalid,
1748 
                        ((dcd_early_branch)&&(~clear_pipeline))         // 15
1749 
                                        ? dcd_branch_pc[14:0]:pf_pc[14:0]
1750 52 dgisselq 
                */
1751 21 dgisselq 
                        };
1752 
`endif
1753 
 
1754 
endmodule

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