1 |
21 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
2 |
|
|
//
|
3 |
|
|
// Filename: zipjiffies.v
|
4 |
|
|
//
|
5 |
|
|
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
6 |
|
|
//
|
7 |
|
|
// Purpose: This peripheral is motivated by the Linux use of 'jiffies'.
|
8 |
|
|
// A process, in Linux, can request to be put to sleep until a certain
|
9 |
|
|
// number of 'jiffies' have elapsed. Using this interface, the CPU can
|
10 |
|
|
// read the number of 'jiffies' from this peripheral (it only has the
|
11 |
|
|
// one location in address space), add the sleep length to it, and
|
12 |
|
|
// write the result back to the peripheral. The zipjiffies peripheral
|
13 |
|
|
// will record the value written to it only if it is nearer the current
|
14 |
|
|
// counter value than the last current waiting interrupt time. If no
|
15 |
|
|
// other interrupts are waiting, and this time is in the future, it will
|
16 |
|
|
// be enabled. (There is currrently no way to disable a jiffie interrupt
|
17 |
|
|
// once set.) The processor may then place this sleep request into a
|
18 |
|
|
// list among other sleep requests. Once the timer expires, it would
|
19 |
|
|
// write the next jiffy request to the peripheral and wake up the process
|
20 |
|
|
// whose timer had expired.
|
21 |
|
|
//
|
22 |
|
|
// Quite elementary, really.
|
23 |
|
|
//
|
24 |
|
|
// Interface:
|
25 |
|
|
// This peripheral contains one register: a counter. Reads from the
|
26 |
|
|
// register return the current value of the counter. Writes within
|
27 |
|
|
// the (N-1) bit space following the current time set an interrupt.
|
28 |
|
|
// Writes of values that occurred in the last 2^(N-1) ticks will be
|
29 |
|
|
// ignored. The timer then interrupts when it's value equals that time.
|
30 |
|
|
// Multiple writes cause the jiffies timer to select the nearest possible
|
31 |
|
|
// interrupt. Upon an interrupt, the next interrupt time/value is cleared
|
32 |
|
|
// and will need to be reset if the CPU wants to get notified again. With
|
33 |
|
|
// only the single interface, there is no way of knowing when the next
|
34 |
|
|
// interrupt is scheduled for, neither is there any way to slow down the
|
35 |
|
|
// interrupt timer in case you don't want it overflowing as often and you
|
36 |
|
|
// wish to wait more jiffies than it supports. Thus, currently, if you
|
37 |
|
|
// have a timer you wish to wait upon that is more than 2^31 into the
|
38 |
|
|
// future, you would need to set timers along the way, wake up on those
|
39 |
|
|
// timers, and set further timer's until you finally get to your
|
40 |
|
|
// destination.
|
41 |
|
|
//
|
42 |
|
|
//
|
43 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
44 |
|
|
// Gisselquist Technology, LLC
|
45 |
|
|
//
|
46 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
47 |
|
|
//
|
48 |
|
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
49 |
|
|
//
|
50 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
51 |
|
|
// modify it under the terms of the GNU General Public License as published
|
52 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
53 |
|
|
// your option) any later version.
|
54 |
|
|
//
|
55 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
56 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
57 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
58 |
|
|
// for more details.
|
59 |
|
|
//
|
60 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
61 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
62 |
|
|
//
|
63 |
|
|
//
|
64 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
65 |
|
|
//
|
66 |
|
|
module zipjiffies(i_clk, i_ce,
|
67 |
|
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
|
68 |
|
|
o_wb_ack, o_wb_stall, o_wb_data,
|
69 |
|
|
o_int);
|
70 |
67 |
dgisselq |
parameter BW = 32;
|
71 |
21 |
dgisselq |
input i_clk, i_ce;
|
72 |
|
|
// Wishbone inputs
|
73 |
|
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
74 |
|
|
input [(BW-1):0] i_wb_data;
|
75 |
|
|
// Wishbone outputs
|
76 |
|
|
output reg o_wb_ack;
|
77 |
|
|
output wire o_wb_stall;
|
78 |
|
|
output wire [(BW-1):0] o_wb_data;
|
79 |
|
|
// Interrupt line
|
80 |
|
|
output reg o_int;
|
81 |
|
|
|
82 |
|
|
//
|
83 |
|
|
// Our counter logic: The counter is always counting up--it cannot
|
84 |
|
|
// be stopped or altered. It's really quite simple. Okay, not quite.
|
85 |
|
|
// We still support the clock enable line. We do this in order to
|
86 |
|
|
// support debugging, so that if we get everything running inside a
|
87 |
|
|
// debugger, the timer's all slow down so that everything can be stepped
|
88 |
|
|
// together, one clock at a time.
|
89 |
|
|
//
|
90 |
|
|
reg [(BW-1):0] r_counter;
|
91 |
|
|
always @(posedge i_clk)
|
92 |
|
|
if (i_ce)
|
93 |
|
|
r_counter <= r_counter+1;
|
94 |
|
|
|
95 |
|
|
//
|
96 |
|
|
// Writes to the counter set an interrupt--but only if they are in the
|
97 |
|
|
// future as determined by the signed result of an unsigned subtract.
|
98 |
|
|
//
|
99 |
|
|
reg int_set, new_set;
|
100 |
|
|
reg [(BW-1):0] int_when, new_when;
|
101 |
|
|
wire signed [(BW-1):0] till_when, till_wb;
|
102 |
|
|
assign till_when = int_when-r_counter;
|
103 |
|
|
assign till_wb = new_when-r_counter;
|
104 |
|
|
|
105 |
|
|
initial new_set = 1'b0;
|
106 |
|
|
always @(posedge i_clk)
|
107 |
67 |
dgisselq |
begin
|
108 |
21 |
dgisselq |
// Delay things by a clock to simplify our logic
|
109 |
67 |
dgisselq |
new_set <= ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
|
110 |
|
|
// new_when is a don't care when new_set = 0, so don't worry
|
111 |
|
|
// about setting it at all times.
|
112 |
|
|
new_when<= i_wb_data;
|
113 |
|
|
end
|
114 |
21 |
dgisselq |
|
115 |
|
|
initial o_int = 1'b0;
|
116 |
|
|
initial int_set = 1'b0;
|
117 |
|
|
always @(posedge i_clk)
|
118 |
|
|
begin
|
119 |
|
|
o_int <= 1'b0;
|
120 |
|
|
if ((i_ce)&&(int_set)&&(r_counter == int_when))
|
121 |
67 |
dgisselq |
// Interrupts are self-clearing
|
122 |
|
|
o_int <= 1'b1; // Set the interrupt flag for one clock
|
123 |
|
|
else if ((new_set)&&(till_wb <= 0))
|
124 |
|
|
o_int <= 1'b1;
|
125 |
21 |
dgisselq |
|
126 |
67 |
dgisselq |
if ((new_set)&&(till_wb > 0))
|
127 |
|
|
int_set <= 1'b1;
|
128 |
|
|
else if ((i_ce)&&(r_counter == int_when))
|
129 |
|
|
int_set <= 1'b0;
|
130 |
|
|
|
131 |
21 |
dgisselq |
if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
|
132 |
|
|
int_when <= new_when;
|
133 |
|
|
end
|
134 |
|
|
|
135 |
|
|
//
|
136 |
|
|
// Acknowledge any wishbone accesses -- everything we did took only
|
137 |
|
|
// one clock anyway.
|
138 |
|
|
//
|
139 |
|
|
always @(posedge i_clk)
|
140 |
|
|
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
|
141 |
|
|
|
142 |
|
|
assign o_wb_data = r_counter;
|
143 |
|
|
assign o_wb_stall = 1'b0;
|
144 |
|
|
endmodule
|