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[/] [xulalx25soc/] [trunk/] [rtl/] [ioslave.v] - Blame information for rev 2

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    ioslave
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//
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// Project:     XuLA2 board
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//
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// Purpose:     This handles a bunch of small, simple I/O registers.  To be
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//              included here, the I/O register must take exactly a single
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//      clock to access and never stall.
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//
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//      Particular peripherals include:
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//              - the interrupt controller
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//              - Realtime Clock
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//              - Realtime clock Date
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//              - A bus error register--records the address of the last
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//                      bus error.  Cannot be written to, save by a bus error.
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//      Other peripherals have been removed due to a lack of bus address space.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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`include "builddate.v"
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module  ioslave(i_clk,
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                // Wishbone control
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                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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                        o_wb_ack, o_wb_stall, o_wb_data,
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                // GPIO wires
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                i_gpio,
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                o_gpio,
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                // Other registers
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                i_bus_err_addr,
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                brd_interrupts, o_ints_to_zip_cpu, o_interrupt);
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        parameter       NGPO=15, NGPI=15;
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        input                   i_clk;
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        // Wishbone control
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        //      inputs...
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        input                   i_wb_cyc, i_wb_stb, i_wb_we;
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        input           [4:0]    i_wb_addr;
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        input           [31:0]   i_wb_data;
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        //      outputs...
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        output  reg             o_wb_ack;
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        output  wire            o_wb_stall;
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        output  wire    [31:0]   o_wb_data;
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        // GPIO
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        input   [(NGPI-1):0]     i_gpio;
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        output wire [(NGPO-1):0] o_gpio;
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        // Other registers
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        input           [31:0]   i_bus_err_addr;
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        input           [5:0]    brd_interrupts;
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        output  wire    [7:0]    o_ints_to_zip_cpu;
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        output  wire            o_interrupt;
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        wire    i_uart_rx_int, i_uart_tx_int, i_scop_int, i_flash_int,i_pwm_int;
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        assign  i_uart_tx_int = brd_interrupts[5];
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        assign  i_uart_rx_int = brd_interrupts[4];
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        assign  i_pwm_int     = brd_interrupts[3];
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        assign  i_scop_int    = brd_interrupts[2];
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        assign  i_flash_int   = brd_interrupts[1];
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        // reg          [31:0]  pwrcount;
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        // reg          [31:0]  rtccount;
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        wire            [31:0]   ictrl_data, gpio_data, date_data;
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        reg     [31:0]   r_wb_data;
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        reg             r_wb_addr;
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        always @(posedge i_clk)
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        begin
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                r_wb_addr <= i_wb_addr[4];
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                // if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr[4]))
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                // begin
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                        // casez(i_wb_addr[3:0])
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                        // // 4'h0: begin end // Reset register
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                        // // 4'h1: begin end // Status/Control register
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                        // // 4'h2: begin end // Reset register
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                        // // 4'h3: begin end // Interrupt Control register
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                        // // 4'h4: // R/O Power count
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                        // // 4'h5: // RTC count
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                        // default: begin end
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                        // endcase
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                // end else
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                if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
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                begin
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                        casez(i_wb_addr[3:0])
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                        4'h02: r_wb_data <= `DATESTAMP;
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                        4'h03: r_wb_data <= ictrl_data;
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                        4'h04: r_wb_data <= i_bus_err_addr;
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                        4'h05: r_wb_data <= date_data;
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                        4'h06: r_wb_data <= gpio_data;
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                        default: r_wb_data <= 32'h0000;
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                        endcase
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                end
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        end
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        // The interrupt controller
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        wire            ck_int;
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        wire    [7:0]    interrupt_vector;
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        assign  interrupt_vector = {
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                        i_uart_tx_int, i_uart_rx_int, i_pwm_int, gpio_int,
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                        i_scop_int, i_flash_int, ck_int, brd_interrupts[0] };
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        icontrol #(8)   intcontroller(i_clk, 1'b0,
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                                ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
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                                        &&(i_wb_addr==5'h3)), i_wb_data,
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                                ictrl_data, interrupt_vector,
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                                o_interrupt);
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        /*
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        // The ticks since power up register
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        initial pwrcount = 32'h00;
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        always @(posedge i_clk)
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                if (~ (&pwrcount))
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                        pwrcount <= pwrcount+1;
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        // The time since power up register
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        reg     [15:0]  subrtc;
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        reg             subpps;
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        initial rtccount = 32'h00;
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        initial subrtc = 16'h00;
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        always @(posedge i_clk)
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                { subpps, subrtc } <= subrtc + 16'd43;
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        always @(posedge i_clk)
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                rtccount <= rtccount + ((subpps)? 32'h1 : 32'h0);
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        */
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        //
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        // GPIO controller
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        //
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        wire    gpio_int;
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        wbgpio  #(NGPI, NGPO)
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                gpiodev(i_clk, i_wb_cyc, (i_wb_stb)&&(i_wb_addr[4:0]==5'h6),
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                        i_wb_we, i_wb_data, gpio_data, i_gpio, o_gpio,gpio_int);
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        //
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        // 4'b1xxx
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        // BUS access to a real time clock (not calendar, just clock)
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        //
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        //
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        wire    [31:0]   ck_data;
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        wire            ck_ppd;
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        rtclight #(32'h35afe5)
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                theclock(i_clk, i_wb_cyc, (i_wb_stb)&&(i_wb_addr[4]),
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                                i_wb_we, i_wb_addr[2:0], i_wb_data,
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                        ck_data, ck_int, ck_ppd);
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        wire            date_ack, date_stall;
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        rtcdate thedate(i_clk, ck_ppd,
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                        i_wb_cyc, (i_wb_stb)&&(i_wb_addr[3:0]==4'h5),
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                                i_wb_we, i_wb_data,
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                        date_ack, date_stall, date_data);
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        always @(posedge i_clk)
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                o_wb_ack <= (i_wb_stb)&&(i_wb_cyc);
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        assign  o_wb_stall = 1'b0;
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        assign  o_wb_data = (r_wb_addr)? ck_data : r_wb_data;
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        //
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        //
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        assign  o_ints_to_zip_cpu = { i_uart_tx_int, i_uart_rx_int,
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                        i_pwm_int, gpio_int, i_scop_int, i_flash_int,
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                        ck_int, o_interrupt };
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endmodule

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