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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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// Filename: jtagser.v
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//
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// Project: XuLA2 board
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//
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// Purpose: All interaction between the FPGA and the host computer on a
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// XuLA board takes place via the JTAG port and the USER
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// instruction. There is no serial port, such as I have had on the other
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// boards I have worked with. (Actually, this SoC project will have a
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// UART port, but that port will not command the bus ...) Nevertheless, I
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// still need to convert this JTAG interface into one that looks like a
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// 32-bit wishbone bus in order to be compatible with all of my other
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// work. This module is part of that conversion. This module turns bits
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// shifted into the JTAG, when it is in the shift-dr state, into bytes
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// plus a strobe output to the rest of the FPGA (you can handle a strobe
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// at all times, right?). Likewise, it takes bytes in for transmitting
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// back to the host and turns them into bits sent across this port.
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//
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//
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// Creator: Dan Gisselquist
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module jtagser(i_clk,
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o_rx_stb, o_rx_data, i_tx_stb, i_tx_data, o_tx_busy);
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input i_clk;
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//
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output reg o_rx_stb;
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output reg [7:0] o_rx_data;
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//
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input i_tx_stb;
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input [7:0] i_tx_data;
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output reg o_tx_busy;
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wire w_capture, w_drck, w_reset, w_runtest, w_sel, w_shift, w_update,
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i_tck, i_tdi, i_tms;
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reg o_tdo;
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BSCAN_SPARTAN6 #(.JTAG_CHAIN(1)) BSCANE2_inst(
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.CAPTURE(w_capture), // CAPTURE output from TAP controller
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.DRCK(w_drck), // Gated TCK output. When SEL is asserted,
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// DRCK toggles when CAPTURE or SHIFT are asserted
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.RESET(w_reset), // RESET output from tap controller
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.RUNTEST(w_runtest),
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.SEL(w_sel),
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.SHIFT(w_shift), // SHIFT output from TAP controller
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.TCK(i_tck), // Fabric connection to TCK pin
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.TDI(i_tdi), // Fabric connection to TDI pin
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.TMS(i_tms), // Fabric connection to TMS pin
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.UPDATE(w_update), // Update output from TAP controller
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.TDO(o_tdo)); // Test Data output (TDO) input pin for user func
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reg r_tck, ck_tck, last_tck, edge_tck, r_tdi, ck_tdi,
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r_shift, ck_shift, r_sel, ck_sel;
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initial r_tck = 1'b0;
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initial ck_tck = 1'b0;
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initial last_tck = 1'b0;
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initial edge_tck = 1'b0;
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always @(posedge i_clk)
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begin // 10 FF's, 1/2 - 1 LUT
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r_tck <= i_tck; ck_tck <= r_tck;
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r_shift <= w_shift; ck_shift <= r_shift;
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r_sel <= w_sel; ck_sel <= r_sel;
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r_tdi <= i_tdi; ck_tdi <= r_tdi;
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//
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last_tck <= ck_tck;
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edge_tck <= (ck_tck)&&(~last_tck);
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//
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end
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reg [2:0] state;
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initial state <= 0;
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always @(posedge i_clk) // Exactly 1 6-LUT and 3 FF's
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if (edge_tck)
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begin
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if ((~ck_sel)||(~ck_shift))
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state <= 0;
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else if ((ck_sel)&&(ck_shift))
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state <= state + 3'h1;
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end
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// Our receive data ... we'll ignore anything less than 8-bits, or
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// any fractions of a byte.
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always @(posedge i_clk)
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if (edge_tck)
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o_rx_data <= { ck_tdi, o_rx_data[7:1] };
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reg nxt_clk_stb;
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initial nxt_clk_stb = 1'b0;
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always @(posedge i_clk)
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if (edge_tck)
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nxt_clk_stb <= (edge_tck)&&(state == 3'h7)&&(ck_sel)&&(ck_shift);
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initial o_rx_stb = 1'b0;
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always @(posedge i_clk)
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if (edge_tck)
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o_rx_stb <= nxt_clk_stb;
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else o_rx_stb <=1'b0;
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reg [7:0] tx_buf;
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initial o_tdo = 1'b1;
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always @(posedge i_clk) // 12 inputs, ... ? LUTs
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if (edge_tck)
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o_tdo <= tx_buf[state];
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reg filled;
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initial filled = 1'b0;
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always @(posedge i_clk)
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begin // 2-LUTs
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if ((i_tx_stb)&&(~o_tx_busy))
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filled <= 1'b1;
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else if ((edge_tck)&&(state == 7))
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filled <= 1'b0;
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end
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always @(posedge i_clk)
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begin // tx_busy <- 8 6-bit LUTs
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if ((i_tx_stb)&&(~o_tx_busy))
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o_tx_busy <= 1'b1;
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else if ((edge_tck)&&(state == 7))
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o_tx_busy <= 1'b0;
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else if (state == 0)
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o_tx_busy <= (filled)||((ck_sel)&&(ck_shift));
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else if (state == 7)
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o_tx_busy <= 1'b1; // filled;
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else
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o_tx_busy <= 1'b1;
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end
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initial tx_buf = 8'hff;
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always @(posedge i_clk) // 8 FF's, 16-LUTs
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if ((i_tx_stb)&&(~o_tx_busy))
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tx_buf <= i_tx_data;
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else if ((edge_tck)&&(state == 7))
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tx_buf <= 8'hff;
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endmodule
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