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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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// Filename: lldspi.v
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//
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// Project: XuLA2 board
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//
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// Purpose: Reads/writes a word (user selectable number of bytes) of data
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// to/from a Quad SPI port. The port is understood to be
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// a normal SPI port unless the driver requests two bit mode. (Not yet
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// supported.) When not in use, no bits will toggle.
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//
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// Creator: Dan Gisselquist
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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`define SPI_IDLE 3'h0
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`define SPI_START 3'h1
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`define SPI_BITS 3'h2
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`define SPI_READY 3'h3
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`define SPI_HOLDING 3'h4
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`define SPI_STOP 3'h5
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`define SPI_STOP_B 3'h6
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// Modes
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// `define SPI_MOD_SPI 2'b00
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// `define QSPI_MOD_QOUT 2'b10
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// `define QSPI_MOD_QIN 2'b11
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module lldspi(i_clk,
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// Module interface
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i_wr, i_hold, i_word, i_len,
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o_word, o_valid, o_busy,
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// QSPI interface
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o_sck, o_cs_n, i_cs_n, o_mosi, i_miso);
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input i_clk;
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// Chip interface
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// Can send info
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// i_hold = 0, i_wr = 1,
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// i_word = { 1'b0, 32'info to send },
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// i_len = # of bytes in word-1
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input i_wr, i_hold;
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input [31:0] i_word;
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input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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output reg [31:0] o_word;
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output reg o_valid, o_busy;
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// Interface with the QSPI lines
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output reg o_sck;
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output reg o_cs_n;
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input i_cs_n; // Feedback from the arbiter
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output reg o_mosi;
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input i_miso;
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reg [5:0] spi_len;
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reg [31:0] r_word;
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reg [30:0] r_input;
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reg [2:0] state;
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initial state = `SPI_IDLE;
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initial o_sck = 1'b1;
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initial o_cs_n = 1'b1;
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initial o_mosi = 1'b0;
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initial o_valid = 1'b0;
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initial o_busy = 1'b0;
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initial r_input = 31'h000;
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always @(posedge i_clk)
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if ((state == `SPI_IDLE)&&(o_sck))
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begin
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o_cs_n <= 1'b1;
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o_valid <= 1'b0;
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o_busy <= 1'b0;
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if (i_wr)
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begin
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r_word <= i_word;
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state <= `SPI_START;
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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o_sck <= 1'b1;
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end
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end else if (state == `SPI_START)
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begin // We come in here with sck high, stay here 'til sck is low
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if (~i_cs_n) // Wait 'til the bus has been granted
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o_sck <= 1'b0;
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if (o_sck == 1'b0)
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begin
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state <= `SPI_BITS;
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spi_len<= spi_len - 6'h1;
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r_word <= { r_word[30:0], 1'b0 };
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end
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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o_valid <= 1'b0;
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o_mosi <= r_word[31];
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end else if (~o_sck)
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begin
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o_sck <= 1'b1;
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o_busy <= ((state != `SPI_READY)||(~i_wr));
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o_valid <= 1'b0;
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end else if (state == `SPI_BITS)
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begin
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// Should enter into here with at least a spi_len
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// of one, perhaps more
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o_sck <= 1'b0;
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o_busy <= 1'b1;
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o_mosi <= r_word[31];
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r_word <= { r_word[30:0], 1'b0 };
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spi_len <= spi_len - 6'h1;
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if (spi_len == 6'h1)
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state <= `SPI_READY;
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o_valid <= 1'b0;
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r_input <= { r_input[29:0], i_miso };
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end else if (state == `SPI_READY)
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begin
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o_valid <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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// This is the state on the last clock (both low and
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// high clocks) of the data. Data is valid during
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// this state. Here we chose to either STOP or
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// continue and transmit more.
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o_sck <= (i_hold); // No clocks while holding
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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state <= `SPI_BITS;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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// Set up the first bits on the bus
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o_mosi <= i_word[31];
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8-6'h1;
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// Read a bit upon any transition
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o_valid <= 1'b1;
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r_input <= { r_input[29:0], i_miso };
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o_word <= { r_input[30:0], i_miso };
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end else begin
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o_sck <= 1'b1;
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state <= (i_hold)?`SPI_HOLDING : `SPI_STOP;
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o_busy <= (~i_hold);
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// Read a bit upon any transition
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o_valid <= 1'b1;
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r_input <= { r_input[29:0], i_miso };
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o_word <= { r_input[30:0], i_miso };
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end
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end else if (state == `SPI_HOLDING)
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begin
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// We need this state so that the o_valid signal
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// can get strobed with our last result. Otherwise
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// we could just sit in READY waiting for a new command.
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//
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// Incidentally, the change producing this state was
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// the result of a nasty race condition. See the
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// commends in wbqspiflash for more details.
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//
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o_valid <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b0;
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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state <= `SPI_BITS;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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// Set up the first bits on the bus
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o_mosi <= i_word[31];
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b111 };
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end else begin
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o_sck <= 1'b1;
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state <= (i_hold)?`SPI_HOLDING : `SPI_STOP;
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o_busy <= (~i_hold);
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end
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end else if (state == `SPI_STOP)
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begin
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o_sck <= 1'b1; // Stop the clock
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o_valid <= 1'b0; // Output may have just been valid, but no more
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o_busy <= 1'b1; // Still busy till port is clear
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state <= `SPI_STOP_B;
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end else if (state == `SPI_STOP_B)
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begin
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o_cs_n <= 1'b1;
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o_sck <= 1'b1;
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// Do I need this????
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// spi_len <= 3; // Minimum CS high time before next cmd
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state <= `SPI_IDLE;
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o_valid <= 1'b0;
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o_busy <= 1'b1;
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end else begin // Invalid states, should never get here
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state <= `SPI_STOP;
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o_valid <= 1'b0;
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o_busy <= 1'b1;
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o_cs_n <= 1'b1;
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o_sck <= 1'b1;
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end
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endmodule
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