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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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// Filename: rtclight.v
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//
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// Project: A Wishbone Controlled Real--time Clock Core
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//
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// Purpose: Implement a real time clock, including alarm, count--down
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// timer, stopwatch, variable time frequency, and more.
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//
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// This is a light-weight version of the RTC found in this directory.
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// Unlike the full RTC, this version does not support time hacks, seven
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// segment display outputs, or LED's. It is an RTC for an internal core
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// only. (That's how I was using it on one of my projects anyway ...)
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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module rtclight(i_clk,
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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// o_wb_ack, o_wb_stb, o_wb_data, // no reads here
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// // Button inputs
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// i_btn,
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// Output registers
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o_data, // multiplexed based upon i_wb_addr
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// Output controls
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o_interrupt,
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// A once-per-day strobe on the last clock of the day
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o_ppd);
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parameter DEFAULT_SPEED = 32'd2814750; // 100 Mhz
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [2:0] i_wb_addr;
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input [31:0] i_wb_data;
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// input i_btn;
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output reg [31:0] o_data;
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output wire o_interrupt, o_ppd;
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reg [21:0] clock;
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reg [31:0] stopwatch, ckspeed;
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reg [25:0] timer;
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wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
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dgisselq |
assign ck_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
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assign tm_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign sw_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
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assign al_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
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assign sp_sel = ((i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
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dgisselq |
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reg [39:0] ck_counter;
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reg ck_carry;
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always @(posedge i_clk)
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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wire ck_pps;
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reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
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reg [7:0] ck_sub;
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initial clock = 22'h00000;
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assign ck_pps = (ck_carry)&&(ck_prepps);
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always @(posedge i_clk)
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begin
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if (ck_carry)
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ck_sub <= ck_sub + 8'h1;
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ck_prepps <= (ck_sub == 8'hff);
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if (ck_pps)
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begin // advance the seconds
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if (clock[3:0] >= 4'h9)
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clock[3:0] <= 4'h0;
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else
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clock[3:0] <= clock[3:0] + 4'h1;
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if (clock[7:0] >= 8'h59)
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clock[7:4] <= 4'h0;
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else if (clock[3:0] >= 4'h9)
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clock[7:4] <= clock[7:4] + 4'h1;
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end
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ck_ppm <= (clock[7:0] == 8'h59);
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if ((ck_pps)&&(ck_ppm))
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begin // advance the minutes
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if (clock[11:8] >= 4'h9)
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clock[11:8] <= 4'h0;
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else
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clock[11:8] <= clock[11:8] + 4'h1;
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if (clock[15:8] >= 8'h59)
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clock[15:12] <= 4'h0;
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else if (clock[11:8] >= 4'h9)
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clock[15:12] <= clock[15:12] + 4'h1;
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end
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ck_pph <= (clock[15:0] == 16'h5959);
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if ((ck_pps)&&(ck_pph))
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begin // advance the hours
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if (clock[21:16] >= 6'h23)
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begin
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clock[19:16] <= 4'h0;
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clock[21:20] <= 2'h0;
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end else if (clock[19:16] >= 4'h9)
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begin
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clock[19:16] <= 4'h0;
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clock[21:20] <= clock[21:20] + 2'h1;
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end else begin
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clock[19:16] <= clock[19:16] + 4'h1;
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end
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end
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ck_ppd <= (clock[21:0] == 22'h235959);
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if ((ck_sel)&&(i_wb_we))
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begin
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if (8'hff != i_wb_data[7:0])
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begin
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clock[7:0] <= i_wb_data[7:0];
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ck_ppm <= (i_wb_data[7:0] == 8'h59);
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end
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if (8'hff != i_wb_data[15:8])
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begin
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clock[15:8] <= i_wb_data[15:8];
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ck_pph <= (i_wb_data[15:8] == 8'h59);
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end
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if (6'h3f != i_wb_data[21:16])
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clock[21:16] <= i_wb_data[21:16];
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if (8'h00 == i_wb_data[7:0])
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ck_sub <= 8'h00;
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end
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end
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// Clock updates take several clocks, so let's make sure we
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// are only looking at a valid clock value before testing it.
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reg [21:0] ck_last_clock;
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always @(posedge i_clk)
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ck_last_clock <= clock[21:0];
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reg tm_pps, tm_ppm, tm_int;
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wire tm_stopped, tm_running, tm_alarm;
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assign tm_stopped = ~timer[24];
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assign tm_running = timer[24];
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assign tm_alarm = timer[25];
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reg [23:0] tm_start;
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reg [7:0] tm_sub;
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initial tm_start = 24'h00;
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initial timer = 26'h00;
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initial tm_int = 1'b0;
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initial tm_pps = 1'b0;
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always @(posedge i_clk)
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begin
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if (ck_carry)
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begin
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tm_sub <= tm_sub + 8'h1;
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tm_pps <= (tm_sub == 8'hff);
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end else
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tm_pps <= 1'b0;
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if ((~tm_alarm)&&(tm_running)&&(tm_pps))
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begin // If we are running ...
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timer[25] <= 1'b0;
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if (timer[23:0] == 24'h00)
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timer[25] <= 1'b1;
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else if (timer[3:0] != 4'h0)
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timer[3:0] <= timer[3:0]-4'h1;
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else begin // last digit is a zero
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timer[3:0] <= 4'h9;
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if (timer[7:4] != 4'h0)
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timer[7:4] <= timer[7:4]-4'h1;
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else begin // last two digits are zero
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timer[7:4] <= 4'h5;
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if (timer[11:8] != 4'h0)
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timer[11:8] <= timer[11:8]-4'h1;
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else begin // last three digits are zero
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timer[11:8] <= 4'h9;
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if (timer[15:12] != 4'h0)
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timer[15:12] <= timer[15:12]-4'h1;
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else begin
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timer[15:12] <= 4'h5;
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if (timer[19:16] != 4'h0)
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timer[19:16] <= timer[19:16]-4'h1;
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else begin
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//
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timer[19:16] <= 4'h9;
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timer[23:20] <= timer[23:20]-4'h1;
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end
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end
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end
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end
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end
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end
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if((~tm_alarm)&&(tm_running))
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begin
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timer[25] <= (timer[23:0] == 24'h00);
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tm_int <= (timer[23:0] == 24'h00);
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end else tm_int <= 1'b0;
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if (tm_alarm)
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timer[24] <= 1'b0;
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if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
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// Only allowed to stop the timer, nothing more
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timer[24] <= i_wb_data[24];
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else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
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begin
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timer[24] <= i_wb_data[24];
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if ((timer[24])||(i_wb_data[24]))
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timer[25] <= 1'b0;
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if (i_wb_data[23:0] != 24'h0000)
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begin
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timer[23:0] <= i_wb_data[23:0];
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tm_start <= i_wb_data[23:0];
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tm_sub <= 8'h00;
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end else if (timer[23:0] == 24'h00)
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begin // Resetting timer to last valid timer start val
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timer[23:0] <= tm_start;
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tm_sub <= 8'h00;
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end
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// Any write clears the alarm
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timer[25] <= 1'b0;
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end
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end
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//
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// Stopwatch functionality
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//
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// Setting bit '0' starts the stop watch, clearing it stops it.
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// Writing to the register with bit '1' high will clear the stopwatch,
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// and return it to zero provided that the stopwatch is stopped either
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// before or after the write. Hence, writing a '2' to the device
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// will always stop and clear it, whereas writing a '3' to the device
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// will only clear it if it was already stopped.
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| 254 |
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reg sw_pps, sw_ppm, sw_pph;
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| 255 |
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reg [7:0] sw_sub;
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wire sw_running;
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assign sw_running = stopwatch[0];
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initial stopwatch = 32'h00000;
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always @(posedge i_clk)
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begin
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sw_pps <= 1'b0;
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if (sw_running)
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begin
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if (ck_carry)
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begin
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sw_sub <= sw_sub + 8'h1;
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sw_pps <= (sw_sub == 8'hff);
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| 268 |
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end
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| 269 |
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end
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| 270 |
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stopwatch[7:1] <= sw_sub[7:1];
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if (sw_pps)
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begin // Second hand
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| 275 |
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if (stopwatch[11:8] >= 4'h9)
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stopwatch[11:8] <= 4'h0;
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else
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| 278 |
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stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
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| 279 |
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| 280 |
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if (stopwatch[15:8] >= 8'h59)
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| 281 |
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stopwatch[15:12] <= 4'h0;
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| 282 |
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else if (stopwatch[11:8] >= 4'h9)
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| 283 |
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stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
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| 284 |
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sw_ppm <= (stopwatch[15:8] == 8'h59);
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| 285 |
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end else sw_ppm <= 1'b0;
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| 286 |
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| 287 |
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if (sw_ppm)
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| 288 |
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begin // Minutes
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| 289 |
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if (stopwatch[19:16] >= 4'h9)
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| 290 |
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stopwatch[19:16] <= 4'h0;
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| 291 |
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else
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| 292 |
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stopwatch[19:16] <= stopwatch[19:16]+4'h1;
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| 294 |
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if (stopwatch[23:16] >= 8'h59)
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| 295 |
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stopwatch[23:20] <= 4'h0;
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| 296 |
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else if (stopwatch[19:16] >= 4'h9)
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stopwatch[23:20] <= stopwatch[23:20]+4'h1;
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| 298 |
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sw_pph <= (stopwatch[23:16] == 8'h59);
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| 299 |
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end else sw_pph <= 1'b0;
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| 300 |
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| 301 |
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if (sw_pph)
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begin // And hours
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| 303 |
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if (stopwatch[27:24] >= 4'h9)
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stopwatch[27:24] <= 4'h0;
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| 305 |
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else
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stopwatch[27:24] <= stopwatch[27:24]+4'h1;
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| 307 |
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| 308 |
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if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
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| 309 |
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stopwatch[31:28] <= stopwatch[27:24]+4'h1;
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| 310 |
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end
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| 311 |
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| 312 |
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if ((sw_sel)&&(i_wb_we))
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| 313 |
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begin
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| 314 |
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stopwatch[0] <= i_wb_data[0];
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| 315 |
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if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
|
| 316 |
|
|
begin
|
| 317 |
|
|
stopwatch[31:1] <= 31'h00;
|
| 318 |
|
|
sw_sub <= 8'h00;
|
| 319 |
|
|
sw_pps <= 1'b0;
|
| 320 |
|
|
sw_ppm <= 1'b0;
|
| 321 |
|
|
sw_pph <= 1'b0;
|
| 322 |
|
|
end
|
| 323 |
|
|
end
|
| 324 |
|
|
end
|
| 325 |
|
|
|
| 326 |
|
|
//
|
| 327 |
|
|
// The alarm code
|
| 328 |
|
|
//
|
| 329 |
|
|
// Set the alarm register to the time you wish the board to "alarm".
|
| 330 |
|
|
// The "alarm" will take place once per day at that time. At that
|
| 331 |
|
|
// time, the RTC code will generate a clock interrupt, and the CPU/host
|
| 332 |
|
|
// can come and see that the alarm tripped.
|
| 333 |
|
|
//
|
| 334 |
|
|
//
|
| 335 |
|
|
reg [21:0] alarm_time;
|
| 336 |
|
|
reg al_int, // The alarm interrupt line
|
| 337 |
|
|
al_enabled, // Whether the alarm is enabled
|
| 338 |
|
|
al_tripped; // Whether the alarm has tripped
|
| 339 |
|
|
initial al_enabled= 1'b0;
|
| 340 |
|
|
initial al_tripped= 1'b0;
|
| 341 |
|
|
always @(posedge i_clk)
|
| 342 |
|
|
begin
|
| 343 |
|
|
if ((al_sel)&&(i_wb_we))
|
| 344 |
|
|
begin
|
| 345 |
|
|
// Only adjust the alarm hours if the requested hours
|
| 346 |
|
|
// are valid. This allows writes to the register,
|
| 347 |
|
|
// without a prior read, to leave these configuration
|
| 348 |
|
|
// bits alone.
|
| 349 |
|
|
if (i_wb_data[21:16] != 6'h3f)
|
| 350 |
|
|
alarm_time[21:16] <= i_wb_data[21:16];
|
| 351 |
|
|
// Here's the same thing for the minutes: only adjust
|
| 352 |
|
|
// the alarm minutes if the new bits are not all 1's.
|
| 353 |
|
|
if (i_wb_data[15:8] != 8'hff)
|
| 354 |
|
|
alarm_time[15:8] <= i_wb_data[15:8];
|
| 355 |
|
|
// Here's the same thing for the seconds: only adjust
|
| 356 |
|
|
// the alarm minutes if the new bits are not all 1's.
|
| 357 |
|
|
if (i_wb_data[7:0] != 8'hff)
|
| 358 |
|
|
alarm_time[7:0] <= i_wb_data[7:0];
|
| 359 |
|
|
al_enabled <= i_wb_data[24];
|
| 360 |
|
|
// Reset the alarm if a '1' is written to the tripped
|
| 361 |
|
|
// register, or if the alarm is disabled.
|
| 362 |
|
|
if ((i_wb_data[25])||(~i_wb_data[24]))
|
| 363 |
|
|
al_tripped <= 1'b0;
|
| 364 |
|
|
end
|
| 365 |
|
|
|
| 366 |
|
|
al_int <= 1'b0;
|
| 367 |
|
|
if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)
|
| 368 |
|
|
&&(al_enabled))
|
| 369 |
|
|
begin
|
| 370 |
|
|
al_tripped <= 1'b1;
|
| 371 |
|
|
al_int <= 1'b1;
|
| 372 |
|
|
end
|
| 373 |
|
|
end
|
| 374 |
|
|
|
| 375 |
|
|
//
|
| 376 |
|
|
// The ckspeed register is equal to 2^48 divded by the number of
|
| 377 |
|
|
// clock ticks you expect per second. Adjust high for a slower
|
| 378 |
|
|
// clock, lower for a faster clock. In this fashion, a single
|
| 379 |
|
|
// real time clock RTL file can handle tracking the clock in any
|
| 380 |
|
|
// device. Further, because this is only the lower 32 bits of a
|
| 381 |
|
|
// 48 bit counter per seconds, the clock jitter is kept below
|
| 382 |
|
|
// 1 part in 65 thousand.
|
| 383 |
|
|
//
|
| 384 |
|
|
initial ckspeed = DEFAULT_SPEED; // 2af31e = 2^48 / 100e6 MHz
|
| 385 |
|
|
// In the case of verilator, comment the above and uncomment the line
|
| 386 |
|
|
// below. The clock constant below is "close" to simulation time,
|
| 387 |
|
|
// meaning that my verilator simulation is running about 300x slower
|
| 388 |
|
|
// than board time.
|
| 389 |
|
|
// initial ckspeed = 32'd786432000;
|
| 390 |
|
|
always @(posedge i_clk)
|
| 391 |
|
|
if ((sp_sel)&&(i_wb_we))
|
| 392 |
|
|
ckspeed <= i_wb_data;
|
| 393 |
|
|
|
| 394 |
|
|
assign o_interrupt = tm_int || al_int;
|
| 395 |
|
|
|
| 396 |
|
|
// A once-per day strobe, on the last second of the day so that the
|
| 397 |
|
|
// the next clock is the first clock of the day. This is useful for
|
| 398 |
|
|
// connecting this module to a year/month/date date/calendar module.
|
| 399 |
|
|
assign o_ppd = (ck_ppd)&&(ck_pps);
|
| 400 |
|
|
|
| 401 |
|
|
always @(posedge i_clk)
|
| 402 |
|
|
case(i_wb_addr[2:0])
|
| 403 |
|
|
3'b000: o_data <= { 10'h0, ck_last_clock };
|
| 404 |
|
|
3'b001: o_data <= { 6'h00, timer };
|
| 405 |
|
|
3'b010: o_data <= stopwatch;
|
| 406 |
|
|
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
|
| 407 |
|
|
3'b100: o_data <= ckspeed;
|
| 408 |
|
|
default: o_data <= 32'h000;
|
| 409 |
|
|
endcase
|
| 410 |
|
|
|
| 411 |
|
|
endmodule
|
