| 1 |
21 |
dgisselq |
///////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//
|
| 3 |
|
|
// Filename: rtclight.v
|
| 4 |
|
|
//
|
| 5 |
|
|
// Project: A Wishbone Controlled Real--time Clock Core
|
| 6 |
|
|
//
|
| 7 |
|
|
// Purpose: Implement a real time clock, including alarm, count--down
|
| 8 |
|
|
// timer, stopwatch, variable time frequency, and more.
|
| 9 |
|
|
//
|
| 10 |
|
|
// This is a light-weight version of the RTC found in this directory.
|
| 11 |
|
|
// Unlike the full RTC, this version does not support time hacks, seven
|
| 12 |
|
|
// segment display outputs, or LED's. It is an RTC for an internal core
|
| 13 |
|
|
// only. (That's how I was using it on one of my projects anyway ...)
|
| 14 |
|
|
//
|
| 15 |
|
|
//
|
| 16 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 17 |
|
|
// Gisselquist Technology, LLC
|
| 18 |
|
|
//
|
| 19 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 20 |
|
|
//
|
| 21 |
|
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
| 22 |
|
|
//
|
| 23 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
| 24 |
|
|
// modify it under the terms of the GNU General Public License as published
|
| 25 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
| 26 |
|
|
// your option) any later version.
|
| 27 |
|
|
//
|
| 28 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
| 29 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
| 30 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 31 |
|
|
// for more details.
|
| 32 |
|
|
//
|
| 33 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 34 |
|
|
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
| 35 |
|
|
// target there if the PDF file isn't present.) If not, see
|
| 36 |
|
|
// <http://www.gnu.org/licenses/> for a copy.
|
| 37 |
|
|
//
|
| 38 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
| 39 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
| 40 |
|
|
//
|
| 41 |
|
|
//
|
| 42 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 43 |
|
|
module rtclight(i_clk,
|
| 44 |
|
|
// Wishbone interface
|
| 45 |
|
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
| 46 |
|
|
// o_wb_ack, o_wb_stb, o_wb_data, // no reads here
|
| 47 |
|
|
// // Button inputs
|
| 48 |
|
|
// i_btn,
|
| 49 |
|
|
// Output registers
|
| 50 |
|
|
o_data, // multiplexed based upon i_wb_addr
|
| 51 |
|
|
// Output controls
|
| 52 |
|
|
o_interrupt,
|
| 53 |
|
|
// A once-per-day strobe on the last clock of the day
|
| 54 |
|
|
o_ppd);
|
| 55 |
|
|
parameter DEFAULT_SPEED = 32'd2814750; // 100 Mhz
|
| 56 |
|
|
input i_clk;
|
| 57 |
|
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
| 58 |
|
|
input [2:0] i_wb_addr;
|
| 59 |
|
|
input [31:0] i_wb_data;
|
| 60 |
|
|
// input i_btn;
|
| 61 |
|
|
output reg [31:0] o_data;
|
| 62 |
|
|
output wire o_interrupt, o_ppd;
|
| 63 |
|
|
|
| 64 |
|
|
reg [21:0] clock;
|
| 65 |
|
|
reg [31:0] stopwatch, ckspeed;
|
| 66 |
|
|
reg [25:0] timer;
|
| 67 |
|
|
|
| 68 |
|
|
wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
|
| 69 |
|
|
assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
|
| 70 |
|
|
assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
|
| 71 |
|
|
assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
|
| 72 |
|
|
assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
|
| 73 |
|
|
assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
|
| 74 |
|
|
|
| 75 |
|
|
reg [39:0] ck_counter;
|
| 76 |
|
|
reg ck_carry;
|
| 77 |
|
|
always @(posedge i_clk)
|
| 78 |
|
|
{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
|
| 79 |
|
|
|
| 80 |
|
|
wire ck_pps;
|
| 81 |
|
|
reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
|
| 82 |
|
|
reg [7:0] ck_sub;
|
| 83 |
|
|
initial clock = 22'h00000;
|
| 84 |
|
|
assign ck_pps = (ck_carry)&&(ck_prepps);
|
| 85 |
|
|
always @(posedge i_clk)
|
| 86 |
|
|
begin
|
| 87 |
|
|
if (ck_carry)
|
| 88 |
|
|
ck_sub <= ck_sub + 8'h1;
|
| 89 |
|
|
ck_prepps <= (ck_sub == 8'hff);
|
| 90 |
|
|
|
| 91 |
|
|
if (ck_pps)
|
| 92 |
|
|
begin // advance the seconds
|
| 93 |
|
|
if (clock[3:0] >= 4'h9)
|
| 94 |
|
|
clock[3:0] <= 4'h0;
|
| 95 |
|
|
else
|
| 96 |
|
|
clock[3:0] <= clock[3:0] + 4'h1;
|
| 97 |
|
|
if (clock[7:0] >= 8'h59)
|
| 98 |
|
|
clock[7:4] <= 4'h0;
|
| 99 |
|
|
else if (clock[3:0] >= 4'h9)
|
| 100 |
|
|
clock[7:4] <= clock[7:4] + 4'h1;
|
| 101 |
|
|
end
|
| 102 |
|
|
ck_ppm <= (clock[7:0] == 8'h59);
|
| 103 |
|
|
|
| 104 |
|
|
if ((ck_pps)&&(ck_ppm))
|
| 105 |
|
|
begin // advance the minutes
|
| 106 |
|
|
if (clock[11:8] >= 4'h9)
|
| 107 |
|
|
clock[11:8] <= 4'h0;
|
| 108 |
|
|
else
|
| 109 |
|
|
clock[11:8] <= clock[11:8] + 4'h1;
|
| 110 |
|
|
if (clock[15:8] >= 8'h59)
|
| 111 |
|
|
clock[15:12] <= 4'h0;
|
| 112 |
|
|
else if (clock[11:8] >= 4'h9)
|
| 113 |
|
|
clock[15:12] <= clock[15:12] + 4'h1;
|
| 114 |
|
|
end
|
| 115 |
|
|
ck_pph <= (clock[15:0] == 16'h5959);
|
| 116 |
|
|
|
| 117 |
|
|
if ((ck_pps)&&(ck_pph))
|
| 118 |
|
|
begin // advance the hours
|
| 119 |
|
|
if (clock[21:16] >= 6'h23)
|
| 120 |
|
|
begin
|
| 121 |
|
|
clock[19:16] <= 4'h0;
|
| 122 |
|
|
clock[21:20] <= 2'h0;
|
| 123 |
|
|
end else if (clock[19:16] >= 4'h9)
|
| 124 |
|
|
begin
|
| 125 |
|
|
clock[19:16] <= 4'h0;
|
| 126 |
|
|
clock[21:20] <= clock[21:20] + 2'h1;
|
| 127 |
|
|
end else begin
|
| 128 |
|
|
clock[19:16] <= clock[19:16] + 4'h1;
|
| 129 |
|
|
end
|
| 130 |
|
|
end
|
| 131 |
|
|
ck_ppd <= (clock[21:0] == 22'h235959);
|
| 132 |
|
|
|
| 133 |
|
|
|
| 134 |
|
|
if ((ck_sel)&&(i_wb_we))
|
| 135 |
|
|
begin
|
| 136 |
|
|
if (8'hff != i_wb_data[7:0])
|
| 137 |
|
|
begin
|
| 138 |
|
|
clock[7:0] <= i_wb_data[7:0];
|
| 139 |
|
|
ck_ppm <= (i_wb_data[7:0] == 8'h59);
|
| 140 |
|
|
end
|
| 141 |
|
|
if (8'hff != i_wb_data[15:8])
|
| 142 |
|
|
begin
|
| 143 |
|
|
clock[15:8] <= i_wb_data[15:8];
|
| 144 |
|
|
ck_pph <= (i_wb_data[15:8] == 8'h59);
|
| 145 |
|
|
end
|
| 146 |
|
|
if (6'h3f != i_wb_data[21:16])
|
| 147 |
|
|
clock[21:16] <= i_wb_data[21:16];
|
| 148 |
|
|
if (8'h00 == i_wb_data[7:0])
|
| 149 |
|
|
ck_sub <= 8'h00;
|
| 150 |
|
|
end
|
| 151 |
|
|
end
|
| 152 |
|
|
|
| 153 |
|
|
// Clock updates take several clocks, so let's make sure we
|
| 154 |
|
|
// are only looking at a valid clock value before testing it.
|
| 155 |
|
|
reg [21:0] ck_last_clock;
|
| 156 |
|
|
always @(posedge i_clk)
|
| 157 |
|
|
ck_last_clock <= clock[21:0];
|
| 158 |
|
|
|
| 159 |
|
|
|
| 160 |
|
|
reg tm_pps, tm_ppm, tm_int;
|
| 161 |
|
|
wire tm_stopped, tm_running, tm_alarm;
|
| 162 |
|
|
assign tm_stopped = ~timer[24];
|
| 163 |
|
|
assign tm_running = timer[24];
|
| 164 |
|
|
assign tm_alarm = timer[25];
|
| 165 |
|
|
reg [23:0] tm_start;
|
| 166 |
|
|
reg [7:0] tm_sub;
|
| 167 |
|
|
initial tm_start = 24'h00;
|
| 168 |
|
|
initial timer = 26'h00;
|
| 169 |
|
|
initial tm_int = 1'b0;
|
| 170 |
|
|
initial tm_pps = 1'b0;
|
| 171 |
|
|
always @(posedge i_clk)
|
| 172 |
|
|
begin
|
| 173 |
|
|
if (ck_carry)
|
| 174 |
|
|
begin
|
| 175 |
|
|
tm_sub <= tm_sub + 8'h1;
|
| 176 |
|
|
tm_pps <= (tm_sub == 8'hff);
|
| 177 |
|
|
end else
|
| 178 |
|
|
tm_pps <= 1'b0;
|
| 179 |
|
|
|
| 180 |
|
|
if ((~tm_alarm)&&(tm_running)&&(tm_pps))
|
| 181 |
|
|
begin // If we are running ...
|
| 182 |
|
|
timer[25] <= 1'b0;
|
| 183 |
|
|
if (timer[23:0] == 24'h00)
|
| 184 |
|
|
timer[25] <= 1'b1;
|
| 185 |
|
|
else if (timer[3:0] != 4'h0)
|
| 186 |
|
|
timer[3:0] <= timer[3:0]-4'h1;
|
| 187 |
|
|
else begin // last digit is a zero
|
| 188 |
|
|
timer[3:0] <= 4'h9;
|
| 189 |
|
|
if (timer[7:4] != 4'h0)
|
| 190 |
|
|
timer[7:4] <= timer[7:4]-4'h1;
|
| 191 |
|
|
else begin // last two digits are zero
|
| 192 |
|
|
timer[7:4] <= 4'h5;
|
| 193 |
|
|
if (timer[11:8] != 4'h0)
|
| 194 |
|
|
timer[11:8] <= timer[11:8]-4'h1;
|
| 195 |
|
|
else begin // last three digits are zero
|
| 196 |
|
|
timer[11:8] <= 4'h9;
|
| 197 |
|
|
if (timer[15:12] != 4'h0)
|
| 198 |
|
|
timer[15:12] <= timer[15:12]-4'h1;
|
| 199 |
|
|
else begin
|
| 200 |
|
|
timer[15:12] <= 4'h5;
|
| 201 |
|
|
if (timer[19:16] != 4'h0)
|
| 202 |
|
|
timer[19:16] <= timer[19:16]-4'h1;
|
| 203 |
|
|
else begin
|
| 204 |
|
|
//
|
| 205 |
|
|
timer[19:16] <= 4'h9;
|
| 206 |
|
|
timer[23:20] <= timer[23:20]-4'h1;
|
| 207 |
|
|
end
|
| 208 |
|
|
end
|
| 209 |
|
|
end
|
| 210 |
|
|
end
|
| 211 |
|
|
end
|
| 212 |
|
|
end
|
| 213 |
|
|
|
| 214 |
|
|
if((~tm_alarm)&&(tm_running))
|
| 215 |
|
|
begin
|
| 216 |
|
|
timer[25] <= (timer[23:0] == 24'h00);
|
| 217 |
|
|
tm_int <= (timer[23:0] == 24'h00);
|
| 218 |
|
|
end else tm_int <= 1'b0;
|
| 219 |
|
|
if (tm_alarm)
|
| 220 |
|
|
timer[24] <= 1'b0;
|
| 221 |
|
|
|
| 222 |
|
|
if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
|
| 223 |
|
|
// Only allowed to stop the timer, nothing more
|
| 224 |
|
|
timer[24] <= i_wb_data[24];
|
| 225 |
|
|
else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
|
| 226 |
|
|
begin
|
| 227 |
|
|
timer[24] <= i_wb_data[24];
|
| 228 |
|
|
if ((timer[24])||(i_wb_data[24]))
|
| 229 |
|
|
timer[25] <= 1'b0;
|
| 230 |
|
|
if (i_wb_data[23:0] != 24'h0000)
|
| 231 |
|
|
begin
|
| 232 |
|
|
timer[23:0] <= i_wb_data[23:0];
|
| 233 |
|
|
tm_start <= i_wb_data[23:0];
|
| 234 |
|
|
tm_sub <= 8'h00;
|
| 235 |
|
|
end else if (timer[23:0] == 24'h00)
|
| 236 |
|
|
begin // Resetting timer to last valid timer start val
|
| 237 |
|
|
timer[23:0] <= tm_start;
|
| 238 |
|
|
tm_sub <= 8'h00;
|
| 239 |
|
|
end
|
| 240 |
|
|
// Any write clears the alarm
|
| 241 |
|
|
timer[25] <= 1'b0;
|
| 242 |
|
|
end
|
| 243 |
|
|
end
|
| 244 |
|
|
|
| 245 |
|
|
//
|
| 246 |
|
|
// Stopwatch functionality
|
| 247 |
|
|
//
|
| 248 |
|
|
// Setting bit '0' starts the stop watch, clearing it stops it.
|
| 249 |
|
|
// Writing to the register with bit '1' high will clear the stopwatch,
|
| 250 |
|
|
// and return it to zero provided that the stopwatch is stopped either
|
| 251 |
|
|
// before or after the write. Hence, writing a '2' to the device
|
| 252 |
|
|
// will always stop and clear it, whereas writing a '3' to the device
|
| 253 |
|
|
// will only clear it if it was already stopped.
|
| 254 |
|
|
reg sw_pps, sw_ppm, sw_pph;
|
| 255 |
|
|
reg [7:0] sw_sub;
|
| 256 |
|
|
wire sw_running;
|
| 257 |
|
|
assign sw_running = stopwatch[0];
|
| 258 |
|
|
initial stopwatch = 32'h00000;
|
| 259 |
|
|
always @(posedge i_clk)
|
| 260 |
|
|
begin
|
| 261 |
|
|
sw_pps <= 1'b0;
|
| 262 |
|
|
if (sw_running)
|
| 263 |
|
|
begin
|
| 264 |
|
|
if (ck_carry)
|
| 265 |
|
|
begin
|
| 266 |
|
|
sw_sub <= sw_sub + 8'h1;
|
| 267 |
|
|
sw_pps <= (sw_sub == 8'hff);
|
| 268 |
|
|
end
|
| 269 |
|
|
end
|
| 270 |
|
|
|
| 271 |
|
|
stopwatch[7:1] <= sw_sub[7:1];
|
| 272 |
|
|
|
| 273 |
|
|
if (sw_pps)
|
| 274 |
|
|
begin // Second hand
|
| 275 |
|
|
if (stopwatch[11:8] >= 4'h9)
|
| 276 |
|
|
stopwatch[11:8] <= 4'h0;
|
| 277 |
|
|
else
|
| 278 |
|
|
stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
|
| 279 |
|
|
|
| 280 |
|
|
if (stopwatch[15:8] >= 8'h59)
|
| 281 |
|
|
stopwatch[15:12] <= 4'h0;
|
| 282 |
|
|
else if (stopwatch[11:8] >= 4'h9)
|
| 283 |
|
|
stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
|
| 284 |
|
|
sw_ppm <= (stopwatch[15:8] == 8'h59);
|
| 285 |
|
|
end else sw_ppm <= 1'b0;
|
| 286 |
|
|
|
| 287 |
|
|
if (sw_ppm)
|
| 288 |
|
|
begin // Minutes
|
| 289 |
|
|
if (stopwatch[19:16] >= 4'h9)
|
| 290 |
|
|
stopwatch[19:16] <= 4'h0;
|
| 291 |
|
|
else
|
| 292 |
|
|
stopwatch[19:16] <= stopwatch[19:16]+4'h1;
|
| 293 |
|
|
|
| 294 |
|
|
if (stopwatch[23:16] >= 8'h59)
|
| 295 |
|
|
stopwatch[23:20] <= 4'h0;
|
| 296 |
|
|
else if (stopwatch[19:16] >= 4'h9)
|
| 297 |
|
|
stopwatch[23:20] <= stopwatch[23:20]+4'h1;
|
| 298 |
|
|
sw_pph <= (stopwatch[23:16] == 8'h59);
|
| 299 |
|
|
end else sw_pph <= 1'b0;
|
| 300 |
|
|
|
| 301 |
|
|
if (sw_pph)
|
| 302 |
|
|
begin // And hours
|
| 303 |
|
|
if (stopwatch[27:24] >= 4'h9)
|
| 304 |
|
|
stopwatch[27:24] <= 4'h0;
|
| 305 |
|
|
else
|
| 306 |
|
|
stopwatch[27:24] <= stopwatch[27:24]+4'h1;
|
| 307 |
|
|
|
| 308 |
|
|
if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
|
| 309 |
|
|
stopwatch[31:28] <= stopwatch[27:24]+4'h1;
|
| 310 |
|
|
end
|
| 311 |
|
|
|
| 312 |
|
|
if ((sw_sel)&&(i_wb_we))
|
| 313 |
|
|
begin
|
| 314 |
|
|
stopwatch[0] <= i_wb_data[0];
|
| 315 |
|
|
if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
|
| 316 |
|
|
begin
|
| 317 |
|
|
stopwatch[31:1] <= 31'h00;
|
| 318 |
|
|
sw_sub <= 8'h00;
|
| 319 |
|
|
sw_pps <= 1'b0;
|
| 320 |
|
|
sw_ppm <= 1'b0;
|
| 321 |
|
|
sw_pph <= 1'b0;
|
| 322 |
|
|
end
|
| 323 |
|
|
end
|
| 324 |
|
|
end
|
| 325 |
|
|
|
| 326 |
|
|
//
|
| 327 |
|
|
// The alarm code
|
| 328 |
|
|
//
|
| 329 |
|
|
// Set the alarm register to the time you wish the board to "alarm".
|
| 330 |
|
|
// The "alarm" will take place once per day at that time. At that
|
| 331 |
|
|
// time, the RTC code will generate a clock interrupt, and the CPU/host
|
| 332 |
|
|
// can come and see that the alarm tripped.
|
| 333 |
|
|
//
|
| 334 |
|
|
//
|
| 335 |
|
|
reg [21:0] alarm_time;
|
| 336 |
|
|
reg al_int, // The alarm interrupt line
|
| 337 |
|
|
al_enabled, // Whether the alarm is enabled
|
| 338 |
|
|
al_tripped; // Whether the alarm has tripped
|
| 339 |
|
|
initial al_enabled= 1'b0;
|
| 340 |
|
|
initial al_tripped= 1'b0;
|
| 341 |
|
|
always @(posedge i_clk)
|
| 342 |
|
|
begin
|
| 343 |
|
|
if ((al_sel)&&(i_wb_we))
|
| 344 |
|
|
begin
|
| 345 |
|
|
// Only adjust the alarm hours if the requested hours
|
| 346 |
|
|
// are valid. This allows writes to the register,
|
| 347 |
|
|
// without a prior read, to leave these configuration
|
| 348 |
|
|
// bits alone.
|
| 349 |
|
|
if (i_wb_data[21:16] != 6'h3f)
|
| 350 |
|
|
alarm_time[21:16] <= i_wb_data[21:16];
|
| 351 |
|
|
// Here's the same thing for the minutes: only adjust
|
| 352 |
|
|
// the alarm minutes if the new bits are not all 1's.
|
| 353 |
|
|
if (i_wb_data[15:8] != 8'hff)
|
| 354 |
|
|
alarm_time[15:8] <= i_wb_data[15:8];
|
| 355 |
|
|
// Here's the same thing for the seconds: only adjust
|
| 356 |
|
|
// the alarm minutes if the new bits are not all 1's.
|
| 357 |
|
|
if (i_wb_data[7:0] != 8'hff)
|
| 358 |
|
|
alarm_time[7:0] <= i_wb_data[7:0];
|
| 359 |
|
|
al_enabled <= i_wb_data[24];
|
| 360 |
|
|
// Reset the alarm if a '1' is written to the tripped
|
| 361 |
|
|
// register, or if the alarm is disabled.
|
| 362 |
|
|
if ((i_wb_data[25])||(~i_wb_data[24]))
|
| 363 |
|
|
al_tripped <= 1'b0;
|
| 364 |
|
|
end
|
| 365 |
|
|
|
| 366 |
|
|
al_int <= 1'b0;
|
| 367 |
|
|
if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)
|
| 368 |
|
|
&&(al_enabled))
|
| 369 |
|
|
begin
|
| 370 |
|
|
al_tripped <= 1'b1;
|
| 371 |
|
|
al_int <= 1'b1;
|
| 372 |
|
|
end
|
| 373 |
|
|
end
|
| 374 |
|
|
|
| 375 |
|
|
//
|
| 376 |
|
|
// The ckspeed register is equal to 2^48 divded by the number of
|
| 377 |
|
|
// clock ticks you expect per second. Adjust high for a slower
|
| 378 |
|
|
// clock, lower for a faster clock. In this fashion, a single
|
| 379 |
|
|
// real time clock RTL file can handle tracking the clock in any
|
| 380 |
|
|
// device. Further, because this is only the lower 32 bits of a
|
| 381 |
|
|
// 48 bit counter per seconds, the clock jitter is kept below
|
| 382 |
|
|
// 1 part in 65 thousand.
|
| 383 |
|
|
//
|
| 384 |
|
|
initial ckspeed = DEFAULT_SPEED; // 2af31e = 2^48 / 100e6 MHz
|
| 385 |
|
|
// In the case of verilator, comment the above and uncomment the line
|
| 386 |
|
|
// below. The clock constant below is "close" to simulation time,
|
| 387 |
|
|
// meaning that my verilator simulation is running about 300x slower
|
| 388 |
|
|
// than board time.
|
| 389 |
|
|
// initial ckspeed = 32'd786432000;
|
| 390 |
|
|
always @(posedge i_clk)
|
| 391 |
|
|
if ((sp_sel)&&(i_wb_we))
|
| 392 |
|
|
ckspeed <= i_wb_data;
|
| 393 |
|
|
|
| 394 |
|
|
assign o_interrupt = tm_int || al_int;
|
| 395 |
|
|
|
| 396 |
|
|
// A once-per day strobe, on the last second of the day so that the
|
| 397 |
|
|
// the next clock is the first clock of the day. This is useful for
|
| 398 |
|
|
// connecting this module to a year/month/date date/calendar module.
|
| 399 |
|
|
assign o_ppd = (ck_ppd)&&(ck_pps);
|
| 400 |
|
|
|
| 401 |
|
|
always @(posedge i_clk)
|
| 402 |
|
|
case(i_wb_addr[2:0])
|
| 403 |
|
|
3'b000: o_data <= { 10'h0, ck_last_clock };
|
| 404 |
|
|
3'b001: o_data <= { 6'h00, timer };
|
| 405 |
|
|
3'b010: o_data <= stopwatch;
|
| 406 |
|
|
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
|
| 407 |
|
|
3'b100: o_data <= ckspeed;
|
| 408 |
|
|
default: o_data <= 32'h000;
|
| 409 |
|
|
endcase
|
| 410 |
|
|
|
| 411 |
|
|
endmodule
|
