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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    rxuart.v
//
// Project:     XuLA2 board
//
// Purpose:     Receive and decode inputs from a single UART line.
//
//
//      To interface with this module, connect it to your system clock,
//      pass it the 32 bit setup register (defined below) and the UART
//      input.  When data becomes available, the o_wr line will be asserted
//      for one clock cycle.  On parity or frame errors, the o_parity_err
//      or o_frame_err lines will be asserted.  Likewise, on a break 
//      condition, o_break will be asserted.  These lines are self clearing.
//
//      There is a synchronous reset line, logic high.
//
//      Now for the setup register.  The register is 32 bits, so that this
//      UART may be set up over a 32-bit bus.
//
//      i_setup[29:28]  Indicates the number of data bits per word.  This will
//      either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
//      for a six bit word, or 2'b11 for a five bit word.
//
//      i_setup[27]     Indicates whether or not to use one or two stop bits.
//              Set this to one to expect two stop bits, zero for one.
//
//      i_setup[26]     Indicates whether or not a parity bit exists.  Set this
//              to 1'b1 to include parity.
//
//      i_setup[25]     Indicates whether or not the parity bit is fixed.  Set
//              to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
//              parity to be set based upon data.  (Both assume the parity
//              enable value is set.)
//
//      i_setup[24]     This bit is ignored if parity is not used.  Otherwise,
//              in the case of a fixed parity bit, this bit indicates whether
//              mark (1'b1) or space (1'b0) parity is used.  Likewise if the
//              parity is not fixed, a 1'b1 selects even parity, and 1'b0
//              selects odd.
//
//      i_setup[23:0]   Indicates the speed of the UART in terms of clocks.
//              So, for example, if you have a 200 MHz clock and wish to
//              run your UART at 9600 baud, you would take 200 MHz and divide
//              by 9600 to set this value to 24'd20834.  Likewise if you wished
//              to run this serial port at 115200 baud from a 200 MHz clock,
//              you would set the value to 24'd1736
//
//      Thus, to set the UART for the common setting of an 8-bit word, 
//      one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
//      would want to set the setup value to:
//
//      32'h0006c8              // For 115,200 baud, 8 bit, no parity
//      32'h005161              // For 9600 baud, 8 bit, no parity
//      
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
// States: (@ baud counter == 0)
//      0        First bit arrives
//      ..7     Bits arrive
//      8       Stop bit (x1)
//      9       Stop bit (x2)
///     c       break condition
//      d       Waiting for the channel to go high
//      e       Waiting for the reset to complete
//      f       Idle state
`define RXU_BIT_ZERO            4'h0
`define RXU_BIT_ONE             4'h1
`define RXU_BIT_TWO             4'h2
`define RXU_BIT_THREE           4'h3
`define RXU_BIT_FOUR            4'h4
`define RXU_BIT_FIVE            4'h5
`define RXU_BIT_SIX             4'h6
`define RXU_BIT_SEVEN           4'h7
`define RXU_PARITY              4'h8
`define RXU_STOP                4'h9
`define RXU_SECOND_STOP         4'ha
// Unused 4'hb
// Unused 4'hc
`define RXU_BREAK               4'hd
`define RXU_RESET_IDLE          4'he
`define RXU_IDLE                4'hf
 
module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
                        o_parity_err, o_frame_err);
        //  parameter // CLOCKS_PER_BAUD = 25'd004340,
                        //  BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
                        //  CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
        // 8 data bits, no parity, (at least 1) stop bit
        input                   i_clk, i_reset;
        input           [29:0]   i_setup;
        input                   i_uart;
        output  reg             o_wr;
        output  reg     [7:0]    o_data;
        output  reg             o_break;
        output  reg             o_parity_err, o_frame_err;
 
 
        wire    [27:0]   clocks_per_baud, break_condition, half_baud;
        wire    [1:0]    data_bits;
        wire            use_parity, parity_even, dblstop, fixd_parity;
        reg     [29:0]   r_setup;
        assign  clocks_per_baud = { 4'h0, r_setup[23:0] };
        assign  data_bits   = r_setup[29:28];
        assign  dblstop     = r_setup[27];
        assign  use_parity  = r_setup[26];
        assign  fixd_parity = r_setup[25];
        assign  parity_even = r_setup[24];
        assign  break_condition = { r_setup[23:0], 4'h0 };
        assign  half_baud = { 5'h00, r_setup[23:1] };
 
        reg     q_uart, qq_uart, ck_uart;
        initial q_uart  = 1'b0;
        initial qq_uart = 1'b0;
        initial ck_uart = 1'b0;
        always @(posedge i_clk)
        begin
                q_uart <= i_uart;
                qq_uart <= q_uart;
                ck_uart <= qq_uart;
        end
 
        reg     [27:0]   chg_counter;
        initial chg_counter = 28'h00;
        always @(posedge i_clk)
                if (i_reset)
                        chg_counter <= 28'h00;
                else if (qq_uart != ck_uart)
                        chg_counter <= 28'h00;
                else if (chg_counter < break_condition)
                        chg_counter <= chg_counter + 1;
 
        reg     line_synch;
        initial line_synch = 1'b0;
        initial o_break    = 1'b0;
        always @(posedge i_clk)
                o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
        always @(posedge i_clk)
                line_synch <= ((chg_counter >= break_condition)&&(ck_uart));
 
        reg     [3:0]    state;
        reg     [27:0]   baud_counter;
        reg     [7:0]    data_reg;
        reg             calc_parity, zero_baud_counter, half_baud_time;
        initial o_wr = 1'b0;
        initial state = `RXU_RESET_IDLE;
        initial o_parity_err = 1'b0;
        initial o_frame_err  = 1'b0;
        // initial      baud_counter = clocks_per_baud;
        always @(posedge i_clk)
        begin
                if (i_reset)
                begin
                        o_wr <= 1'b0;
                        o_data <= 8'h00;
                        state <= `RXU_RESET_IDLE;
                        baud_counter <= clocks_per_baud-28'h01;// Set, not reset
                        data_reg <= 8'h00;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                end else if (state == `RXU_RESET_IDLE)
                begin
                        r_setup <= i_setup;
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
                        baud_counter <= clocks_per_baud-28'h01;// Set, not reset
                        if (line_synch)
                                // Goto idle state from a reset
                                state <= `RXU_IDLE;
                        else // Otherwise, stay in this condition 'til reset
                                state <= `RXU_RESET_IDLE;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                end else if (o_break)
                begin // We are in a break condition
                        state <= `RXU_BREAK;
                        o_wr <= 1'b0;
                        o_data <= 8'h00;
                        baud_counter <= clocks_per_baud-28'h01;// Set, not reset
                        data_reg <= 8'h00;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                        r_setup <= i_setup;
                end else if (state == `RXU_BREAK)
                begin // Goto idle state following return ck_uart going high
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
                        baud_counter <= clocks_per_baud - 28'h01;
                        if (ck_uart)
                                state <= `RXU_IDLE;
                        else
                                state <= `RXU_BREAK;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                        r_setup <= i_setup;
                end else if (state == `RXU_IDLE)
                begin // Idle state, independent of baud counter
                        r_setup <= i_setup;
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
                        baud_counter <= clocks_per_baud - 28'h01;
                        if ((~ck_uart)&&(half_baud_time))
                        begin
                                // We are in the center of a valid start bit
                                case (data_bits)
                                2'b00: state <= `RXU_BIT_ZERO;
                                2'b01: state <= `RXU_BIT_ONE;
                                2'b10: state <= `RXU_BIT_TWO;
                                2'b11: state <= `RXU_BIT_THREE;
                                endcase
                        end else // Otherwise, just stay here in idle
                                state <= `RXU_IDLE;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                end else if (zero_baud_counter)
                begin
                        baud_counter <= clocks_per_baud-28'h1;
                        if (state < `RXU_BIT_SEVEN)
                        begin
                                // Data arrives least significant bit first.
                                // By the time this is clocked in, it's what
                                // you'll have.
                                data_reg <= { ck_uart, data_reg[7:1] };
                                calc_parity <= calc_parity ^ ck_uart;
                                o_data <= 8'h00;
                                o_wr <= 1'b0;
                                state <= state + 1;
                                o_parity_err <= 1'b0;
                                o_frame_err <= 1'b0;
                        end else if (state == `RXU_BIT_SEVEN)
                        begin
                                data_reg <= { ck_uart, data_reg[7:1] };
                                calc_parity <= calc_parity ^ ck_uart;
                                o_data <= 8'h00;
                                o_wr <= 1'b0;
                                state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
                                o_parity_err <= 1'b0;
                                o_frame_err <= 1'b0;
                        end else if (state == `RXU_PARITY)
                        begin
                                if (fixd_parity)
                                        o_parity_err <= (ck_uart ^ parity_even);
                                else
                                        o_parity_err <= ((parity_even && (calc_parity != ck_uart))
                                                ||((~parity_even)&&(calc_parity==ck_uart)));
                                state <= `RXU_STOP;
                                o_frame_err <= 1'b0;
                        end else if (state == `RXU_STOP)
                        begin // Stop (or parity) bit(s)
                                case (data_bits)
                                2'b00: o_data <= data_reg;
                                2'b01: o_data <= { 1'b0, data_reg[7:1] };
                                2'b10: o_data <= { 2'b0, data_reg[7:2] };
                                2'b11: o_data <= { 3'b0, data_reg[7:3] };
                                endcase
                                o_wr <= 1'b1; // Pulse the write
                                o_frame_err <= (~ck_uart);
                                if (~ck_uart)
                                        state <= `RXU_RESET_IDLE;
                                else if (dblstop)
                                        state <= `RXU_SECOND_STOP;
                                else
                                        state <= `RXU_IDLE;
                                // o_parity_err <= 1'b0;
                        end else // state must equal RX_SECOND_STOP
                        begin
                                if (~ck_uart)
                                begin
                                        o_frame_err <= 1'b1;
                                        state <= `RXU_RESET_IDLE;
                                end else begin
                                        state <= `RXU_IDLE;
                                        o_frame_err  <= 1'b0;
                                end
                                o_parity_err <= 1'b0;
                        end
                end else begin
                        o_wr <= 1'b0;   // data_reg = data_reg
                        baud_counter <= baud_counter - 28'd1;
                        o_parity_err <= 1'b0;
                        o_frame_err  <= 1'b0;
                end
        end
 
        initial zero_baud_counter = 1'b0;
        always @(posedge i_clk)
                zero_baud_counter <= (baud_counter == 28'h01);
 
        initial half_baud_time = 0;
        always @(posedge i_clk)
                half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	7	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2	2	dgisselq	`//`
3			`// Filename: rxuart.v`
4			`//`
5	7	dgisselq	`// Project: XuLA2 board`
6	2	dgisselq	`//`
7			`// Purpose: Receive and decode inputs from a single UART line.`
8			`//`
9	99	dgisselq	`//`
10	2	dgisselq	`// To interface with this module, connect it to your system clock,`
11			`// pass it the 32 bit setup register (defined below) and the UART`
12			`// input. When data becomes available, the o_wr line will be asserted`
13			`// for one clock cycle. On parity or frame errors, the o_parity_err`
14			`// or o_frame_err lines will be asserted. Likewise, on a break`
15			`// condition, o_break will be asserted. These lines are self clearing.`
16			`//`
17			`// There is a synchronous reset line, logic high.`
18			`//`
19			`// Now for the setup register. The register is 32 bits, so that this`
20			`// UART may be set up over a 32-bit bus.`
21			`//`
22			`// i_setup[29:28] Indicates the number of data bits per word. This will`
23			`// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10`
24			`// for a six bit word, or 2'b11 for a five bit word.`
25			`//`
26			`// i_setup[27] Indicates whether or not to use one or two stop bits.`
27			`// Set this to one to expect two stop bits, zero for one.`
28			`//`
29			`// i_setup[26] Indicates whether or not a parity bit exists. Set this`
30			`// to 1'b1 to include parity.`
31			`//`
32			`// i_setup[25] Indicates whether or not the parity bit is fixed. Set`
33			`// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the`
34			`// parity to be set based upon data. (Both assume the parity`
35			`// enable value is set.)`
36			`//`
37			`// i_setup[24] This bit is ignored if parity is not used. Otherwise,`
38			`// in the case of a fixed parity bit, this bit indicates whether`
39			`// mark (1'b1) or space (1'b0) parity is used. Likewise if the`
40			`// parity is not fixed, a 1'b1 selects even parity, and 1'b0`
41			`// selects odd.`
42			`//`
43			`// i_setup[23:0] Indicates the speed of the UART in terms of clocks.`
44			`// So, for example, if you have a 200 MHz clock and wish to`
45			`// run your UART at 9600 baud, you would take 200 MHz and divide`
46			`// by 9600 to set this value to 24'd20834. Likewise if you wished`
47			`// to run this serial port at 115200 baud from a 200 MHz clock,`
48			`// you would set the value to 24'd1736`
49			`//`
50			`// Thus, to set the UART for the common setting of an 8-bit word,`
51			`// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you`
52			`// would want to set the setup value to:`
53			`//`
54			`// 32'h0006c8 // For 115,200 baud, 8 bit, no parity`
55			`// 32'h005161 // For 9600 baud, 8 bit, no parity`
56			`//`
57	7	dgisselq	`//`
58			`//`
59			`// Creator: Dan Gisselquist, Ph.D.`
60	2	dgisselq	`// Gisselquist Technology, LLC`
61			`//`
62	7	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
63	2	dgisselq	`//`
64	99	dgisselq	`// Copyright (C) 2015-2016, Gisselquist Technology, LLC`
65	2	dgisselq	`//`
66	7	dgisselq	`// This program is free software (firmware): you can redistribute it and/or`
67			`// modify it under the terms of the GNU General Public License as published`
68			`// by the Free Software Foundation, either version 3 of the License, or (at`
69			`// your option) any later version.`
70	2	dgisselq	`//`
71	7	dgisselq	`// This program is distributed in the hope that it will be useful, but WITHOUT`
72			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
73			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
74			`// for more details.`
75	2	dgisselq	`//`
76	99	dgisselq	`// You should have received a copy of the GNU General Public License along`
77			`// with this program. (It's in the $(ROOT)/doc directory, run make with no`
78			`// target there if the PDF file isn't present.) If not, see`
79			`// <http://www.gnu.org/licenses/> for a copy.`
80			`//`
81	7	dgisselq	`// License: GPL, v3, as defined and found on www.gnu.org,`
82			`// http://www.gnu.org/licenses/gpl.html`
83	2	dgisselq	`//`
84	7	dgisselq	`//`
85			`////////////////////////////////////////////////////////////////////////////////`
86			`//`
87			`//`
88	2	dgisselq	`// States: (@ baud counter == 0)`
89			`// 0 First bit arrives`
90			`// ..7 Bits arrive`
91			`// 8 Stop bit (x1)`
92			`// 9 Stop bit (x2)`
93			`/// c break condition`
94			`// d Waiting for the channel to go high`
95			`// e Waiting for the reset to complete`
96			`// f Idle state`
97			`define RXU_BIT_ZERO 4'h0
98			`define RXU_BIT_ONE 4'h1
99			`define RXU_BIT_TWO 4'h2
100			`define RXU_BIT_THREE 4'h3
101			`define RXU_BIT_FOUR 4'h4
102			`define RXU_BIT_FIVE 4'h5
103			`define RXU_BIT_SIX 4'h6
104			`define RXU_BIT_SEVEN 4'h7
105			`define RXU_PARITY 4'h8
106			`define RXU_STOP 4'h9
107			`define RXU_SECOND_STOP 4'ha
108			`// Unused 4'hb`
109			`// Unused 4'hc`
110			`define RXU_BREAK 4'hd
111			`define RXU_RESET_IDLE 4'he
112			`define RXU_IDLE 4'hf
113
114			`module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,`
115	9	dgisselq	`o_parity_err, o_frame_err);`
116	2	dgisselq	`// parameter // CLOCKS_PER_BAUD = 25'd004340,`
117			`// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,`
118			`// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;`
119			`// 8 data bits, no parity, (at least 1) stop bit`
120			`input i_clk, i_reset;`
121			`input [29:0] i_setup;`
122			`input i_uart;`
123			`output reg o_wr;`
124			`output reg [7:0] o_data;`
125			`output reg o_break;`
126			`output reg o_parity_err, o_frame_err;`
127
128
129			`wire [27:0] clocks_per_baud, break_condition, half_baud;`
130			`wire [1:0] data_bits;`
131			`wire use_parity, parity_even, dblstop, fixd_parity;`
132			`reg [29:0] r_setup;`
133			`assign clocks_per_baud = { 4'h0, r_setup[23:0] };`
134			`assign data_bits = r_setup[29:28];`
135			`assign dblstop = r_setup[27];`
136			`assign use_parity = r_setup[26];`
137			`assign fixd_parity = r_setup[25];`
138			`assign parity_even = r_setup[24];`
139			`assign break_condition = { r_setup[23:0], 4'h0 };`
140			`assign half_baud = { 5'h00, r_setup[23:1] };`
141
142			`reg q_uart, qq_uart, ck_uart;`
143			`initial q_uart = 1'b0;`
144			`initial qq_uart = 1'b0;`
145			`initial ck_uart = 1'b0;`
146			`always @(posedge i_clk)`
147			`begin`
148			`q_uart <= i_uart;`
149			`qq_uart <= q_uart;`
150			`ck_uart <= qq_uart;`
151			`end`
152
153			`reg [27:0] chg_counter;`
154			`initial chg_counter = 28'h00;`
155			`always @(posedge i_clk)`
156			`if (i_reset)`
157			`chg_counter <= 28'h00;`
158			`else if (qq_uart != ck_uart)`
159			`chg_counter <= 28'h00;`
160			`else if (chg_counter < break_condition)`
161			`chg_counter <= chg_counter + 1;`
162
163	99	dgisselq	`reg line_synch;`
164			`initial line_synch = 1'b0;`
165			`initial o_break = 1'b0;`
166	2	dgisselq	`always @(posedge i_clk)`
167	99	dgisselq	`o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;`
168			`always @(posedge i_clk)`
169			`line_synch <= ((chg_counter >= break_condition)&&(ck_uart));`
170	2	dgisselq
171			`reg [3:0] state;`
172			`reg [27:0] baud_counter;`
173			`reg [7:0] data_reg;`
174	99	dgisselq	`reg calc_parity, zero_baud_counter, half_baud_time;`
175	2	dgisselq	`initial o_wr = 1'b0;`
176			initial state = `RXU_RESET_IDLE;
177			`initial o_parity_err = 1'b0;`
178			`initial o_frame_err = 1'b0;`
179			`// initial baud_counter = clocks_per_baud;`
180			`always @(posedge i_clk)`
181			`begin`
182			`if (i_reset)`
183			`begin`
184			`o_wr <= 1'b0;`
185			`o_data <= 8'h00;`
186			state <= `RXU_RESET_IDLE;
187	99	dgisselq	`baud_counter <= clocks_per_baud-28'h01;// Set, not reset`
188	2	dgisselq	`data_reg <= 8'h00;`
189			`calc_parity <= 1'b0;`
190			`o_parity_err <= 1'b0;`
191			`o_frame_err <= 1'b0;`
192			end else if (state == `RXU_RESET_IDLE)
193			`begin`
194			`r_setup <= i_setup;`
195			`data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;`
196			`baud_counter <= clocks_per_baud-28'h01;// Set, not reset`
197	99	dgisselq	`if (line_synch)`
198	2	dgisselq	`// Goto idle state from a reset`
199			state <= `RXU_IDLE;
200			`else // Otherwise, stay in this condition 'til reset`
201			state <= `RXU_RESET_IDLE;
202			`calc_parity <= 1'b0;`
203			`o_parity_err <= 1'b0;`
204			`o_frame_err <= 1'b0;`
205	99	dgisselq	`end else if (o_break)`
206	2	dgisselq	`begin // We are in a break condition`
207			state <= `RXU_BREAK;
208			`o_wr <= 1'b0;`
209			`o_data <= 8'h00;`
210			`baud_counter <= clocks_per_baud-28'h01;// Set, not reset`
211			`data_reg <= 8'h00;`
212			`calc_parity <= 1'b0;`
213			`o_parity_err <= 1'b0;`
214			`o_frame_err <= 1'b0;`
215			`r_setup <= i_setup;`
216			end else if (state == `RXU_BREAK)
217			`begin // Goto idle state following return ck_uart going high`
218			`data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;`
219			`baud_counter <= clocks_per_baud - 28'h01;`
220			`if (ck_uart)`
221			state <= `RXU_IDLE;
222			`else`
223			state <= `RXU_BREAK;
224			`calc_parity <= 1'b0;`
225			`o_parity_err <= 1'b0;`
226			`o_frame_err <= 1'b0;`
227			`r_setup <= i_setup;`
228			end else if (state == `RXU_IDLE)
229			`begin // Idle state, independent of baud counter`
230	58	dgisselq	`r_setup <= i_setup;`
231	2	dgisselq	`data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;`
232			`baud_counter <= clocks_per_baud - 28'h01;`
233	99	dgisselq	`if ((~ck_uart)&&(half_baud_time))`
234	2	dgisselq	`begin`
235			`// We are in the center of a valid start bit`
236			`case (data_bits)`
237			2'b00: state <= `RXU_BIT_ZERO;
238			2'b01: state <= `RXU_BIT_ONE;
239			2'b10: state <= `RXU_BIT_TWO;
240			2'b11: state <= `RXU_BIT_THREE;
241			`endcase`
242			`end else // Otherwise, just stay here in idle`
243			state <= `RXU_IDLE;
244			`calc_parity <= 1'b0;`
245			`o_parity_err <= 1'b0;`
246			`o_frame_err <= 1'b0;`
247	99	dgisselq	`end else if (zero_baud_counter)`
248	2	dgisselq	`begin`
249			`baud_counter <= clocks_per_baud-28'h1;`
250			if (state < `RXU_BIT_SEVEN)
251			`begin`
252			`// Data arrives least significant bit first.`
253			`// By the time this is clocked in, it's what`
254			`// you'll have.`
255			`data_reg <= { ck_uart, data_reg[7:1] };`
256			`calc_parity <= calc_parity ^ ck_uart;`
257			`o_data <= 8'h00;`
258			`o_wr <= 1'b0;`
259			`state <= state + 1;`
260			`o_parity_err <= 1'b0;`
261			`o_frame_err <= 1'b0;`
262			end else if (state == `RXU_BIT_SEVEN)
263			`begin`
264			`data_reg <= { ck_uart, data_reg[7:1] };`
265			`calc_parity <= calc_parity ^ ck_uart;`
266			`o_data <= 8'h00;`
267			`o_wr <= 1'b0;`
268			state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
269			`o_parity_err <= 1'b0;`
270			`o_frame_err <= 1'b0;`
271			end else if (state == `RXU_PARITY)
272			`begin`
273			`if (fixd_parity)`
274			`o_parity_err <= (ck_uart ^ parity_even);`
275			`else`
276			`o_parity_err <= ((parity_even && (calc_parity != ck_uart))`
277			`\|\|((~parity_even)&&(calc_parity==ck_uart)));`
278			state <= `RXU_STOP;
279			`o_frame_err <= 1'b0;`
280			end else if (state == `RXU_STOP)
281			`begin // Stop (or parity) bit(s)`
282			`case (data_bits)`
283			`2'b00: o_data <= data_reg;`
284			`2'b01: o_data <= { 1'b0, data_reg[7:1] };`
285			`2'b10: o_data <= { 2'b0, data_reg[7:2] };`
286			`2'b11: o_data <= { 3'b0, data_reg[7:3] };`
287			`endcase`
288			`o_wr <= 1'b1; // Pulse the write`
289			`o_frame_err <= (~ck_uart);`
290			`if (~ck_uart)`
291			state <= `RXU_RESET_IDLE;
292			`else if (dblstop)`
293			state <= `RXU_SECOND_STOP;
294			`else`
295			state <= `RXU_IDLE;
296			`// o_parity_err <= 1'b0;`
297			`end else // state must equal RX_SECOND_STOP`
298			`begin`
299			`if (~ck_uart)`
300			`begin`
301			`o_frame_err <= 1'b1;`
302			state <= `RXU_RESET_IDLE;
303			`end else begin`
304			state <= `RXU_IDLE;
305			`o_frame_err <= 1'b0;`
306			`end`
307			`o_parity_err <= 1'b0;`
308			`end`
309			`end else begin`
310			`o_wr <= 1'b0; // data_reg = data_reg`
311	18	dgisselq	`baud_counter <= baud_counter - 28'd1;`
312	2	dgisselq	`o_parity_err <= 1'b0;`
313			`o_frame_err <= 1'b0;`
314			`end`
315			`end`
316
317	99	dgisselq	`initial zero_baud_counter = 1'b0;`
318			`always @(posedge i_clk)`
319			`zero_baud_counter <= (baud_counter == 28'h01);`
320
321			`initial half_baud_time = 0;`
322			`always @(posedge i_clk)`
323			`half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);`
324
325
326	2	dgisselq	`endmodule`
327
328

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