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[/] [xulalx25soc/] [trunk/] [rtl/] [rxuart.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////////
//
//
// Filename:    rxuart.v
//
// Project:     FPGA library development (Spartan 3E development board)
//
// Purpose:     Receive and decode inputs from a single UART line.
//
//
//      To interface with this module, connect it to your system clock,
//      pass it the 32 bit setup register (defined below) and the UART
//      input.  When data becomes available, the o_wr line will be asserted
//      for one clock cycle.  On parity or frame errors, the o_parity_err
//      or o_frame_err lines will be asserted.  Likewise, on a break 
//      condition, o_break will be asserted.  These lines are self clearing.
//
//      There is a synchronous reset line, logic high.
//
//      Now for the setup register.  The register is 32 bits, so that this
//      UART may be set up over a 32-bit bus.
//
//      i_setup[29:28]  Indicates the number of data bits per word.  This will
//      either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
//      for a six bit word, or 2'b11 for a five bit word.
//
//      i_setup[27]     Indicates whether or not to use one or two stop bits.
//              Set this to one to expect two stop bits, zero for one.
//
//      i_setup[26]     Indicates whether or not a parity bit exists.  Set this
//              to 1'b1 to include parity.
//
//      i_setup[25]     Indicates whether or not the parity bit is fixed.  Set
//              to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
//              parity to be set based upon data.  (Both assume the parity
//              enable value is set.)
//
//      i_setup[24]     This bit is ignored if parity is not used.  Otherwise,
//              in the case of a fixed parity bit, this bit indicates whether
//              mark (1'b1) or space (1'b0) parity is used.  Likewise if the
//              parity is not fixed, a 1'b1 selects even parity, and 1'b0
//              selects odd.
//
//      i_setup[23:0]   Indicates the speed of the UART in terms of clocks.
//              So, for example, if you have a 200 MHz clock and wish to
//              run your UART at 9600 baud, you would take 200 MHz and divide
//              by 9600 to set this value to 24'd20834.  Likewise if you wished
//              to run this serial port at 115200 baud from a 200 MHz clock,
//              you would set the value to 24'd1736
//
//      Thus, to set the UART for the common setting of an 8-bit word, 
//      one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
//      would want to set the setup value to:
//
//      32'h0006c8              // For 115,200 baud, 8 bit, no parity
//      32'h005161              // For 9600 baud, 8 bit, no parity
//      
// Creator:     Dan Gisselquist
//              Gisselquist Technology, LLC
//
// Copyright:   2015
//
//
/////////////////////////////////////////////////////////////////////////
//
// This software is the ownership of Gisselquist Technology, LLC, and as
// such it is proprietary.  It is provided without any warrantees, either
// express or implied, so that it may be tested.  Upon completion, I ask
// that working code be returned and not further distributed beyond those
// that it is originally offered to.
//
// Thank you.
//
 
// States: (@ baud counter == 0)
//      0        First bit arrives
//      ..7     Bits arrive
//      8       Stop bit (x1)
//      9       Stop bit (x2)
///     c       break condition
//      d       Waiting for the channel to go high
//      e       Waiting for the reset to complete
//      f       Idle state
`define RXU_BIT_ZERO            4'h0
`define RXU_BIT_ONE             4'h1
`define RXU_BIT_TWO             4'h2
`define RXU_BIT_THREE           4'h3
`define RXU_BIT_FOUR            4'h4
`define RXU_BIT_FIVE            4'h5
`define RXU_BIT_SIX             4'h6
`define RXU_BIT_SEVEN           4'h7
`define RXU_PARITY              4'h8
`define RXU_STOP                4'h9
`define RXU_SECOND_STOP         4'ha
// Unused 4'hb
// Unused 4'hc
`define RXU_BREAK               4'hd
`define RXU_RESET_IDLE          4'he
`define RXU_IDLE                4'hf
 
module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
                        o_parity_err, o_frame_err, o_ck_uart);
        //  parameter // CLOCKS_PER_BAUD = 25'd004340,
                        //  BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
                        //  CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
        // 8 data bits, no parity, (at least 1) stop bit
        input                   i_clk, i_reset;
        input           [29:0]   i_setup;
        input                   i_uart;
        output  reg             o_wr;
        output  reg     [7:0]    o_data;
        output  reg             o_break;
        output  reg             o_parity_err, o_frame_err;
        output  wire            o_ck_uart;
 
 
        wire    [27:0]   clocks_per_baud, break_condition, half_baud;
        wire    [1:0]    data_bits;
        wire            use_parity, parity_even, dblstop, fixd_parity;
        reg     [29:0]   r_setup;
        assign  clocks_per_baud = { 4'h0, r_setup[23:0] };
        assign  data_bits   = r_setup[29:28];
        assign  dblstop     = r_setup[27];
        assign  use_parity  = r_setup[26];
        assign  fixd_parity = r_setup[25];
        assign  parity_even = r_setup[24];
        assign  break_condition = { r_setup[23:0], 4'h0 };
        assign  half_baud = { 5'h00, r_setup[23:1] };
 
        reg     q_uart, qq_uart, ck_uart;
        initial q_uart  = 1'b0;
        initial qq_uart = 1'b0;
        initial ck_uart = 1'b0;
        always @(posedge i_clk)
        begin
                q_uart <= i_uart;
                qq_uart <= q_uart;
                ck_uart <= qq_uart;
        end
        assign  o_ck_uart = ck_uart;
 
        reg     [27:0]   chg_counter;
        initial chg_counter = 28'h00;
        always @(posedge i_clk)
                if (i_reset)
                        chg_counter <= 28'h00;
                else if (qq_uart != ck_uart)
                        chg_counter <= 28'h00;
                else if (chg_counter < break_condition)
                        chg_counter <= chg_counter + 1;
 
        always @(posedge i_clk)
                o_break <=((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
 
        reg     [3:0]    state;
        reg     [27:0]   baud_counter;
        reg     [7:0]    data_reg;
        reg             calc_parity;
        initial o_wr = 1'b0;
        initial state = `RXU_RESET_IDLE;
        initial o_parity_err = 1'b0;
        initial o_frame_err  = 1'b0;
        // initial      baud_counter = clocks_per_baud;
        always @(posedge i_clk)
        begin
                if (i_reset)
                begin
                        o_wr <= 1'b0;
                        o_data <= 8'h00;
                        state <= `RXU_RESET_IDLE;
                        baud_counter <= clocks_per_baud; // Set, not reset
                        data_reg <= 8'h00;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                end else if (state == `RXU_RESET_IDLE)
                begin
                        r_setup <= i_setup;
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
                        baud_counter <= clocks_per_baud-28'h01;// Set, not reset
                        if ((ck_uart)&&(chg_counter >= break_condition))
                                // Goto idle state from a reset
                                state <= `RXU_IDLE;
                        else // Otherwise, stay in this condition 'til reset
                                state <= `RXU_RESET_IDLE;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                end else if ((~ck_uart)&&(chg_counter >= break_condition))
                begin // We are in a break condition
                        state <= `RXU_BREAK;
                        o_wr <= 1'b0;
                        o_data <= 8'h00;
                        baud_counter <= clocks_per_baud-28'h01;// Set, not reset
                        data_reg <= 8'h00;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                        r_setup <= i_setup;
                end else if (state == `RXU_BREAK)
                begin // Goto idle state following return ck_uart going high
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
                        baud_counter <= clocks_per_baud - 28'h01;
                        if (ck_uart)
                                state <= `RXU_IDLE;
                        else
                                state <= `RXU_BREAK;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                        r_setup <= i_setup;
                end else if (state == `RXU_IDLE)
                begin // Idle state, independent of baud counter
                        data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
                        baud_counter <= clocks_per_baud - 28'h01;
                        if ((ck_uart == 1'b0)&&(chg_counter > half_baud))
                        begin
                                // We are in the center of a valid start bit
                                case (data_bits)
                                2'b00: state <= `RXU_BIT_ZERO;
                                2'b01: state <= `RXU_BIT_ONE;
                                2'b10: state <= `RXU_BIT_TWO;
                                2'b11: state <= `RXU_BIT_THREE;
                                endcase
                        end else // Otherwise, just stay here in idle
                                state <= `RXU_IDLE;
                        calc_parity <= 1'b0;
                        o_parity_err <= 1'b0;
                        o_frame_err <= 1'b0;
                end else if (baud_counter == 0)
                begin
                        baud_counter <= clocks_per_baud-28'h1;
                        if (state < `RXU_BIT_SEVEN)
                        begin
                                // Data arrives least significant bit first.
                                // By the time this is clocked in, it's what
                                // you'll have.
                                data_reg <= { ck_uart, data_reg[7:1] };
                                calc_parity <= calc_parity ^ ck_uart;
                                o_data <= 8'h00;
                                o_wr <= 1'b0;
                                state <= state + 1;
                                o_parity_err <= 1'b0;
                                o_frame_err <= 1'b0;
                        end else if (state == `RXU_BIT_SEVEN)
                        begin
                                data_reg <= { ck_uart, data_reg[7:1] };
                                calc_parity <= calc_parity ^ ck_uart;
                                o_data <= 8'h00;
                                o_wr <= 1'b0;
                                state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
                                o_parity_err <= 1'b0;
                                o_frame_err <= 1'b0;
                        end else if (state == `RXU_PARITY)
                        begin
                                if (fixd_parity)
                                        o_parity_err <= (ck_uart ^ parity_even);
                                else
                                        o_parity_err <= ((parity_even && (calc_parity != ck_uart))
                                                ||((~parity_even)&&(calc_parity==ck_uart)));
                                state <= `RXU_STOP;
                                o_frame_err <= 1'b0;
                        end else if (state == `RXU_STOP)
                        begin // Stop (or parity) bit(s)
                                case (data_bits)
                                2'b00: o_data <= data_reg;
                                2'b01: o_data <= { 1'b0, data_reg[7:1] };
                                2'b10: o_data <= { 2'b0, data_reg[7:2] };
                                2'b11: o_data <= { 3'b0, data_reg[7:3] };
                                endcase
                                o_wr <= 1'b1; // Pulse the write
                                o_frame_err <= (~ck_uart);
                                if (~ck_uart)
                                        state <= `RXU_RESET_IDLE;
                                else if (dblstop)
                                        state <= `RXU_SECOND_STOP;
                                else
                                        state <= `RXU_IDLE;
                                // o_parity_err <= 1'b0;
                        end else // state must equal RX_SECOND_STOP
                        begin
                                if (~ck_uart)
                                begin
                                        o_frame_err <= 1'b1;
                                        state <= `RXU_RESET_IDLE;
                                end else begin
                                        state <= `RXU_IDLE;
                                        o_frame_err  <= 1'b0;
                                end
                                o_parity_err <= 1'b0;
                        end
                end else begin
                        o_wr <= 1'b0;   // data_reg = data_reg
                        baud_counter <= baud_counter - 1;
                        o_parity_err <= 1'b0;
                        o_frame_err  <= 1'b0;
                end
        end
 
endmodule
 
 

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[/] [xulalx25soc/] [trunk/] [rtl/] [rxuart.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dgisselq	`/////////////////////////////////////////////////////////////////////////`
2			`//`
3			`//`
4			`// Filename: rxuart.v`
5			`//`
6			`// Project: FPGA library development (Spartan 3E development board)`
7			`//`
8			`// Purpose: Receive and decode inputs from a single UART line.`
9			`//`
10			`//`
11			`// To interface with this module, connect it to your system clock,`
12			`// pass it the 32 bit setup register (defined below) and the UART`
13			`// input. When data becomes available, the o_wr line will be asserted`
14			`// for one clock cycle. On parity or frame errors, the o_parity_err`
15			`// or o_frame_err lines will be asserted. Likewise, on a break`
16			`// condition, o_break will be asserted. These lines are self clearing.`
17			`//`
18			`// There is a synchronous reset line, logic high.`
19			`//`
20			`// Now for the setup register. The register is 32 bits, so that this`
21			`// UART may be set up over a 32-bit bus.`
22			`//`
23			`// i_setup[29:28] Indicates the number of data bits per word. This will`
24			`// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10`
25			`// for a six bit word, or 2'b11 for a five bit word.`
26			`//`
27			`// i_setup[27] Indicates whether or not to use one or two stop bits.`
28			`// Set this to one to expect two stop bits, zero for one.`
29			`//`
30			`// i_setup[26] Indicates whether or not a parity bit exists. Set this`
31			`// to 1'b1 to include parity.`
32			`//`
33			`// i_setup[25] Indicates whether or not the parity bit is fixed. Set`
34			`// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the`
35			`// parity to be set based upon data. (Both assume the parity`
36			`// enable value is set.)`
37			`//`
38			`// i_setup[24] This bit is ignored if parity is not used. Otherwise,`
39			`// in the case of a fixed parity bit, this bit indicates whether`
40			`// mark (1'b1) or space (1'b0) parity is used. Likewise if the`
41			`// parity is not fixed, a 1'b1 selects even parity, and 1'b0`
42			`// selects odd.`
43			`//`
44			`// i_setup[23:0] Indicates the speed of the UART in terms of clocks.`
45			`// So, for example, if you have a 200 MHz clock and wish to`
46			`// run your UART at 9600 baud, you would take 200 MHz and divide`
47			`// by 9600 to set this value to 24'd20834. Likewise if you wished`
48			`// to run this serial port at 115200 baud from a 200 MHz clock,`
49			`// you would set the value to 24'd1736`
50			`//`
51			`// Thus, to set the UART for the common setting of an 8-bit word,`
52			`// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you`
53			`// would want to set the setup value to:`
54			`//`
55			`// 32'h0006c8 // For 115,200 baud, 8 bit, no parity`
56			`// 32'h005161 // For 9600 baud, 8 bit, no parity`
57			`//`
58			`// Creator: Dan Gisselquist`
59			`// Gisselquist Technology, LLC`
60			`//`
61			`// Copyright: 2015`
62			`//`
63			`//`
64			`/////////////////////////////////////////////////////////////////////////`
65			`//`
66			`// This software is the ownership of Gisselquist Technology, LLC, and as`
67			`// such it is proprietary. It is provided without any warrantees, either`
68			`// express or implied, so that it may be tested. Upon completion, I ask`
69			`// that working code be returned and not further distributed beyond those`
70			`// that it is originally offered to.`
71			`//`
72			`// Thank you.`
73			`//`
74
75			`// States: (@ baud counter == 0)`
76			`// 0 First bit arrives`
77			`// ..7 Bits arrive`
78			`// 8 Stop bit (x1)`
79			`// 9 Stop bit (x2)`
80			`/// c break condition`
81			`// d Waiting for the channel to go high`
82			`// e Waiting for the reset to complete`
83			`// f Idle state`
84			`define RXU_BIT_ZERO 4'h0
85			`define RXU_BIT_ONE 4'h1
86			`define RXU_BIT_TWO 4'h2
87			`define RXU_BIT_THREE 4'h3
88			`define RXU_BIT_FOUR 4'h4
89			`define RXU_BIT_FIVE 4'h5
90			`define RXU_BIT_SIX 4'h6
91			`define RXU_BIT_SEVEN 4'h7
92			`define RXU_PARITY 4'h8
93			`define RXU_STOP 4'h9
94			`define RXU_SECOND_STOP 4'ha
95			`// Unused 4'hb`
96			`// Unused 4'hc`
97			`define RXU_BREAK 4'hd
98			`define RXU_RESET_IDLE 4'he
99			`define RXU_IDLE 4'hf
100
101			`module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,`
102			`o_parity_err, o_frame_err, o_ck_uart);`
103			`// parameter // CLOCKS_PER_BAUD = 25'd004340,`
104			`// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,`
105			`// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;`
106			`// 8 data bits, no parity, (at least 1) stop bit`
107			`input i_clk, i_reset;`
108			`input [29:0] i_setup;`
109			`input i_uart;`
110			`output reg o_wr;`
111			`output reg [7:0] o_data;`
112			`output reg o_break;`
113			`output reg o_parity_err, o_frame_err;`
114			`output wire o_ck_uart;`
115
116
117			`wire [27:0] clocks_per_baud, break_condition, half_baud;`
118			`wire [1:0] data_bits;`
119			`wire use_parity, parity_even, dblstop, fixd_parity;`
120			`reg [29:0] r_setup;`
121			`assign clocks_per_baud = { 4'h0, r_setup[23:0] };`
122			`assign data_bits = r_setup[29:28];`
123			`assign dblstop = r_setup[27];`
124			`assign use_parity = r_setup[26];`
125			`assign fixd_parity = r_setup[25];`
126			`assign parity_even = r_setup[24];`
127			`assign break_condition = { r_setup[23:0], 4'h0 };`
128			`assign half_baud = { 5'h00, r_setup[23:1] };`
129
130			`reg q_uart, qq_uart, ck_uart;`
131			`initial q_uart = 1'b0;`
132			`initial qq_uart = 1'b0;`
133			`initial ck_uart = 1'b0;`
134			`always @(posedge i_clk)`
135			`begin`
136			`q_uart <= i_uart;`
137			`qq_uart <= q_uart;`
138			`ck_uart <= qq_uart;`
139			`end`
140			`assign o_ck_uart = ck_uart;`
141
142			`reg [27:0] chg_counter;`
143			`initial chg_counter = 28'h00;`
144			`always @(posedge i_clk)`
145			`if (i_reset)`
146			`chg_counter <= 28'h00;`
147			`else if (qq_uart != ck_uart)`
148			`chg_counter <= 28'h00;`
149			`else if (chg_counter < break_condition)`
150			`chg_counter <= chg_counter + 1;`
151
152			`always @(posedge i_clk)`
153			`o_break <=((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;`
154
155			`reg [3:0] state;`
156			`reg [27:0] baud_counter;`
157			`reg [7:0] data_reg;`
158			`reg calc_parity;`
159			`initial o_wr = 1'b0;`
160			initial state = `RXU_RESET_IDLE;
161			`initial o_parity_err = 1'b0;`
162			`initial o_frame_err = 1'b0;`
163			`// initial baud_counter = clocks_per_baud;`
164			`always @(posedge i_clk)`
165			`begin`
166			`if (i_reset)`
167			`begin`
168			`o_wr <= 1'b0;`
169			`o_data <= 8'h00;`
170			state <= `RXU_RESET_IDLE;
171			`baud_counter <= clocks_per_baud; // Set, not reset`
172			`data_reg <= 8'h00;`
173			`calc_parity <= 1'b0;`
174			`o_parity_err <= 1'b0;`
175			`o_frame_err <= 1'b0;`
176			end else if (state == `RXU_RESET_IDLE)
177			`begin`
178			`r_setup <= i_setup;`
179			`data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;`
180			`baud_counter <= clocks_per_baud-28'h01;// Set, not reset`
181			`if ((ck_uart)&&(chg_counter >= break_condition))`
182			`// Goto idle state from a reset`
183			state <= `RXU_IDLE;
184			`else // Otherwise, stay in this condition 'til reset`
185			state <= `RXU_RESET_IDLE;
186			`calc_parity <= 1'b0;`
187			`o_parity_err <= 1'b0;`
188			`o_frame_err <= 1'b0;`
189			`end else if ((~ck_uart)&&(chg_counter >= break_condition))`
190			`begin // We are in a break condition`
191			state <= `RXU_BREAK;
192			`o_wr <= 1'b0;`
193			`o_data <= 8'h00;`
194			`baud_counter <= clocks_per_baud-28'h01;// Set, not reset`
195			`data_reg <= 8'h00;`
196			`calc_parity <= 1'b0;`
197			`o_parity_err <= 1'b0;`
198			`o_frame_err <= 1'b0;`
199			`r_setup <= i_setup;`
200			end else if (state == `RXU_BREAK)
201			`begin // Goto idle state following return ck_uart going high`
202			`data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;`
203			`baud_counter <= clocks_per_baud - 28'h01;`
204			`if (ck_uart)`
205			state <= `RXU_IDLE;
206			`else`
207			state <= `RXU_BREAK;
208			`calc_parity <= 1'b0;`
209			`o_parity_err <= 1'b0;`
210			`o_frame_err <= 1'b0;`
211			`r_setup <= i_setup;`
212			end else if (state == `RXU_IDLE)
213			`begin // Idle state, independent of baud counter`
214			`data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;`
215			`baud_counter <= clocks_per_baud - 28'h01;`
216			`if ((ck_uart == 1'b0)&&(chg_counter > half_baud))`
217			`begin`
218			`// We are in the center of a valid start bit`
219			`case (data_bits)`
220			2'b00: state <= `RXU_BIT_ZERO;
221			2'b01: state <= `RXU_BIT_ONE;
222			2'b10: state <= `RXU_BIT_TWO;
223			2'b11: state <= `RXU_BIT_THREE;
224			`endcase`
225			`end else // Otherwise, just stay here in idle`
226			state <= `RXU_IDLE;
227			`calc_parity <= 1'b0;`
228			`o_parity_err <= 1'b0;`
229			`o_frame_err <= 1'b0;`
230			`end else if (baud_counter == 0)`
231			`begin`
232			`baud_counter <= clocks_per_baud-28'h1;`
233			if (state < `RXU_BIT_SEVEN)
234			`begin`
235			`// Data arrives least significant bit first.`
236			`// By the time this is clocked in, it's what`
237			`// you'll have.`
238			`data_reg <= { ck_uart, data_reg[7:1] };`
239			`calc_parity <= calc_parity ^ ck_uart;`
240			`o_data <= 8'h00;`
241			`o_wr <= 1'b0;`
242			`state <= state + 1;`
243			`o_parity_err <= 1'b0;`
244			`o_frame_err <= 1'b0;`
245			end else if (state == `RXU_BIT_SEVEN)
246			`begin`
247			`data_reg <= { ck_uart, data_reg[7:1] };`
248			`calc_parity <= calc_parity ^ ck_uart;`
249			`o_data <= 8'h00;`
250			`o_wr <= 1'b0;`
251			state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
252			`o_parity_err <= 1'b0;`
253			`o_frame_err <= 1'b0;`
254			end else if (state == `RXU_PARITY)
255			`begin`
256			`if (fixd_parity)`
257			`o_parity_err <= (ck_uart ^ parity_even);`
258			`else`
259			`o_parity_err <= ((parity_even && (calc_parity != ck_uart))`
260			`\|\|((~parity_even)&&(calc_parity==ck_uart)));`
261			state <= `RXU_STOP;
262			`o_frame_err <= 1'b0;`
263			end else if (state == `RXU_STOP)
264			`begin // Stop (or parity) bit(s)`
265			`case (data_bits)`
266			`2'b00: o_data <= data_reg;`
267			`2'b01: o_data <= { 1'b0, data_reg[7:1] };`
268			`2'b10: o_data <= { 2'b0, data_reg[7:2] };`
269			`2'b11: o_data <= { 3'b0, data_reg[7:3] };`
270			`endcase`
271			`o_wr <= 1'b1; // Pulse the write`
272			`o_frame_err <= (~ck_uart);`
273			`if (~ck_uart)`
274			state <= `RXU_RESET_IDLE;
275			`else if (dblstop)`
276			state <= `RXU_SECOND_STOP;
277			`else`
278			state <= `RXU_IDLE;
279			`// o_parity_err <= 1'b0;`
280			`end else // state must equal RX_SECOND_STOP`
281			`begin`
282			`if (~ck_uart)`
283			`begin`
284			`o_frame_err <= 1'b1;`
285			state <= `RXU_RESET_IDLE;
286			`end else begin`
287			state <= `RXU_IDLE;
288			`o_frame_err <= 1'b0;`
289			`end`
290			`o_parity_err <= 1'b0;`
291			`end`
292			`end else begin`
293			`o_wr <= 1'b0; // data_reg = data_reg`
294			`baud_counter <= baud_counter - 1;`
295			`o_parity_err <= 1'b0;`
296			`o_frame_err <= 1'b0;`
297			`end`
298			`end`
299
300			`endmodule`
301
302