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[/] [xulalx25soc/] [trunk/] [rtl/] [spiarbiter.v] - Blame information for rev 86

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    spiarbiter.v
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//
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// Project:     XuLA2 board
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//
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// Purpose:     The XuLA2 offers SPI access to both a FLASH and an SD Card.
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//              This simple script arbitrates between the two of those to
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//      determine who has access.  Drivers for both chips may interact with
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//      this arbiter as though it were a SPI device with one additional piece
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//      of functionality: the clock line may not be brought low until access
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//      has been granted to the chip.  Thus, the controller wishing to access
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//      its device should pull the CS line low, and then wait to read that
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//      its grant line is high.  Once CS is low and grant is high, it may
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//      then bring CK low and start its transaction.
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//
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//      When two or more controllers request access at the same time,
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//      access will be given in priority order.  Further, access is always
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//      granted to device 'A' without request as long as device 'B' isn't
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//      busy.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module  spiarbiter(i_clk,
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                i_cs_a_n, i_ck_a, i_mosi_a,
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                i_cs_b_n, i_ck_b, i_mosi_b,
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                o_cs_a_n, o_cs_b_n, o_ck, o_mosi,
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                o_grant);
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        input           i_clk;
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        input           i_cs_a_n, i_ck_a, i_mosi_a;
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        // output       wire    o_grant_a;
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        input           i_cs_b_n, i_ck_b, i_mosi_b;
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        // output       wire    o_grant_b;
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        output  wire    o_cs_a_n, o_cs_b_n, o_ck, o_mosi;
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        //
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        output  wire    o_grant; // == o_grant_a = ~o_grant_b
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        reg     a_owner;
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        initial a_owner = 1'b1;
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        always @(posedge i_clk)
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                if ((i_cs_a_n)&&(i_cs_b_n))
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                        a_owner <= 1'b1; // Keep control
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                else if ((i_cs_a_n)&&(~i_cs_b_n))
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                        a_owner <= 1'b0; // Give up control
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                else if ((~i_cs_a_n)&&(i_cs_b_n))
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                        a_owner <= 1'b1; // Take control
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        // assign       o_grant_a = a_owner;
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        // assign       o_grant_b = (~a_owner);
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        assign  o_cs_a_n = (~a_owner)||(i_cs_a_n);
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        assign  o_cs_b_n = ( a_owner)||(i_cs_b_n);
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        assign  o_ck     = ( a_owner)?i_ck_a   : i_ck_b;
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        assign  o_mosi   = ( a_owner)?i_mosi_a : i_mosi_b;
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        assign  o_grant = ~a_owner;
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endmodule
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