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[/] [xulalx25soc/] [trunk/] [rtl/] [toplevel.v] - Blame information for rev 2

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1 2 dgisselq
`timescale 10ns / 100ps
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///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    toplevel.v
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//
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// Project:     XuLA2 board
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//
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// Purpose:     This is the _top_level_ verilog file for the XuLA2-LX25
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//              SoC project.  Everything else fits underneath here (logically).
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//      This is also the only file that will not go through Verilator.  Specific
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//      to this file are the Xilinx primitives necessary to build for the
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//      XuLA2 board--with the only exception being the ICAPE_SPARTAN6 interface.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// `define      HELLO_WORLD
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// `define      ECHO_TEST
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//
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module toplevel(i_clk_12mhz,
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                i_ram_feedback_clk,
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                o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
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                o_ram_clk, o_ram_cke, o_ram_cs_n, o_ram_ras_n, o_ram_cas_n,
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                o_ram_we_n, o_ram_bs, o_ram_addr, o_ram_udqm, o_ram_ldqm,
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                io_ram_data,
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                i_gpio, o_gpio, o_pwm, i_rx_uart, o_tx_uart);
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        input           i_clk_12mhz;
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        input           i_ram_feedback_clk;
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        //
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        // SPI connection(s): Flash and SD Card
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        output  wire    o_sf_cs_n;
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        output  wire    o_sd_cs_n;
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        output  wire    o_spi_sck;
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        output  wire    o_spi_mosi;
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        input           i_spi_miso;
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        //
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        // SD RAM
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        output  wire    o_ram_clk, o_ram_cke;
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        output  wire    o_ram_cs_n, o_ram_ras_n, o_ram_cas_n, o_ram_we_n;
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        output  wire    [1:0]    o_ram_bs;
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        output  wire    [12:0]   o_ram_addr;
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        output  wire            o_ram_udqm, o_ram_ldqm;
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        inout   wire    [15:0]   io_ram_data;
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        //
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        // General purpose I/O
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        // output       [31:0]  io_chan;
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        input           [13:0]   i_gpio;
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        output  wire    [14:0]   o_gpio;
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        output  wire            o_pwm;
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        input                   i_rx_uart;
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        output  wire            o_tx_uart;
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/////
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        wire    [7:0]    rx_data, tx_data;
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        wire            rx_stb, tx_stb, tx_busy;
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        wire            clk_s, reset_s, intermediate_clk, intermediate_clk_n,
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                        ck_zero_0;
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        wire    ck_zero_1;
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        DCM_SP #(
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                .CLKDV_DIVIDE(2.0),
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                .CLKFX_DIVIDE(3),
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                .CLKFX_MULTIPLY(20),
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                .CLKIN_DIVIDE_BY_2("FALSE"),
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                .CLKIN_PERIOD(83.333333),
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                .CLKOUT_PHASE_SHIFT("NONE"),
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                .CLK_FEEDBACK("1X"),
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                .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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                .DLL_FREQUENCY_MODE("LOW"),
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                .DUTY_CYCLE_CORRECTION("TRUE"),
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                .PHASE_SHIFT(0),
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                .STARTUP_WAIT("TRUE")
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        ) u0(   .CLKIN(i_clk_12mhz),
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                .CLK0(ck_zero_0),
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                .CLKFB(ck_zero_0),
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                .CLKFX(clk_s),
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                // .CLKFX180(intermediate_clk_n),
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                .PSEN(1'b0),
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                .RST(1'b0));
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        DCM_SP #(
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                .CLKDV_DIVIDE(2),
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                .CLKFX_MULTIPLY(2),
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                .CLKFX_DIVIDE(2),
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                .CLKOUT_PHASE_SHIFT("FIXED"),
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                .CLK_FEEDBACK("1X"),
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                .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
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                .DLL_FREQUENCY_MODE("LOW"),
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                .DUTY_CYCLE_CORRECTION("TRUE"),
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                // At a clock of 92MHz ...
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                // Didn't work at -64, -70, -76 is worse than the other two
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                // -56: Write works, 0x96 reads work 
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                // -48: Write fails, 0x0183 or 0x351 is first write that fails
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                // -40: Write fails, 0x071a,176a,0x576
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                // -56 was my working choice at 92 MHz
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                //      That would be about a 2.4ns delay from clock to 
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                //      data.
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                // Suddenly needed to shift to 80 MHz. 
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                //      -56 no longer sort of works
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                //      -49 writes seem to work, reads ... not so much
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                //      -45 writes no longer working ??
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                //              Read fails @ 0x891, 0x58e, @0x3d65, @0x0aec,
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                //                      @0x11b8, @0beb, @0x01014
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                // Trying a different approach: register in i_ram_feedback_clk,
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                //      followed by o_ram_clk, instead of registering on
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                //      clk_s second.  Starting build at 1857
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                //      Okay, so that was an error, now they are referenced to
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                //      intermediate_clk, and I still need to try
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                //      intermediate_clk_n if that doesn't work.
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                //      THIS NEEDS A DELAY ADJUSTMENT: WBSDRAMNG adjusted from
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                //      6 to 5, and rebuild started at 1914. (finished by 1930)
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                //      This one has read bugs at 0x027, 0x030, 0x039, 0x021
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                //              etc.  So we are worse. 
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                //      (We also failed timing--I did nothing to fix that)
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                //
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                // tho ... even if this works, it is wrong.  The data lines
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                // going into wbsdramng need to be clocked on the system clock
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                // on entrance.  Thus, the last always@ block must clock these
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                // lines on clk_s.  This is fixed, and cannot change.
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                // This leaves us with a couple options for clocking the first
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                // always block:
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                //
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                //      i_ram_feedback_clk, posedge (the right answer ... but
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                //              giving me problems)
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                //      clk_s   pos/neg edge
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                //      intermediate_clk        posedge (Build started at 1932)
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                //              Result: much worse!!
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                //      intermediate_clk_n      posedge (delay of 6 needed, not
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                //              tested as a result.
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                //
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                //      
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                .PHASE_SHIFT(-45),
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                .STARTUP_WAIT("TRUE")
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        ) u1(   .CLKIN(clk_s),
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                .CLK0(ck_zero_1),
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                .CLKFB(ck_zero_1),
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                .CLK180(intermediate_clk_n),
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                .PSEN(1'b0),
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                .RST(1'b0));
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        assign  intermediate_clk = ck_zero_1;
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        ODDR2 u2( .Q(o_ram_clk),
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                .C0(intermediate_clk),
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                .C1(intermediate_clk_n),
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                .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
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        // Generate active-high reset.
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        /*
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        reg     r_reset;
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        initial r_reset = 1'b1;
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        always @(posedge i_clk_12mhz)
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                r_reset <= 1'b0;
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        */
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        assign  reset_s = 1'b0;
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        jtagser jtagtxrx(clk_s, rx_stb, rx_data, tx_stb, tx_data, tx_busy);
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        wire    [15:0]   ram_data;
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        wire            ram_drive_data;
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        reg     [15:0]   r_ram_data;
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        busmaster #(24,15,14)
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                wbbus(clk_s, reset_s,
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                        // External JTAG bus control
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                        rx_stb, rx_data, tx_stb, tx_data, tx_busy,
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                        // Board lights and switches ... none
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                        // SPI/SD-card flash
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                        o_sf_cs_n, o_sd_cs_n, o_spi_sck, o_spi_mosi, i_spi_miso,
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                        // SDRAM interface
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                        // o_ram_clk,   // SDRAM clock = clk_100mhz_s = clk_s
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                        o_ram_cs_n,     // Chip select
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                        o_ram_cke,      // Clock enable
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                        o_ram_ras_n,    // Row address strobe
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                        o_ram_cas_n,    // Column address strobe
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                        o_ram_we_n,     // Write enable
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                        o_ram_bs,       // Bank select
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                        o_ram_addr,     // Address lines
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                        ram_drive_data,
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                        r_ram_data,     // Data lines (input)
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                        ram_data,       // Data lines (output)
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                        { o_ram_udqm, o_ram_ldqm },
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                        // GPIO
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                        i_gpio, o_gpio, o_pwm, i_rx_uart, o_tx_uart
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                );
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        assign io_ram_data = (ram_drive_data) ? ram_data : 16'bzzzz_zzzz_zzzz_zzzz;
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        reg     [15:0]   r_ram_data_ext_clk;
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        // always @(posedge intermediate_clk_n)
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        always @(posedge clk_s)
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                r_ram_data_ext_clk <= io_ram_data;
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        always @(posedge clk_s)
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                r_ram_data <= r_ram_data_ext_clk;
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endmodule

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