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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: uartdev.v
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//
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// Project: XuLA2 board
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//
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module uartdev(i_clk, i_rx_uart, o_tx_uart,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_rx_int, o_tx_int);
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parameter DEFAULT_SETUP = { 2'b00, 1'b0, 1'b0, 2'b00, 24'd10417 };
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input i_clk, i_rx_uart;
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output wire o_tx_uart;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [1:0] i_wb_addr;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output wire o_rx_int, o_tx_int;
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reg [29:0] r_setup;
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reg r_tx_stb, rx_rdy;
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reg [7:0] r_tx_data;
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initial r_setup = DEFAULT_SETUP;
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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begin
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case(i_wb_addr)
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2'b00: r_setup <= i_wb_data[29:0];
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2'b10: begin
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r_tx_data <= i_wb_data[7:0];
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r_tx_stb <= 1'b1;
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end
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default: begin end
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endcase
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end else
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r_tx_stb <= 1'b0;
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wire rx_stb, rx_break, rx_parity_err, rx_frame_err, rx_ignored;
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wire [7:0] rx_data;
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rxuart rxmod(i_clk, 1'b0, r_setup, i_rx_uart,
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rx_stb, rx_data, rx_break,
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rx_parity_err, rx_frame_err, rx_ignored);
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wire tx_break, tx_busy;
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assign tx_break = 1'b0;
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txuart txmod(i_clk, 1'b0, r_setup, tx_break, r_tx_stb, r_tx_data,
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o_tx_uart, tx_busy);
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reg [7:0] r_data;
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always @(posedge i_clk)
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if (rx_stb)
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r_data <= rx_data;
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always @(posedge i_clk)
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begin
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if (rx_stb)
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rx_rdy <= (rx_rdy | rx_stb);
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case(i_wb_addr)
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2'b00: o_wb_data <= { 2'b00, r_setup };
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2'b01: o_wb_data <= { 2'b00, r_setup };
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2'b10: o_wb_data <= { 31'h00,tx_busy };
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2'b11: begin
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
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rx_rdy <= 1'b0;
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o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
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end
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endcase
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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end
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assign o_wb_stall = 1'b0;
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assign o_rx_int = rx_stb;
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assign o_tx_int = ~tx_busy;
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endmodule
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