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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbicape6.v
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//
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// Project: Wishbone to ICAPE_SPARTAN6 interface conversion
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//
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// Purpose: This is a companion project to the ICAPE2 conversion, instead
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// involving a conversion from a 32-bit WISHBONE bus to read
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// and write the ICAPE_SPARTAN6 program. This is the 'non-simple'
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// portion of the interface, sporting all of the smarts necessary to run
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// the simple interface and make working with ICAPE as simple as
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// reading and writing from a wishbone bus. For example, register ID's
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// are given by bus addresses, even though they take extra cycles to
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// set and clear within the interface.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Following instructions on page 116-117 of the configuration guide ...
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//
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// W FFFF
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// W FFFF
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// W AA99
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// W 5566
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// W 2000 NOOP
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// W 2901 Write Type-1 packet header to read register 901??
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// W 2000 NOOP
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// W 2000 NOOP
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// W 2000 NOOP
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// W 2000 NOOP
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// R vvvv Read register from previous packet header command
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// W 30A1 Write word to CMD register
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// W 000D DESYNC command
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// W 2000 NOOP
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// W 2000 NOOP
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//
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// Bits need to be bit-reversed within a byte
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//
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//
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// IPROG example
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//
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// W FFFF
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// W AA99
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// W 5566
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// W 3261 Write 1 words to GENERAL_1
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// W xxxx write Multiboot start address [15:0]
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// W 3281 Write 1 words to GENERAL_2
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// W xxxx write Opcode and multiboot start address [23:16]
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// W 32A1 Write 1 words to GENERAL_3
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// W xxxx write Fallback start address
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// W 32C1 Write 1 words to GENERAL_4
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// W xxxx write Opcode dne Fallback start address [23:16]
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// W 30A1 Write 1 word to CMD
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// W 000E IPGROG Cmd
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// W 2000 NOOP
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//
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//
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//
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// This fails when using wgregs on the XuLA2 board because the ICAPE port and
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// the JTAG port cannot both be active at the same time.
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//
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//
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`define ICAP_IDLE 5'h0
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`define ICAP_START 5'h1
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`define ICAP_CLOSE 5'hf
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module wbicape6(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data, dbg_data);
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input i_clk;
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// Wishbone slave inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [5:0] i_wb_addr;
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input [31:0] i_wb_data;
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_stall;
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output wire [31:0] o_wb_data;
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output wire [31:0] dbg_data;
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// Interface to the lower level ICAPE port
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reg icap_cyc, icap_stb, icap_we;
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reg [15:0] icap_data_i;
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wire icap_ack, icap_stall;
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wire [15:0] icap_data_o;
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reg [4:0] state;
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reg r_we;
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reg [15:0] r_data;
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wire [25:0] icap_dbg;
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assign dbg_data = { i_wb_stb, state[3:0], r_we, icap_dbg };
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reg stalled_state;
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reg [7:0] r_cmd_word;
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wire [15:0] w_cmd_word;
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assign w_cmd_word = { 3'b001, r_cmd_word, 5'h00 }; // Type-1 packet hdr
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initial icap_stb = 1'b0;
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initial icap_cyc = 1'b0;
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initial state = `ICAP_IDLE;
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always @(posedge i_clk)
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begin
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b0;
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if (stalled_state)
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state <= `ICAP_IDLE;
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else if ((~icap_stall)&&(state != `ICAP_IDLE))
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state <= state + 1;
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case(state)
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`ICAP_IDLE: begin
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icap_stb <= 1'b0;
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icap_cyc <= 1'b0;
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state <= `ICAP_IDLE;
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r_data <= i_wb_data[15:0];
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r_we <= i_wb_we;
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if ((i_wb_cyc)&&(i_wb_stb))
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begin
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state <= `ICAP_START;
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icap_stb <= i_wb_stb;
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icap_cyc <= i_wb_cyc;
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icap_we <= 1'b1;
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icap_data_i <= 16'hffff;
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r_cmd_word <= { (i_wb_we)? 2'b10:2'b01, i_wb_addr };
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o_wb_stall <= 1'b1;
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end end
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`ICAP_START: begin
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if (~icap_stall)
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icap_data_i <= 16'hffff;
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end
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5'h2: begin
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if (~icap_stall)
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icap_data_i <= 16'haa99;
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end
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5'h3: begin
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if (~icap_stall)
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icap_data_i <= 16'h5566;
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end
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5'h4: begin
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if (~icap_stall)
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icap_data_i <= 16'h2000;
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end
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5'h5: begin
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if (~icap_stall)
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begin
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icap_data_i <= w_cmd_word; // Includes address
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end end
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5'h6: begin // Write
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if (~icap_stall)
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begin
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if (r_we)
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icap_data_i <= r_data;
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else
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icap_data_i <= 16'h2000;
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end end
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5'h7: begin
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// Need to send four NOOPs before we can begin
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// reading. Send the four NOOPs for a write anyway.
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if (~icap_stall)
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icap_data_i <= 16'h2000;
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end
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5'h8: begin
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if (~icap_stall)
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icap_data_i <= 16'h2000;
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end
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5'h9: begin
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if (~icap_stall)
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begin
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icap_data_i <= 16'h2000;
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if (r_we)
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state <= `ICAP_CLOSE;
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end end
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5'ha: begin
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if (~icap_stall)
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begin
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// We now request the chip enable line be
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// dropped, so we can switch from writing to
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// reading
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icap_data_i <= 16'h2000;
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icap_stb <= 1'b0;
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icap_cyc <= 1'b0;
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end end
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5'hb: begin
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if (~icap_stall)
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begin
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// Switch the write line to read, must be done
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// w/the chip enable off (hence _cyc=0). O/w
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// the interface will abort.
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icap_data_i <= 16'h2000;
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icap_we <=1'b0;
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end end
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5'hc: begin
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if (~icap_stall)
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begin
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// We can finally issue our read command
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// Re-activate the interface, and read
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icap_data_i <= 16'h2000;
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icap_stb <= 1'b1;
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icap_cyc <= 1'b1;
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end end
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5'hd: begin
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if (~icap_stall)
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begin
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// De-activate the interface again so we can
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// switch back to write.
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icap_data_i <= 16'h2000;
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icap_stb <= 1'b0;
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icap_cyc <= 1'b0;
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end end
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5'he: begin
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if (~icap_stall)
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begin
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// Switch back to write while the interface
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// is deactivated.
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icap_we <= 1'b1;
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icap_data_i <= 16'h2000;
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end end
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`ICAP_CLOSE: begin
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if (~icap_stall)
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begin
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icap_we <= 1'b1;
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// Type 1: Write 1 word to CMD register
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icap_data_i <= 16'h30a1;
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r_data <= icap_data_o;
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icap_stb <= 1'b1;
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icap_cyc <= 1'b1;
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end end
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5'h10: begin // DESYNC Command
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if (~icap_stall)
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begin
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icap_data_i <= 16'h000d;
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end end
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5'h11: begin // DESYNC must be followed by two NOOPs
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if (~icap_stall)
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begin
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icap_data_i <= 16'h2000;
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end end
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5'h12: begin // NOOP
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if (~icap_stall)
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begin
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icap_data_i <= 16'h2000;
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state <= `ICAP_IDLE;
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o_wb_ack <= 1'b1;
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o_wb_stall <= 1'b0;
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end end
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default: begin
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// If we were in the middle of a bus cycle, and got
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// here then ... we just failed that cycle. Setting
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// the bus error flag would be appropriate, but we
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// have no such flag to our interface. Hence we just
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// drop things and depend upon a bus watchdog to
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// catch that we aren't answering.
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o_wb_ack <= 1'b0;
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o_wb_stall <= 1'b0;
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icap_stb <= 1'b0;
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icap_cyc <= 1'b0;
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state <= `ICAP_IDLE;
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end
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endcase
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end
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wbicapesimple spartancfg(i_clk, icap_cyc, icap_stb, icap_we,
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icap_data_i,
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icap_ack, icap_stall, icap_data_o,
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icap_dbg);
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assign o_wb_data = { 16'h0000, r_data };
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reg [3:0] last_state;
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initial last_state = `ICAP_IDLE;
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always @(posedge i_clk)
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last_state <= state;
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reg [11:0] reset_ctr;
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always @(posedge i_clk)
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if (last_state != state)
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reset_ctr <= 0;
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else if (state == `ICAP_IDLE)
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reset_ctr <= 0;
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else
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reset_ctr <= reset_ctr + 1;
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always @(posedge i_clk)
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stalled_state <= (&reset_ctr);
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endmodule
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