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[/] [xulalx25soc/] [trunk/] [rtl/] [wbspiflash.v] - Blame information for rev 2

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    wbspiflash.v
4
//
5
// Project:     XuLA2 board
6
//
7
// Purpose:     Access a SPI flash via a WISHBONE interface.  This
8
//              includes both read and write (and erase) commands to the SPI
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//              flash.  All read/write commands are accomplished using the
10
//              high speed (4-bit) interface.  Further, the device will be
11
//              left/kept in the 4-bit read interface mode between accesses,
12
//              for a minimum read latency.
13
//
14
//      Wishbone Registers (See spec sheet for more detail):
15
//      0: local config(r) / erase commands(w) / deep power down cmds / etc.
16
//      R: (Write in Progress), (dirty-block), (spi_port_busy), 1'b0, 9'h00,
17
//              { last_erased_sector, 14'h00 } if (WIP)
18
//              else { current_sector_being_erased, 14'h00 }
19
//              current if write in progress, last if written
20
//      W: (1'b1 to erase), (12'h ignored), next_erased_block, 14'h ignored)
21
//      1: Configuration register
22
//      2: Status register (R/w)
23
//      3: Read ID (read only)
24
//      (19 bits): Data (R/w, but expect writes to take a while)
25
//              
26
//
27
// Creator:     Dan Gisselquist
28
//              Gisselquist Technology, LLC
29
//
30
///////////////////////////////////////////////////////////////////////////
31
//
32
// Copyright (C) 2015, Gisselquist Technology, LLC
33
//
34
// This program is free software (firmware): you can redistribute it and/or
35
// modify it under the terms of  the GNU General Public License as published
36
// by the Free Software Foundation, either version 3 of the License, or (at
37
// your option) any later version.
38
//
39
// This program is distributed in the hope that it will be useful, but WITHOUT
40
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
41
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
42
// for more details.
43
//
44
// You should have received a copy of the GNU General Public License along
45
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
46
// target there if the PDF file isn't present.)  If not, see
47
// <http://www.gnu.org/licenses/> for a copy.
48
//
49
// License:     GPL, v3, as defined and found on www.gnu.org,
50
//              http://www.gnu.org/licenses/gpl.html
51
//
52
//
53
///////////////////////////////////////////////////////////////////////////
54
`define WBSPI_RESET             6'd0
55
// `define      WBSPI_RESET_QUADMODE    1
56
`define WBSPI_IDLE              6'd2
57
// `define      WBQSPI_RDIDLE           3       // Idle, but in fast read mode
58
// `define      WBSPI_WBDECODE          4
59
`define WBSPI_WAIT_WIP_CLEAR    6'd5
60
`define WBSPI_CHECK_WIP_CLEAR   6'd6
61
`define WBSPI_CHECK_WIP_DONE    6'd7
62
`define WBSPI_WEN               6'd8
63
`define WBSPI_PP                6'd9    // Program page
64
// `define      WBSPI_QPP               10      // Program page, 4 bit mode
65
`define WBSPI_WR_DATA           6'd11
66
`define WBSPI_WR_BUS_CYCLE      6'd12
67
`define WBSPI_RD_DUMMY          6'd13
68
// `define      WBSPI_QRD_ADDRESS       14
69
// `define      WBSPI_QRD_DUMMY 15
70
`define WBSPI_READ_CMD          6'd16
71
`define WBSPI_READ_DATA         6'd17
72
//`define       WBSPI_WAIT_TIL_RDIDLE   18
73
`define WBSPI_READ_ID_CMD       6'd19
74
`define WBSPI_READ_ID           6'd20
75
`define WBSPI_READ_STATUS       6'd21
76
`define WBSPI_READ_CONFIG       6'd22
77
`define WBSPI_WRITE_STATUS      6'd23
78
`define WBSPI_WRITE_CONFIG      6'd24
79
`define WBSPI_ERASE_WEN         6'd25
80
`define WBSPI_ERASE_CMD         6'd26
81
`define WBSPI_ERASE_BLOCK       6'd27
82
`define WBSPI_CLEAR_STATUS      6'd28
83
`define WBSPI_IDLE_CHECK_WIP    6'd29
84
`define WBSPI_WAIT_TIL_IDLE     6'd30
85
//
86
module  wbspiflash(i_clk_100mhz,
87
                // Internal wishbone connections
88
                i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we,
89
                i_wb_addr, i_wb_data,
90
                // Wishbone return values
91
                o_wb_ack, o_wb_stall, o_wb_data,
92
                // Quad Spi connections to the external device
93
                o_spi_sck, o_spi_cs_n, i_spi_cs_n, o_spi_mosi, i_spi_miso,
94
                o_interrupt);
95
        parameter       AW=18, // Address width, -2 for 32-bit word access
96
                        PW=6,   // Page address width (256 bytes,64 words)
97
                        SW=10;  // Sector address width (4kB, 1kW)
98
        // parameter    AW, PW, Sw; // Address, page, and sector width(s)
99
        input                   i_clk_100mhz;
100
        // Wishbone, inputs first
101
        input                   i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb, i_wb_we;
102
        input   [(AW-1):0]       i_wb_addr;
103
        input           [31:0]   i_wb_data;
104
        // then outputs
105
        output  reg             o_wb_ack;
106
        output  reg             o_wb_stall;
107
        output  reg     [31:0]   o_wb_data;
108
        // Quad SPI control wires
109
        output  wire            o_spi_sck;
110
        output  wire            o_spi_cs_n;
111
        input                   i_spi_cs_n;
112
        output  wire            o_spi_mosi;
113
        input                   i_spi_miso;
114
        // Interrupt line
115
        output  reg             o_interrupt;
116
        // output       wire    [31:0]  o_debug;
117
 
118
        reg             spi_wr, spi_hold;
119
        reg     [31:0]   spi_in;
120
        reg     [1:0]    spi_len;
121
        wire    [31:0]   spi_out;
122
        wire            spi_valid, spi_busy;
123
        wire            w_spi_sck, w_spi_cs_n;
124
        wire            w_spi_mosi;
125
        // wire [22:0]  spi_dbg;
126
        lldspi  lldriver(i_clk_100mhz,
127
                        spi_wr, spi_hold, spi_in, spi_len,
128
                                spi_out, spi_valid, spi_busy,
129
                        w_spi_sck, w_spi_cs_n, i_spi_cs_n, w_spi_mosi,
130
                                i_spi_miso);
131
 
132
        // Erase status tracking
133
        reg             write_in_progress, write_protect;
134
        reg [(AW-1-SW):0] erased_sector;
135
        reg             dirty_sector;
136
        initial begin
137
                write_in_progress = 1'b0;
138
                erased_sector = 0;
139
                dirty_sector  = 1'b1;
140
                write_protect = 1'b1;
141
        end
142
 
143
        reg     [7:0]    last_status;
144
        reg             spif_cmd, spif_override;
145
        reg [(AW-1):0]   spif_addr;
146
        reg     [31:0]   spif_data;
147
        reg     [5:0]    state;
148
        reg             spif_ctrl, spif_req;
149
        wire    [(AW-1-SW):0]    spif_sector;
150
        assign  spif_sector = spif_addr[(AW-1):SW];
151
 
152
        // assign       o_debug = { spi_wr, spi_hold, state, spi_dbg };
153
 
154
        initial state = `WBSPI_RESET;
155
        initial o_wb_ack   = 1'b0;
156
        initial o_wb_stall = 1'b1;
157
        initial spi_wr     = 1'b0;
158
        initial spi_len    = 2'b00;
159
        initial o_interrupt= 1'b0;
160
        always @(posedge i_clk_100mhz)
161
        begin
162
        if (state == `WBSPI_RESET)
163
        begin
164
                // From a reset, we should
165
                //      Enable the Quad I/O mode
166
                //      Disable the Write protection bits in the status register
167
                //      Chip should already be up and running, so we can start
168
                //      immediately ....
169
                o_wb_ack <= 1'b0;
170
                o_wb_stall <= 1'b1;
171
                spi_wr   <= 1'b0;
172
                spi_hold <= 1'b0;
173
                last_status <= 8'h00;
174
                state <= `WBSPI_IDLE;
175
                spif_req <= 1'b0;
176
        end else if (state == `WBSPI_IDLE)
177
        begin
178
                o_interrupt <= 1'b0;
179
                o_wb_stall <= 1'b0;
180
                o_wb_ack <= 1'b0;
181
                spif_cmd   <= i_wb_we;
182
                spif_addr  <= i_wb_addr;
183
                spif_data  <= i_wb_data;
184
                spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
185
                spif_req   <= (i_wb_ctrl_stb)||(i_wb_data_stb);
186
                spi_wr   <= 1'b0; // Keep the port idle, unless told otherwise
187
                spi_hold <= 1'b0;
188
                // Data register access
189
                if ((i_wb_data_stb)&&(i_wb_cyc))
190
                begin
191
 
192
                        if (i_wb_we) // Request to write a page
193
                        begin
194
                                if((~write_protect)&&(~write_in_progress))
195
                                begin // 00
196
                                        spi_wr <= 1'b1;
197
                                        spi_len <= 2'b00; // 8 bits
198
                                        // Send a write enable command
199
                                        spi_in <= { 8'h06, 24'h00 };
200
                                        state <= `WBSPI_WEN;
201
 
202
                                        o_wb_ack <= 1'b0;
203
                                        o_wb_stall <= 1'b1;
204
                                end else if (write_protect)
205
                                begin // whether or not write-in_progress ...
206
                                        // Do nothing on a write protect
207
                                        // violation
208
                                        //
209
                                        o_wb_ack <= 1'b1;
210
                                        o_wb_stall <= 1'b0;
211
                                end else begin // write is in progress, wait
212
                                        // for it to complete
213
                                        state <= `WBSPI_WAIT_WIP_CLEAR;
214
                                        o_wb_ack <= 1'b0;
215
                                        o_wb_stall <= 1'b1;
216
                                end
217
                        end else if (~write_in_progress)
218
                        begin // Read access, normal mode(s)
219
                                o_wb_ack   <= 1'b0;
220
                                o_wb_stall <= 1'b1;
221
                                spi_wr     <= 1'b1;     // Write cmd to device
222
                                spi_in <= { 8'h0b,
223
                                        {(22-AW){1'b0}},
224
                                        i_wb_addr[(AW-1):0], 2'b00 };
225
                                state <= `WBSPI_RD_DUMMY;
226
                                spi_len    <= 2'b11; // cmd+addr,32bits
227
                        end else begin
228
                                // A write is in progress ... need to stall
229
                                // the bus until the write is complete.
230
                                state <= `WBSPI_WAIT_WIP_CLEAR;
231
                                o_wb_ack   <= 1'b0;
232
                                o_wb_stall <= 1'b1;
233
                        end
234
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)&&(i_wb_we))
235
                begin
236
                        o_wb_stall <= 1'b1;
237
                        case(i_wb_addr[1:0])
238
                        2'b00: begin // Erase command register
239
                                write_protect <= ~i_wb_data[28];
240
                                o_wb_stall <= 1'b0;
241
 
242
                                if((i_wb_data[31])&&(~write_in_progress))
243
                                begin
244
                                        // Command an erase--ack it immediately
245
 
246
                                        o_wb_ack <= 1'b1;
247
                                        o_wb_stall <= 1'b0;
248
 
249
                                        if ((i_wb_data[31])&&(~write_protect))
250
                                        begin
251
                                                spi_wr <= 1'b1;
252
                                                spi_len <= 2'b00;
253
                                                // Send a write enable command
254
                                                spi_in <= { 8'h06, 24'h00 };
255
                                                state <= `WBSPI_ERASE_CMD;
256
                                                o_wb_stall <= 1'b1;
257
                                        end
258
                                end else if (i_wb_data[31])
259
                                begin
260
                                        state <= `WBSPI_WAIT_WIP_CLEAR;
261
                                        o_wb_ack   <= 1'b1;
262
                                        o_wb_stall <= 1'b1;
263
                                end else
264
                                        o_wb_ack   <= 1'b1;
265
                                        o_wb_stall <= 1'b0;
266
                                end
267
                        2'b01: begin
268
                                /*
269
                                // Write the configuration register
270
                                o_wb_ack <= 1'b1;
271
                                o_wb_stall <= 1'b1;
272
 
273
                                // Need to send a write enable command first
274
                                spi_wr <= 1'b1;
275
                                spi_len <= 2'b00; // 8 bits
276
                                // Send a write enable command
277
                                spi_in <= { 8'h06, 24'h00 };
278
                                state <= `WBSPI_WRITE_CONFIG;
279
                                */
280
                                o_wb_ack <= 1'b1; // Ack immediately
281
                                o_wb_stall <= 1'b0; // No stall, but do nothing
282
                                end
283
                        2'b10: begin
284
                                /*
285
                                // Write the status register
286
                                o_wb_ack <= 1'b1; // Ack immediately
287
                                o_wb_stall <= 1'b1; // Stall other cmds
288
                                // Need to send a write enable command first
289
                                spi_wr <= 1'b1;
290
                                spi_len <= 2'b00; // 8 bits
291
                                // Send a write enable command
292
                                spi_in <= { 8'h06, 24'h00 };
293
                                state <= `WBSPI_WRITE_STATUS;
294
                                */
295
                                o_wb_ack <= 1'b1; // Ack immediately
296
                                o_wb_stall <= 1'b0; // No stall, but do nothing
297
                                end
298
                        2'b11: begin // Write the ID register??? makes no sense
299
                                o_wb_ack <= 1'b1;
300
                                o_wb_stall <= 1'b0;
301
                                end
302
                        endcase
303
                end else if ((i_wb_cyc)&&(i_wb_ctrl_stb)) // &&(~i_wb_we))
304
                begin
305
                        case(i_wb_addr[1:0])
306
                        2'b00: begin // Read local register
307
                                if (write_in_progress) // Read status
308
                                begin// register, is write still in progress?
309
                                        state <= `WBSPI_READ_STATUS;
310
                                        spi_wr <= 1'b1;
311
                                        spi_len <= 2'b01;// 8 bits out, 8 bits in
312
                                        spi_in <= { 8'h05, 24'h00};
313
 
314
                                        o_wb_ack <= 1'b0;
315
                                        o_wb_stall <= 1'b1;
316
                                end else begin // Return w/o talking to device
317
                                        o_wb_ack <= 1'b1;
318
                                        o_wb_stall <= 1'b0;
319
                                        o_wb_data <= { write_in_progress,
320
                                                dirty_sector, spi_busy,
321
                                                ~write_protect,
322
                                                {(28-AW){1'b0}},
323
                                                erased_sector, {(SW){1'b0}} };
324
                                end end
325
                        2'b01: begin // Read configuration register
326
                                state <= `WBSPI_READ_CONFIG;
327
                                spi_wr <= 1'b1;
328
                                spi_len <= 2'b01;
329
                                spi_in <= { 8'h35, 24'h00};
330
 
331
                                o_wb_ack <= 1'b0;
332
                                o_wb_stall <= 1'b1;
333
                                end
334
                        2'b10: begin // Read status register
335
                                state <= `WBSPI_READ_STATUS;
336
                                spi_wr <= 1'b1;
337
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
338
                                spi_in <= { 8'h05, 24'h00};
339
 
340
                                o_wb_ack <= 1'b0;
341
                                o_wb_stall <= 1'b1;
342
                                end
343
                        2'b11: begin // Read ID register
344
                                state <= `WBSPI_READ_ID_CMD;
345
                                spi_wr <= 1'b1;
346
                                spi_len <= 2'b00;
347
                                spi_in <= { 8'h9f, 24'h00};
348
 
349
                                o_wb_ack <= 1'b0;
350
                                o_wb_stall <= 1'b1;
351
                                end
352
                        endcase
353
                end else if ((~i_wb_cyc)&&(write_in_progress))
354
                begin
355
                        state <= `WBSPI_IDLE_CHECK_WIP;
356
                        spi_wr <= 1'b1;
357
                        spi_len <= 2'b01; // 8 bits out, 8 bits in
358
                        spi_in <= { 8'h05, 24'h00};
359
 
360
                        o_wb_ack <= 1'b0;
361
                        o_wb_stall <= 1'b1;
362
                end
363
        end else if (state == `WBSPI_WAIT_WIP_CLEAR)
364
        begin
365
                o_wb_stall <= 1'b1;
366
                o_wb_ack   <= 1'b0;
367
                spi_wr <= 1'b0;
368
                spif_req<= (spif_req) && (i_wb_cyc);
369
                if (~spi_busy)
370
                begin
371
                        spi_wr   <= 1'b1;
372
                        spi_in   <= { 8'h05, 24'h0000 };
373
                        spi_hold <= 1'b1;
374
                        spi_len  <= 2'b01; // 16 bits write, so we can read 8
375
                        state <= `WBSPI_CHECK_WIP_CLEAR;
376
                end
377
        end else if (state == `WBSPI_CHECK_WIP_CLEAR)
378
        begin
379
                o_wb_stall <= 1'b1;
380
                o_wb_ack   <= 1'b0;
381
                // Repeat as often as necessary until we are clear
382
                spi_wr <= 1'b1;
383
                spi_in <= 32'h0000; // Values here are actually irrelevant
384
                spi_hold <= 1'b1;
385
                spi_len <= 2'b00; // One byte at a time
386
                spif_req<= (spif_req) && (i_wb_cyc);
387
                if ((spi_valid)&&(~spi_out[0]))
388
                begin
389
                        state <= `WBSPI_CHECK_WIP_DONE;
390
                        spi_wr   <= 1'b0;
391
                        spi_hold <= 1'b0;
392
                        write_in_progress <= 1'b0;
393
                        last_status <= spi_out[7:0];
394
                end
395
        end else if (state == `WBSPI_CHECK_WIP_DONE)
396
        begin
397
                o_wb_stall <= 1'b1;
398
                o_wb_ack   <= 1'b0;
399
                // Let's let the SPI port come back to a full idle,
400
                // and the chip select line go low before continuing
401
                spi_wr   <= 1'b0;
402
                spi_len  <= 2'b00;
403
                spi_hold <= 1'b0;
404
                spif_req<= (spif_req) && (i_wb_cyc);
405
                if ((o_spi_cs_n)&&(~spi_busy)) // Chip select line is high, we can continue
406
                begin
407
                        spi_wr   <= 1'b0;
408
                        spi_hold <= 1'b0;
409
 
410
                        casez({ spif_cmd, spif_ctrl, spif_addr[1:0] })
411
                        4'b00??: begin // Read data from ... somewhere
412
                                spi_wr     <= 1'b1;     // Write cmd to device
413
                                spi_in <= { 8'h0b, {(22-AW){1'b0}},
414
                                        spif_addr[(AW-1):0], 2'b00 };
415
                                state <= `WBSPI_RD_DUMMY;
416
                                spi_len    <= 2'b11; // Send cmd and addr
417
                                end
418
                        4'b10??: begin // Write data to ... anywhere
419
                                spi_wr <= 1'b1;
420
                                spi_len <= 2'b00; // 8 bits
421
                                // Send a write enable command
422
                                spi_in <= { 8'h06, 24'h00 };
423
                                state <= `WBSPI_WEN;
424
                                end
425
                        4'b0110: begin // Read status register
426
                                state <= `WBSPI_READ_STATUS;
427
                                spi_wr <= 1'b1;
428
                                spi_len <= 2'b01; // 8 bits out, 8 bits in
429
                                spi_in <= { 8'h05, 24'h00};
430
                                end
431
                        4'b0111: begin
432
                                state <= `WBSPI_READ_ID_CMD;
433
                                spi_wr <= 1'b1;
434
                                spi_len <= 2'b00;
435
                                spi_in <= { 8'h9f, 24'h00};
436
                                end
437
                        default: begin //
438
                                o_wb_stall <= 1'b1;
439
                                o_wb_ack <= spif_req;
440
                                state <= `WBSPI_WAIT_TIL_IDLE;
441
                                end
442
                        endcase
443
                // spif_cmd   <= i_wb_we;
444
                // spif_addr  <= i_wb_addr;
445
                // spif_data  <= i_wb_data;
446
                // spif_ctrl  <= (i_wb_ctrl_stb)&&(~i_wb_data_stb);
447
                // spi_wr <= 1'b0; // Keep the port idle, unless told otherwise
448
                end
449
        end else if (state == `WBSPI_WEN)
450
        begin // We came here after issuing a write enable command
451
                spi_wr <= 1'b0;
452
                o_wb_ack <= 1'b0;
453
                o_wb_stall <= 1'b1;
454
                spif_req<= (spif_req) && (i_wb_cyc);
455
                if ((~spi_busy)&&(o_spi_cs_n)&&(~spi_wr)) // Let's come to a full stop
456
                        state <= `WBSPI_PP;
457
        end else if (state == `WBSPI_PP)
458
        begin // We come here under a full stop / full port idle mode
459
                // Issue our command immediately
460
                spi_wr <= 1'b1;
461
                spi_in <= { 8'h02, {(22-AW){1'b0}}, spif_addr, 2'b00 };
462
                spi_len <= 2'b11;
463
                spi_hold <= 1'b1;
464
                spif_req<= (spif_req) && (i_wb_cyc);
465
 
466
                // Once we get busy, move on
467
                if (spi_busy)
468
                        state <= `WBSPI_WR_DATA;
469
                if (spif_sector == erased_sector)
470
                        dirty_sector <= 1'b1;
471
        end else if (state == `WBSPI_WR_DATA)
472
        begin
473
                o_wb_stall <= 1'b1;
474
                o_wb_ack   <= 1'b0;
475
                spi_wr   <= 1'b1; // write without waiting
476
                spi_in   <= {
477
                        spif_data[ 7: 0],
478
                        spif_data[15: 8],
479
                        spif_data[23:16],
480
                        spif_data[31:24] };
481
                spi_len  <= 2'b11; // Write 4 bytes
482
                spi_hold <= 1'b1;
483
                if (~spi_busy)
484
                begin
485
                        o_wb_ack <= spif_req; // Ack when command given
486
                        state <= `WBSPI_WR_BUS_CYCLE;
487
                end
488
                spif_req<= (spif_req) && (i_wb_cyc);
489
        end else if (state == `WBSPI_WR_BUS_CYCLE)
490
        begin
491
                o_wb_ack <= 1'b0; // Turn off our ack and stall flags
492
                o_wb_stall <= 1'b1;
493
                spi_wr <= 1'b0;
494
                spi_hold <= 1'b1;
495
                write_in_progress <= 1'b1;
496
                spif_req<= (spif_req) && (i_wb_cyc);
497
                if (~i_wb_cyc)
498
                begin
499
                        state <= `WBSPI_WAIT_TIL_IDLE;
500
                        spi_hold <= 1'b0;
501
                end else if (spi_wr)
502
                begin // Give the SPI a chance to get busy on the last write
503
                        // Do nothing here.
504
                end else if ((i_wb_data_stb)&&(i_wb_we)
505
                                &&(i_wb_addr == (spif_addr+1))
506
                                &&(i_wb_addr[(AW-1):PW]==spif_addr[(AW-1):PW]))
507
                begin
508
// CHECK ME!
509
                        spif_cmd  <= 1'b1;
510
                        spif_data <= i_wb_data;
511
                        spif_addr <= i_wb_addr;
512
                        spif_ctrl  <= 1'b0;
513
                        spif_req<= 1'b1;
514
                        // We'll keep the bus stalled on this request
515
                        // for a while
516
                        state <= `WBSPI_WR_DATA;
517
                        o_wb_ack   <= 1'b0;
518
                        o_wb_stall <= 1'b0;
519
                end else if ((i_wb_data_stb|i_wb_ctrl_stb)&&(~o_wb_ack)) // Writing out of bounds
520
                begin
521
                        spi_hold <= 1'b0;
522
                        spi_wr   <= 1'b0;
523
                        state <= `WBSPI_WAIT_TIL_IDLE;
524
                end // Otherwise we stay here
525
        end else if (state == `WBSPI_RD_DUMMY)
526
        begin
527
                o_wb_ack   <= 1'b0;
528
                o_wb_stall <= 1'b1;
529
 
530
                spi_wr <= 1'b1; // Non-stop
531
                // Need to read one byte of dummy data,
532
                // just to consume 8 clocks
533
                spi_in <= { 8'h00, 24'h00 };
534
                spi_len <= 2'b00; // Read 8 bits
535
                spi_hold <= 1'b0;
536
                spif_req<= (spif_req) && (i_wb_cyc);
537
 
538
                if ((~spi_busy)&&(~o_spi_cs_n))
539
                        // Our command was accepted
540
                        state <= `WBSPI_READ_CMD;
541
        end else if (state == `WBSPI_READ_CMD)
542
        begin // Issue our first command to read 32 bits.
543
                o_wb_ack   <= 1'b0;
544
                o_wb_stall <= 1'b1;
545
 
546
                spi_wr <= 1'b1;
547
                spi_in <= { 8'hff, 24'h00 }; // Empty
548
                spi_len <= 2'b11; // Read 32 bits
549
                spi_hold <= 1'b0;
550
                spif_req<= (spif_req) && (i_wb_cyc);
551
                if ((spi_valid)&&(spi_len == 2'b11))
552
                        state <= `WBSPI_READ_DATA;
553
        end else if (state == `WBSPI_READ_DATA)
554
        begin
555
                // Pipelined read support
556
                spi_wr <=((i_wb_cyc)&&(i_wb_data_stb)&&(~i_wb_we)&&(i_wb_addr== (spif_addr+1)));
557
                spi_in <= 32'h00;
558
                spi_len <= 2'b11;
559
                // Don't let the device go to idle until the bus cycle ends.
560
                //      This actually prevents a *really* nasty race condition,
561
                //      where the strobe comes in after the lower level device
562
                //      has decided to stop waiting.  The write is then issued,
563
                //      but no one is listening.  By leaving the device open,
564
                //      the device is kept in a state where a valid strobe
565
                //      here will be useful.  Of course, we don't accept
566
                //      all commands, just reads.  Further, the strobe needs
567
                //      to be high for two clocks cycles without changing
568
                //      anything on the bus--one for us to notice it and pull
569
                //      our head out of the sand, and a second for whoever
570
                //      owns the bus to realize their command went through.
571
                spi_hold <= 1'b1;
572
                spif_req<= (spif_req) && (i_wb_cyc);
573
                if ((spi_valid)&&(~spi_in[31]))
574
                begin // Single pulse acknowledge and write data out
575
                        o_wb_ack <= spif_req;
576
                        o_wb_stall <= (~spi_wr);
577
                        // adjust endian-ness to match the PC
578
                        o_wb_data <= { spi_out[7:0], spi_out[15:8],
579
                                spi_out[23:16], spi_out[31:24] };
580
                        state <= (spi_wr)?`WBSPI_READ_DATA
581
                                : `WBSPI_WAIT_TIL_IDLE;
582
                        spif_req <= spi_wr;
583
                        spi_hold <= (~spi_wr);
584
                        if (spi_wr)
585
                                spif_addr <= i_wb_addr;
586
                end else if (~i_wb_cyc)
587
                begin // FAIL SAFE: If the bus cycle ends, forget why we're
588
                        // here, just go back to idle
589
                        state <= `WBSPI_WAIT_TIL_IDLE;
590
                        spi_hold <= 1'b0;
591
                        o_wb_ack <= 1'b0;
592
                        o_wb_stall <= 1'b1;
593
                end else begin
594
                        o_wb_ack <= 1'b0;
595
                        o_wb_stall <= 1'b1;
596
                end
597
        end else if (state == `WBSPI_READ_ID_CMD)
598
        begin // We came into here immediately after issuing a 0x9f command
599
                // Now we need to read 32 bits of data.  Result should be
600
                // 0x0102154d (8'h manufacture ID, 16'h device ID, followed
601
                // by the number of extended bytes available 8'h4d).
602
                o_wb_ack <= 1'b0;
603
                o_wb_stall<= 1'b1;
604
 
605
                spi_wr <= 1'b1; // No data to send, but need four bytes, since
606
                spi_len <= 2'b11; // 32 bits of data are ... useful
607
                spi_in <= 32'h00; // Irrelevant
608
                spi_hold <= 1'b0;
609
                spif_req <= (spif_req) && (i_wb_cyc);
610
                if ((~spi_busy)&&(~o_spi_cs_n)&&(spi_len == 2'b11))
611
                        // Our command was accepted, now go read the result
612
                        state <= `WBSPI_READ_ID;
613
        end else if (state == `WBSPI_READ_ID)
614
        begin
615
                o_wb_ack <= 1'b0; // Assuming we're still waiting
616
                o_wb_stall <= 1'b1;
617
 
618
                spi_wr <= 1'b0; // No more writes, we've already written the cmd
619
                spi_hold <= 1'b0;
620
                spif_req <= (spif_req) && (i_wb_cyc);
621
 
622
                // Here, we just wait until the result comes back
623
                // The problem is, the result may be the previous result.
624
                // So we use spi_len as an indicator
625
                spi_len <= 2'b00;
626
                if((spi_valid)&&(spi_len==2'b00))
627
                begin // Put the results out as soon as possible
628
                        o_wb_data <= spi_out[31:0];
629
                        o_wb_ack <= spif_req;
630
                        spif_req <= 1'b0;
631
                end else if ((~spi_busy)&&(o_spi_cs_n))
632
                begin
633
                        state <= `WBSPI_IDLE;
634
                        o_wb_stall <= 1'b0;
635
                end
636
        end else if (state == `WBSPI_READ_STATUS)
637
        begin // We enter after the command has been given, for now just
638
                // read and return
639
                spi_wr <= 1'b0;
640
                o_wb_ack <= 1'b0;
641
                spi_hold <= 1'b0;
642
                spif_req <= (spif_req) && (i_wb_cyc);
643
                if (spi_valid)
644
                begin
645
                        o_wb_ack <= spif_req;
646
                        o_wb_stall <= 1'b1;
647
                        spif_req <= 1'b0;
648
                        last_status <= spi_out[7:0];
649
                        write_in_progress <= spi_out[0];
650
                        if (spif_addr[1:0] == 2'b00) // Local read, checking
651
                        begin // status, 'cause we're writing
652
                                o_wb_data <= { spi_out[0],
653
                                        dirty_sector, spi_busy,
654
                                        ~write_protect,
655
                                        {(28-AW){1'b0}},
656
                                        erased_sector, {(SW){1'b0}} };
657
                        end else begin
658
                                o_wb_data <= { 24'h00, spi_out[7:0] };
659
                        end
660
                end
661
 
662
                if ((~spi_busy)&&(~spi_wr))
663
                        state <= `WBSPI_IDLE;
664
        end else if (state == `WBSPI_READ_CONFIG)
665
        begin // We enter after the command has been given, for now just
666
                // read and return
667
                spi_wr <= 1'b0;
668
                o_wb_ack <= 1'b0;
669
                o_wb_stall <= 1'b1;
670
                spi_hold <= 1'b0;
671
                spif_req <= (spif_req) && (i_wb_cyc);
672
 
673
                if (spi_valid)
674
                        o_wb_data <= { 24'h00, spi_out[7:0] };
675
 
676
                if ((~spi_busy)&&(~spi_wr))
677
                begin
678
                        state <= `WBSPI_IDLE;
679
                        o_wb_ack   <= spif_req;
680
                        o_wb_stall <= 1'b0;
681
                        spif_req <= 1'b0;
682
                end
683
        end else if (state == `WBSPI_WRITE_CONFIG)
684
        begin // We enter immediately after commanding a WEN
685
                o_wb_ack   <= 1'b0;
686
                o_wb_stall <= 1'b1;
687
 
688
                spi_len <= 2'b10;
689
                spi_in <= { 8'h01, last_status,
690
                                spif_data[7:2], 1'b0,spif_data[0], 8'h00 };
691
                spi_wr <= 1'b0;
692
                spi_hold <= 1'b0;
693
                spif_req <= (spif_req) && (i_wb_cyc);
694
                if ((~spi_busy)&&(~spi_wr))
695
                begin
696
                        spi_wr <= 1'b1;
697
                        state <= `WBSPI_WAIT_TIL_IDLE;
698
                        write_in_progress <= 1'b1;
699
                end
700
        end else if (state == `WBSPI_WRITE_STATUS)
701
        begin // We enter immediately after commanding a WEN
702
                o_wb_ack   <= 1'b0;
703
                o_wb_stall <= 1'b1;
704
 
705
                spi_len <= 2'b01;
706
                spi_in <= { 8'h01, spif_data[7:0], 16'h00 };
707
                // last_status <= i_wb_data[7:0]; // We'll read this in a moment
708
                spi_wr <= 1'b0;
709
                spi_hold <= 1'b0;
710
                spif_req <= (spif_req) && (i_wb_cyc);
711
                if ((~spi_busy)&&(~spi_wr))
712
                begin
713
                        spi_wr <= 1'b1;
714
                        last_status <= spif_data[7:0];
715
                        write_in_progress <= 1'b1;
716
                        if(((last_status[6])||(last_status[5]))
717
                                &&((~spif_data[6])&&(~spif_data[5])))
718
                                state <= `WBSPI_CLEAR_STATUS;
719
                        else
720
                                state <= `WBSPI_WAIT_TIL_IDLE;
721
                end
722
        end else if (state == `WBSPI_ERASE_CMD)
723
        begin // Know that WIP is clear on entry, WEN has just been commanded
724
                spi_wr     <= 1'b0;
725
                o_wb_ack   <= 1'b0;
726
                o_wb_stall <= 1'b1;
727
                spi_hold   <= 1'b0;
728
                spif_req <= (spif_req) && (i_wb_cyc);
729
 
730
                // Here's the erase command
731
                //spi_in <= { 8'hd8, 4'h0, spif_data[17:14], 14'h000, 2'b00 };
732
                spi_in <= { 8'h20, 4'h0, spif_data[(AW-1):SW],
733
                                {(SW){1'b0}}, 2'b00 };
734
                spi_len <= 2'b11; // 32 bit write
735
                // together with setting our copy of the WIP bit
736
                write_in_progress <= 1'b1;
737
                // keeping track of which sector we just erased
738
                erased_sector <= spif_data[(AW-1):SW];
739
                // and marking this erase sector as no longer dirty
740
                dirty_sector <= 1'b0;
741
 
742
                // Wait for a full stop before issuing this command
743
                if ((~spi_busy)&&(~spi_wr)&&(o_spi_cs_n))
744
                begin // When our command is accepted, move to the next state
745
                        spi_wr <= 1'b1;
746
                        state <= `WBSPI_ERASE_BLOCK;
747
                end
748
        end else if (state == `WBSPI_ERASE_BLOCK)
749
        begin
750
                spi_wr     <= 1'b0;
751
                spi_hold   <= 1'b0;
752
                o_wb_stall <= 1'b1;
753
                o_wb_ack   <= 1'b0;
754
                spif_req <= (spif_req) && (i_wb_cyc);
755
                // When the port clears, we can head back to idle
756
                if ((~spi_busy)&&(~spi_wr))
757
                begin
758
                        o_wb_ack <= spif_req;
759
                        state <= `WBSPI_IDLE;
760
                end
761
        end else if (state == `WBSPI_CLEAR_STATUS)
762
        begin // Issue a clear status command
763
                spi_wr <= 1'b1;
764
                spi_hold <= 1'b0;
765
                spi_len <= 2'b00; // 8 bit command
766
                spi_in <= { 8'h30, 24'h00 };
767
                last_status[6:5] <= 2'b00;
768
                spif_req <= (spif_req) && (i_wb_cyc);
769
                if ((spi_wr)&&(~spi_busy))
770
                        state <= `WBSPI_WAIT_TIL_IDLE;
771
        end else if (state == `WBSPI_IDLE_CHECK_WIP)
772
        begin // We are now in read status register mode
773
 
774
                // No bus commands have (yet) been given
775
                o_wb_stall <= 1'b1;
776
                o_wb_ack   <= 1'b0;
777
                spif_req <= (spif_req) && (i_wb_cyc);
778
 
779
                // Stay in this mode unless/until we get a command, or
780
                //      the write is over
781
                spi_wr <= (((~i_wb_cyc)||((~i_wb_data_stb)&&(~i_wb_ctrl_stb)))
782
                                &&(write_in_progress));
783
                spi_len <= 2'b00; // 8 bit reads
784
                if (spi_valid)
785
                begin
786
                        write_in_progress <= spi_out[0];
787
                        if ((~spi_out[0])&&(write_in_progress))
788
                                o_interrupt <= 1'b1;
789
                end else
790
                        o_interrupt <= 1'b0;
791
 
792
                if ((~spi_wr)&&(~spi_busy)&&(o_spi_cs_n))
793
                begin // We can now go to idle and process a command
794
                        o_wb_stall <= 1'b0;
795
                        o_wb_ack   <= 1'b0;
796
                        state <= `WBSPI_IDLE;
797
                end
798
        end else // if (state == `WBSPI_WAIT_TIL_IDLE) or anything else
799
        begin
800
                spi_wr     <= 1'b0;
801
                spi_hold   <= 1'b0;
802
                o_wb_stall <= 1'b1;
803
                o_wb_ack   <= 1'b0;
804
                spif_req   <= 1'b0;
805
                if ((~spi_busy)&&(o_spi_cs_n)&&(~spi_wr)) // Wait for a full
806
                begin // clearing of the SPI port before moving on
807
                        state <= `WBSPI_IDLE;
808
                        o_wb_stall <= 1'b0;
809
                        o_wb_ack   <= 1'b0; // Shouldn't be acking anything here
810
                end
811
        end
812
        end
813
 
814
        // Command and control during the reset sequence
815
        assign  o_spi_cs_n = w_spi_cs_n;
816
        assign  o_spi_sck  = w_spi_sck;
817
        assign  o_spi_mosi = w_spi_mosi;
818
endmodule

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