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[/] [xulalx25soc/] [trunk/] [rtl/] [wbubus.v] - Blame information for rev 115

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1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbubus.v
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//
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// Project:     FPGA library
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//
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// Purpose:     This is the top level file for the entire JTAG-USB to Wishbone
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//              bus conversion.  (It's also the place to start debugging, should
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//      things not go as planned.)  Bytes come into this routine, bytes go out,
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//      and the wishbone bus (external to this routine) is commanded in between.
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//
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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module  wbubus(i_clk, i_rx_stb, i_rx_data,
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                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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                i_interrupt,
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                o_tx_stb, o_tx_data, i_tx_busy, o_dbg);
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        parameter       LGWATCHDOG=19;
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        input                   i_clk;
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        input                   i_rx_stb;
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        input           [7:0]    i_rx_data;
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        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
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        output  wire    [31:0]   o_wb_addr, o_wb_data;
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        input                   i_wb_ack, i_wb_stall, i_wb_err;
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        input           [31:0]   i_wb_data;
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        input                   i_interrupt;
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        output  wire            o_tx_stb;
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        output  wire    [7:0]    o_tx_data;
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        input                   i_tx_busy;
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        output  wire            o_dbg;
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        reg             r_wdt_reset;
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        // Decode ASCII input requests into WB bus cycle requests
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        wire            in_stb;
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        wire    [35:0]   in_word;
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        wbuinput        getinput(i_clk, i_rx_stb, i_rx_data, in_stb, in_word);
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        wire    w_bus_busy, fifo_in_stb, exec_stb, w_bus_reset;
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        wire    [35:0]   fifo_in_word, exec_word;
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// `define      NO_INPUT_FIFO
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`ifdef  NO_INPUT_FIFO
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        assign  fifo_in_stb = in_stb;
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        assign  fifo_in_word = in_word;
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        assign  w_bus_reset = 1'b0;
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`else
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        wire            ififo_empty_n, ififo_err;
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        assign  fifo_in_stb = (~w_bus_busy)&&(ififo_empty_n);
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        assign  w_bus_reset = r_wdt_reset;
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        wbufifo #(36,6) padififo(i_clk, w_bus_reset,
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                                in_stb, in_word, fifo_in_stb, fifo_in_word,
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                                ififo_empty_n, ififo_err);
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`endif
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        // Take requests in, Run the bus, send results out
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        // This only works if no requests come in while requests
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        // are pending.
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        wbuexec runwb(i_clk, r_wdt_reset, fifo_in_stb, fifo_in_word, w_bus_busy,
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                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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                exec_stb, exec_word);
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        /*
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        wire    [31:0]  cyc_debug;
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        assign  cyc_debug = { 1'b0, o_wb_cyc, o_wb_stb, o_wb_we, i_wb_ack, i_wb_stall,
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                                (i_wb_err||r_wdt_reset), o_wb_addr[14:0],
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                                o_wb_data[4:0], i_wb_data[4:0] };
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        assign  o_dbg = cyc_debug;
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        */
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        /*
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        wire    [31:0]  fif_debug;
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        assign  fif_debug = {
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                        (exec_stb)&&(exec_word[35:30] == 6'h05),// 1
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                        fifo_in_stb, fifo_in_word[35:30],       // 7
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                        exec_stb, exec_word[35:30],             // 7
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                        o_wb_cyc, o_wb_stb, o_wb_we,
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                                i_wb_ack, i_wb_stall,           // 5
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                        w_bus_busy, ififo_empty_n, w_bus_reset, // 3
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                        i_rx_stb, o_wb_addr[7:0] };             // 9
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        assign  o_dbg = fif_debug;
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        */
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        wire            ofifo_err;
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        // wire [30:0]  out_dbg;
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        wbuoutput       wroutput(i_clk, w_bus_reset,
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                        exec_stb, exec_word,
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                        o_wb_cyc, i_interrupt, exec_stb,
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                        o_tx_stb, o_tx_data, i_tx_busy, ofifo_err);
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        // Add in a watchdog timer to the bus
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        reg     [(LGWATCHDOG-1):0]       r_wdt_timer;
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        initial r_wdt_reset = 1'b0;
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        initial r_wdt_timer = 0;
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        always @(posedge i_clk)
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                if ((~o_wb_cyc)||(i_wb_ack))
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                begin
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                        r_wdt_timer <= 0;
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                        r_wdt_reset <= 1'b0;
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                end else if (&r_wdt_timer)
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                begin
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                        r_wdt_reset <= 1'b1;
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                        r_wdt_timer <= 0;
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                end else begin
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                        r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1};
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                        r_wdt_reset <= 1'b0;
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                end
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        assign  o_dbg = w_bus_reset;
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endmodule
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