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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbudeword.v
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//
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dgisselq |
// Project: FPGA library
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dgisselq |
//
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// Purpose: Once a word has come from the bus, undergone compression, had
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// idle cycles and interrupts placed in it, this routine converts
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// that word form a 36-bit single word into a series of 6-bit words
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// that can head to the output routine. Hence, it 'deword's the value:
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// unencoding the 36-bit word encoding.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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dgisselq |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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dgisselq |
//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module wbudeword(i_clk, i_stb, i_word, i_tx_busy, o_stb, o_nl_hexbits, o_busy);
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input i_clk, i_stb;
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input [35:0] i_word;
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input i_tx_busy;
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output reg o_stb;
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output reg [6:0] o_nl_hexbits;
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output reg o_busy;
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wire [2:0] w_len;
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assign w_len = (i_word[35:33]==3'b000)? 3'b001
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: (i_word[35:32]==4'h2)? 3'b110
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: (i_word[35:32]==4'h3)? (3'b010+{1'b0,i_word[31:30]})
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: (i_word[35:34]==2'b01)? 3'b010
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: (i_word[35:34]==2'b10)? 3'b001
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: 3'b110;
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reg r_dly;
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reg [2:0] r_len;
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reg [29:0] r_word;
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initial o_stb = 1'b0;
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initial o_busy = 1'b0;
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initial r_dly = 1'b0;
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always @(posedge i_clk)
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if ((i_stb)&&(~o_busy)) // Only accept when not busy
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begin
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r_len <= w_len-3'b001;
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r_word <= i_word[29:0];
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o_stb <= 1'b1;
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o_nl_hexbits <= { 1'b0, i_word[35:30] }; // No newline ... yet
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o_busy <= 1'b1;
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r_dly <= 1'b1;
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end else if ((o_stb)&&(i_tx_busy))
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begin
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o_busy <= 1'b1; // wait and do nothing
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r_dly <= 1'b1;
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end else if (o_stb) // and (~i_tx_busy) means ours was accepted
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o_stb <= 1'b0; // Delay one clock
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else if (r_len > 0)
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begin
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o_stb <= 1'b1;
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o_nl_hexbits <= { 1'b0, r_word[29:24] };
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r_word[29:6] <= r_word[23:0];
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r_len <= r_len - 3'b001;
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o_busy <= 1'b1; // wait and do nothing
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r_dly <= 1'b1;
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end else if (~o_nl_hexbits[6])
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begin
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o_stb <= 1'b1;
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o_nl_hexbits <= 7'h40;
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o_busy <= 1'b1; // wait and do nothing
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r_dly <= 1'b1;
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end else begin
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r_dly <= 1'b0;
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o_busy <= (r_dly);
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end
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endmodule
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