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[/] [xulalx25soc/] [trunk/] [rtl/] [wbuidleint.v] - Blame information for rev 112

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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbuidleint.v
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//
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// Project:     FPGA library
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//
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// Purpose:     Creates an output for the interface, inserting idle words and
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//              words indicating an interrupt has taken place into the output
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//      stream.  Henceforth, the output means more than just bus transaction
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//      results.  It may mean there is no bus transaction result to report,
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//      or that an interrupt has taken place.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module  wbuidleint(i_clk, i_stb, i_codword, i_cyc, i_busy, i_int,
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                o_stb, o_codword, o_busy,
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                i_tx_busy);
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        input                   i_clk;
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        // From the FIFO following the bus executor
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        input                   i_stb;
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        input           [35:0]   i_codword;
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        // From the rest of the board
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        input                   i_cyc, i_busy, i_int;
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        // To the next stage
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        output  reg             o_stb;
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        output  reg     [35:0]   o_codword;
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        output  reg             o_busy;
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        // Is the next stage busy?
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        input                   i_tx_busy;
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        reg     int_request, int_sent;
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        initial int_request = 1'b0;
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        always @(posedge i_clk)
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                if((o_stb)&&(~i_tx_busy)&&(o_codword[35:30]==6'h4))
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                        int_request <= i_int;
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                else
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                        int_request <= (int_request)||(i_int);
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        // Now, for the idle counter
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        wire            idle_expired;
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        reg             idle_state;
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        reg     [35:0]   idle_counter;
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        initial idle_counter = 36'h0000;
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        always @(posedge i_clk)
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                if ((i_stb)||(o_stb))
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                        idle_counter <= 36'h000;
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                else if (~idle_counter[35])
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                        idle_counter <= idle_counter + 36'd43;
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        initial idle_state = 1'b0;
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        always @(posedge i_clk)
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                if ((o_stb)&&(~i_tx_busy)&&(o_codword[35:31]==5'h0))
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                        idle_state <= 1'b1;
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                else if (~idle_counter[35])
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                        idle_state <= 1'b0;
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        assign  idle_expired = (~idle_state)&&(idle_counter[35]);
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        initial o_stb  = 1'b0;
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        initial o_busy = 1'b0;
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        always @(posedge i_clk)
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                if ((o_stb)&&(i_tx_busy))
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                begin
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                        o_busy <= 1'b1;
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                end else if (o_stb) // and not i_tx_busy
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                begin
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                        // Idle one clock before becoming not busy
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                        o_stb <= 1'b0;
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                        o_busy <= 1'b1;
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                end else if (o_busy)
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                        o_busy <= 1'b0;
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                else if (i_stb) // and (~o_busy)&&(~o_stb)
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                begin // On a valid output, just send it out
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                        // We'll open this strobe, even if the transmitter
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                        // is busy, just 'cause we might otherwise lose it
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                        o_codword <= i_codword;
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                        o_stb <= 1'b1;
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                        o_busy <= 1'b1;
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                end else if ((int_request)&&(~int_sent))
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                begin
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                        o_stb <= 1'b1;
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                        o_codword <= { 6'h4, 30'h0000 }; // interrupt codeword
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                        o_busy <= 1'b1;
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                end else if (idle_expired)
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                begin // Strobe, if we're not writing or our
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                        // last command wasn't an idle
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                        o_stb  <= 1'b1;
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                        o_busy <= 1'b1;
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                        if (i_cyc)
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                                o_codword <= { 6'h1, 30'h0000 }; // idle codeword, bus busy
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                        else
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                                o_codword <= { 6'h0, 30'h0000 };
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                end
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        initial int_sent = 1'b0;
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        always @(posedge i_clk)
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                if ((int_request)&&((~o_stb)&&(~o_busy)&&(~i_stb)))
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                        int_sent <= 1'b1;
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                else if (~i_int)
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                        int_sent <= 1'b0;
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endmodule

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