| 1 |
2 |
dgisselq |
///////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//
|
| 3 |
|
|
// Filename: wbureadcw.v
|
| 4 |
|
|
//
|
| 5 |
|
|
// Project: XuLA2 board
|
| 6 |
|
|
//
|
| 7 |
|
|
// Purpose: Read bytes from a serial port (i.e. the jtagser) and translate
|
| 8 |
|
|
// those bytes into a 6-byte codeword. This codeword may specify
|
| 9 |
|
|
// a number of values to be read, the value to be written, or an address
|
| 10 |
|
|
// to read/write from, or perhaps the end of a write sequence.
|
| 11 |
|
|
//
|
| 12 |
|
|
// See the encoding documentation file for more information.
|
| 13 |
|
|
//
|
| 14 |
|
|
//
|
| 15 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 16 |
|
|
// Gisselquist Technology, LLC
|
| 17 |
|
|
//
|
| 18 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 19 |
|
|
//
|
| 20 |
|
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
| 21 |
|
|
//
|
| 22 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
| 23 |
|
|
// modify it under the terms of the GNU General Public License as published
|
| 24 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
| 25 |
|
|
// your option) any later version.
|
| 26 |
|
|
//
|
| 27 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
| 28 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
| 29 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 30 |
|
|
// for more details.
|
| 31 |
|
|
//
|
| 32 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
| 33 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
| 34 |
|
|
//
|
| 35 |
|
|
//
|
| 36 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 37 |
|
|
//
|
| 38 |
|
|
//
|
| 39 |
|
|
// Goal: single clock pipeline, 50 slices or less
|
| 40 |
|
|
//
|
| 41 |
|
|
module wbureadcw(i_clk, i_stb, i_valid, i_hexbits,
|
| 42 |
|
|
o_stb, o_codword);
|
| 43 |
|
|
input i_clk, i_stb, i_valid;
|
| 44 |
|
|
input [5:0] i_hexbits;
|
| 45 |
|
|
output reg o_stb;
|
| 46 |
|
|
output reg [35:0] o_codword;
|
| 47 |
|
|
|
| 48 |
|
|
|
| 49 |
|
|
// Timing:
|
| 50 |
|
|
// Clock 0: i_stb is high, i_valid is low
|
| 51 |
|
|
// Clock 1: shiftreg[5:0] is valid, cw_len is valid
|
| 52 |
|
|
// r_len = 1
|
| 53 |
|
|
// Clock 2: o_stb = 1, for cw_len = 1;
|
| 54 |
|
|
// o_codword is 1-byte valid
|
| 55 |
|
|
// i_stb may go high again on this clock as well.
|
| 56 |
|
|
// Clock 3: o_stb = 0 (cw_len=1),
|
| 57 |
|
|
// cw_len = 0,
|
| 58 |
|
|
// r_len = 0 (unless i_stb)
|
| 59 |
|
|
// Ready for next word
|
| 60 |
|
|
|
| 61 |
|
|
reg [2:0] r_len, cw_len;
|
| 62 |
|
|
|
| 63 |
|
|
wire w_stb;
|
| 64 |
|
|
assign w_stb = ((r_len == cw_len)&&(cw_len != 0))
|
| 65 |
|
|
||((i_stb)&&(~i_valid)&&(lastcw == 2'b01));
|
| 66 |
|
|
|
| 67 |
|
|
// r_len is the length of the codeword as it exists
|
| 68 |
|
|
// in our register
|
| 69 |
|
|
initial r_len = 3'h0;
|
| 70 |
|
|
always @(posedge i_clk)
|
| 71 |
|
|
if ((i_stb)&&(~i_valid)) // Newline reset
|
| 72 |
|
|
r_len <= 0;
|
| 73 |
|
|
else if (w_stb) // reset/restart w/o newline
|
| 74 |
|
|
r_len <= (i_stb)? 3'h1:3'h0;
|
| 75 |
|
|
else if (i_stb) //in middle of word
|
| 76 |
|
|
r_len <= r_len + 3'h1;
|
| 77 |
|
|
|
| 78 |
|
|
reg [35:0] shiftreg;
|
| 79 |
|
|
always @(posedge i_clk)
|
| 80 |
|
|
if (w_stb)
|
| 81 |
|
|
shiftreg[35:30] <= i_hexbits;
|
| 82 |
|
|
else if (i_stb) case(r_len)
|
| 83 |
|
|
3'b000: shiftreg[35:30] <= i_hexbits;
|
| 84 |
|
|
3'b001: shiftreg[29:24] <= i_hexbits;
|
| 85 |
|
|
3'b010: shiftreg[23:18] <= i_hexbits;
|
| 86 |
|
|
3'b011: shiftreg[17:12] <= i_hexbits;
|
| 87 |
|
|
3'b100: shiftreg[11: 6] <= i_hexbits;
|
| 88 |
|
|
3'b101: shiftreg[ 5: 0] <= i_hexbits;
|
| 89 |
|
|
default: begin end
|
| 90 |
|
|
endcase
|
| 91 |
|
|
|
| 92 |
|
|
reg [1:0] lastcw;
|
| 93 |
|
|
always @(posedge i_clk)
|
| 94 |
|
|
if (o_stb)
|
| 95 |
|
|
lastcw <= o_codword[35:34];
|
| 96 |
|
|
always @(posedge i_clk)
|
| 97 |
|
|
if ((i_stb)&&(~i_valid)&&(lastcw == 2'b01))
|
| 98 |
|
|
o_codword[35:30] <= 6'h2e;
|
| 99 |
|
|
else
|
| 100 |
|
|
o_codword <= shiftreg;
|
| 101 |
|
|
|
| 102 |
|
|
// How long do we expect this codeword to be?
|
| 103 |
|
|
initial cw_len = 3'b000;
|
| 104 |
|
|
always @(posedge i_clk)
|
| 105 |
|
|
if ((i_stb)&&(~i_valid))
|
| 106 |
|
|
cw_len <= 0;
|
| 107 |
|
|
else if ((i_stb)&&((cw_len == 0)||(w_stb)))
|
| 108 |
|
|
begin
|
| 109 |
|
|
if (i_hexbits[5:4] == 2'b11) // 2b vector read
|
| 110 |
|
|
cw_len <= 3'h2;
|
| 111 |
|
|
else if (i_hexbits[5:4] == 2'b10) // 1b vector read
|
| 112 |
|
|
cw_len <= 3'h1;
|
| 113 |
|
|
else if (i_hexbits[5:3] == 3'b010) // 2b compressed wr
|
| 114 |
|
|
cw_len <= 3'h2;
|
| 115 |
|
|
else if (i_hexbits[5:3] == 3'b001) // 2b compressed addr
|
| 116 |
|
|
cw_len <= 3'b010 + { 1'b0, i_hexbits[2:1] };
|
| 117 |
|
|
else // long write or set address
|
| 118 |
|
|
cw_len <= 3'h6;
|
| 119 |
|
|
end else if (w_stb)
|
| 120 |
|
|
cw_len <= 0;
|
| 121 |
|
|
|
| 122 |
|
|
always @(posedge i_clk)
|
| 123 |
|
|
o_stb <= w_stb;
|
| 124 |
|
|
|
| 125 |
|
|
endmodule
|
| 126 |
|
|
|
