OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [sw/] [dumpsdram.cpp] - Blame information for rev 49

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    dumpsdram.cpp
4
//
5
// Project:     XuLA2 board
6
//
7
// Purpose:     Read local memory, dump into a file.
8
//
9
//
10
// Creator:     Dan Gisselquist, Ph.D.
11
//              Gisselquist Technology, LLC
12
//
13
////////////////////////////////////////////////////////////////////////////////
14
//
15
// Copyright (C) 2015, Gisselquist Technology, LLC
16
//
17
// This program is free software (firmware): you can redistribute it and/or
18
// modify it under the terms of  the GNU General Public License as published
19
// by the Free Software Foundation, either version 3 of the License, or (at
20
// your option) any later version.
21
//
22
// This program is distributed in the hope that it will be useful, but WITHOUT
23
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
24
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
25
// for more details.
26
//
27
// License:     GPL, v3, as defined and found on www.gnu.org,
28
//              http://www.gnu.org/licenses/gpl.html
29
//
30
//
31
////////////////////////////////////////////////////////////////////////////////
32
//
33
//
34
//
35
#include <stdio.h>
36
#include <stdlib.h>
37
#include <unistd.h>
38
#include <strings.h>
39
#include <ctype.h>
40
#include <string.h>
41
#include <signal.h>
42
#include <assert.h>
43
 
44 40 dgisselq
#include "llcomms.h"
45 5 dgisselq
#include "usbi.h"
46
#include "port.h"
47
#include "regdefs.h"
48
 
49
FPGA    *m_fpga;
50
 
51
int main(int argc, char **argv) {
52
        FILE            *fp, *fpin;
53
        unsigned        pos=0;
54 40 dgisselq
        int             port = FPGAPORT, skp;
55 5 dgisselq
        const int       BUFLN = 127;
56
        FPGA::BUSW      *buf = new FPGA::BUSW[BUFLN],
57
                        *cmp = new FPGA::BUSW[BUFLN];
58 40 dgisselq
        bool            use_usb = true;
59 5 dgisselq
 
60 40 dgisselq
        skp = 1;
61
        for(int argn=0; argn<argc-skp; argn++) {
62
                if (argv[argn+skp][0] == '-') {
63
                        if (argv[argn+skp][1] == 'u')
64
                                use_usb = true;
65
                        else if (argv[argn+skp][1] == 'p') {
66
                                use_usb = false;
67
                                if (isdigit(argv[argn+skp][2]))
68
                                        port = atoi(&argv[argn+skp][2]);
69
                        } skp++; argn--;
70
                } else
71
                        argv[argn] = argv[argn+skp];
72
        } argc -= skp;
73
 
74
        if (argc!=2) {
75
                printf("Usage: dumpsdram [-p [port]] srcfile outfile\n");
76 5 dgisselq
                exit(-1);
77
        }
78
 
79 46 dgisselq
        /*
80 40 dgisselq
        for(int i=0; i<argc; i++) {
81
                printf("ARG[%d] = %s\n", i, argv[i]);
82 46 dgisselq
        } */
83 5 dgisselq
 
84 40 dgisselq
        fpin = fopen(argv[0], "rb");
85 5 dgisselq
        if (fpin == NULL) {
86
                fprintf(stderr, "Could not open %s\n", argv[1]);
87
                exit(-1);
88
        }
89
 
90 40 dgisselq
        if (use_usb)
91
                m_fpga = new FPGA(new USBI());
92
        else
93
                m_fpga = new FPGA(new NETCOMMS(FPGAHOST, port));
94
 
95
 
96 5 dgisselq
        try {
97
                int     nr;
98
                pos = SDRAMBASE;
99
                do {
100
                        nr = BUFLN;
101
                        if (nr + pos > SDRAMBASE*2)
102
                                nr = SDRAMBASE*2 - pos;
103
                        nr = fread(buf, sizeof(FPGA::BUSW), nr, fpin);
104
                        if (nr <= 0)
105
                                break;
106 40 dgisselq
 
107 46 dgisselq
                        if (false) {
108
                                for(int i=0; i<nr; i++)
109
                                        m_fpga->writeio(pos+i, buf[i]);
110
                        } else
111
                                m_fpga->writei(pos, nr, buf);
112 5 dgisselq
                        pos += nr;
113
                } while((nr > 0)&&(pos < 2*SDRAMBASE));
114
 
115
                printf("SUCCESS::fully wrote full file to memory (pos = %08x)\n", pos);
116
        } catch(BUSERR a) {
117
                fprintf(stderr, "BUS Err while writing at address 0x%08x\n", a.addr);
118
                fprintf(stderr, "... is your program too long for this memory?\n");
119
                exit(-2);
120 40 dgisselq
        } catch(...) {
121
                fprintf(stderr, "Other error\n");
122
                exit(-3);
123 5 dgisselq
        }
124
 
125
        rewind(fpin);
126
 
127 40 dgisselq
        fp = fopen(argv[1], "wb");
128 5 dgisselq
        if (fp == NULL) {
129
                fprintf(stderr, "Could not open: %s\n", argv[2]);
130
                exit(-1);
131
        }
132
 
133 46 dgisselq
        unsigned        mmaddr[65536], mmval[65536], mmidx = 0;
134
 
135 5 dgisselq
        try {
136
                pos = SDRAMBASE;
137
                const unsigned int MAXRAM = SDRAMBASE*2;
138 46 dgisselq
                bool    mismatch = false;
139
                unsigned        total_reread = 0;
140 5 dgisselq
                do {
141
                        int nw, nr;
142
                        if (MAXRAM-pos > BUFLN)
143
                                nr = BUFLN;
144
                        else
145
                                nr = MAXRAM-pos;
146 46 dgisselq
 
147
                        if (false) {
148
                                for(int i=0; i<nr; i++)
149
                                        buf[i] = m_fpga->readio(pos+i);
150
                        } else
151
                                m_fpga->readi(pos, nr, buf);
152
 
153 5 dgisselq
                        pos += nr;
154
                        nw = fwrite(buf, sizeof(FPGA::BUSW), nr, fp);
155
                        if (nw < nr) {
156
                                printf("Only wrote %d of %d words!\n", nw, nr);
157
                                exit(-2);
158 46 dgisselq
                        } // printf("nr = %d, pos = %08x (%08x / %08x)\n", nr,
159
                        //      pos, SDRAMBASE, MAXRAM);
160 5 dgisselq
 
161
                        {int cr;
162
                        cr = fread(cmp, sizeof(FPGA::BUSW), nr, fpin);
163 46 dgisselq
                        total_reread += cr;
164 5 dgisselq
                        for(int i=0; i<cr; i++)
165 46 dgisselq
                                if (cmp[i] != buf[i]) {
166 40 dgisselq
                                        printf("MISMATCH: MEM[%08x] = %08x(read) != %08x(expected)\n",
167 5 dgisselq
                                                pos-nr+i, buf[i], cmp[i]);
168 46 dgisselq
                                        mmaddr[mmidx] = pos-nr+i;
169
                                        mmval[mmidx] = cmp[i];
170
                                        if (mmidx < 65536)
171
                                                mmidx++;
172
                                        mismatch = true;
173
                                }
174 5 dgisselq
                        if (cr != nr) {
175 46 dgisselq
                                printf("Only read %d words from our input file\n", total_reread);
176 5 dgisselq
                                break;
177
                        }
178
                        }
179
                } while(pos < MAXRAM);
180 46 dgisselq
                if (mismatch)
181
                        printf("Read %04x (%6d) words from memory.  These did not match the source file.  (Failed test)\n",
182 5 dgisselq
                                pos-SDRAMBASE, pos-SDRAMBASE);
183 46 dgisselq
                else
184
                        printf("Successfully  read&copied %04x (%6d) words from memory\n",
185
                                pos-SDRAMBASE, pos-SDRAMBASE);
186 5 dgisselq
        } catch(BUSERR a) {
187
                fprintf(stderr, "BUS Err at address 0x%08x\n", a.addr);
188
                fprintf(stderr, "... is your program too long for this memory?\n");
189
                exit(-2);
190 40 dgisselq
        } catch(...) {
191
                fprintf(stderr, "Other error\n");
192
                exit(-3);
193 5 dgisselq
        }
194
 
195 46 dgisselq
        for(unsigned i=0; i<mmidx; i++) {
196
                unsigned bv = m_fpga->readio(mmaddr[i]);
197
                if (bv == mmval[i])
198
                        printf("Re-match, MEM[%08x]\n", mmaddr[i]);
199
                else
200
                        printf("2ndary Fail: MEM[%08x] = %08x(read) != %08x(expected)\n",
201
                                mmaddr[i], bv, mmval[i]);
202
        }
203
 
204 5 dgisselq
        delete  m_fpga;
205
}
206
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.