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dgisselq |
#**********************************************************************
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# Copyright (c) 1997-2014 by XESS Corp .
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# All rights reserved.
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 3.0 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library. If not, see
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# .
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#**********************************************************************
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NET i_clk_12mhz LOC = A9; # 12 MHz clock input.
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##############################
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# SDRAM
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##############################
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NET o_ram_cke LOC = J12;
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NET o_ram_clk LOC = K11;
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NET i_ram_feedback_clk LOC = K12;
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NET o_ram_cs_n LOC = H4;
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NET o_ram_ras_n LOC = L4;
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NET o_ram_cas_n LOC = L3;
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NET o_ram_we_n LOC = M3;
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NET o_ram_ldqm LOC = M4;
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NET o_ram_udqm LOC = L13;
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NET o_ram_bs<0> LOC = H3;
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NET o_ram_bs<1> LOC = G3;
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NET o_ram_addr<0> LOC = E4;
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NET o_ram_addr<1> LOC = E3;
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NET o_ram_addr<2> LOC = D3;
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NET o_ram_addr<3> LOC = C3;
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NET o_ram_addr<4> LOC = B12;
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NET o_ram_addr<5> LOC = A12;
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NET o_ram_addr<6> LOC = D12;
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NET o_ram_addr<7> LOC = E12;
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NET o_ram_addr<8> LOC = G16;
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NET o_ram_addr<9> LOC = G12;
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NET o_ram_addr<10> LOC = F4;
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NET o_ram_addr<11> LOC = G11;
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NET o_ram_addr<12> LOC = H13;
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NET io_ram_data<0> LOC = P6;
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NET io_ram_data<1> LOC = T6;
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NET io_ram_data<2> LOC = T5;
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NET io_ram_data<3> LOC = P5;
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NET io_ram_data<4> LOC = R5;
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NET io_ram_data<5> LOC = N5;
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NET io_ram_data<6> LOC = P4;
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NET io_ram_data<7> LOC = N4;
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NET io_ram_data<8> LOC = P12;
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NET io_ram_data<9> LOC = R12;
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NET io_ram_data<10> LOC = T13;
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NET io_ram_data<11> LOC = T14;
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NET io_ram_data<12> LOC = R14;
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NET io_ram_data<13> LOC = T15;
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NET io_ram_data<14> LOC = T12;
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NET io_ram_data<15> LOC = P11;
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##############################
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# Flash
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##############################
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NET o_sd_cs_n LOC = T8;
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NET o_sf_cs_n LOC = T3;
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NET o_spi_sck LOC = R11;
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NET o_spi_mosi LOC = T10;
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NET i_spi_miso LOC = P10;
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##############################
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# Prototyping Header
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##############################
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# NET io_chan_clk LOC = T7; # L32N
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dgisselq |
NET i_rx_uart LOC = B15; # L32P
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NET i_gpio<0> LOC = R15; # L49P
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NET i_gpio<1> LOC = R16; # L49N
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NET i_gpio<2> LOC = M15; # L46P
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NET i_gpio<3> LOC = M16; # L46N
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NET i_gpio<4> LOC = K15; # L44P
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NET i_gpio<5> LOC = K16; # L44N
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NET i_gpio<6> LOC = J16; # L43N
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NET i_gpio<7> LOC = J14; # L43P
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NET i_gpio<8> LOC = F15; # L35P
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NET i_gpio<9> LOC = F16; # L35N
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NET i_gpio<10> LOC = C16; # L33N
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NET i_gpio<11> LOC = C15; # L33P
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NET i_gpio<12> LOC = R2; # L29N
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NET i_gpio<13> LOC = R7; # L29P
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NET o_pwm LOC = T4; # L63N (No differential pair!)
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NET o_tx_uart LOC = B16; # L32P
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NET o_gpio<0> LOC = R1; # L32N
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NET o_gpio<1> LOC = M2; # L35P
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NET o_gpio<2> LOC = M1; # L35N
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NET o_gpio<3> LOC = K3; # L42P
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NET o_gpio<4> LOC = J4; # L42N
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NET o_gpio<5> LOC = H1; # L39N
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NET o_gpio<6> LOC = H2; # L39P
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NET o_gpio<7> LOC = F1; # L41N
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NET o_gpio<8> LOC = F2; # L41P
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NET o_gpio<9> LOC = E1; # L46N
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NET o_gpio<10> LOC = E2; # L46P
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NET o_gpio<11> LOC = C1; # L50P
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NET o_gpio<12> LOC = B1; # L50N
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NET o_gpio<13> LOC = B2; # L52P
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NET o_gpio<14> LOC = A2; # L52N
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##############################
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# I/O Drive
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##############################
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NET i_clk_12mhz IOSTANDARD = LVTTL;
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NET o_ram_clk IOSTANDARD = LVTTL | SLEW=FAST | DRIVE=8;
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NET i_ram_feedback_clk IOSTANDARD = LVTTL;
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NET o_ram_cke IOSTANDARD = LVTTL;
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NET o_ram_cs_n IOSTANDARD = LVTTL;
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NET o_ram_addr* IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET o_ram_bs* IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET o_ram_ras_n IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET o_ram_cas_n IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET o_ram_we_n IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET io_ram_data* IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET o_ram_udqm IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET o_ram_ldqm IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
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NET o_sd_cs_n IOSTANDARD = LVTTL;
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NET o_sf_cs_n IOSTANDARD = LVTTL;
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NET o_spi_sck IOSTANDARD = LVTTL;
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NET o_spi_mosi IOSTANDARD = LVTTL;
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NET i_gpio* IOSTANDARD = LVTTL;
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NET o_gpio* IOSTANDARD = LVTTL;
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NET o_pwm IOSTANDARD = LVTTL;
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NET o_tx_uart IOSTANDARD = LVTTL;
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NET i_rx_uart IOSTANDARD = LVTTL;
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##############################
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# Clock Nets
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##############################
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NET "i_clk_12mhz" TNM_NET = "i_clk_12mhz";
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NET "i_ram_feedback_clk" TNM_NET = "i_ram_feedback_clk";
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dgisselq |
TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 82 ns HIGH 50%;
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# TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.333333 ns HIGH 50%;
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# TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 10.0 ns HIGH 50%;
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TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 11.3 ns HIGH 50%;
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