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/*******************************************************************************************/
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/** **/
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/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
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/** **/
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/** control module Rev 0.0 05/30/2012 **/
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/** **/
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/*******************************************************************************************/
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module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
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ex_bank_pls, ex_dehl_inst, halt_nxt, hflg_ctl, ief_ctl, if_frst, inta_frst,
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imd_ctl, ld_dmaa, ld_inst, ld_inta, ld_page, ld_wait, nflg_ctl, output_inh,
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page_sel, pc_sel, pflg_ctl, rd_frst, rd_nxt, reti_nxt, sflg_en, state_nxt,
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tflg_ctl, tran_sel, wr_addr, wr_frst, zflg_en, carry_bit, dmar_reg, inst_reg,
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intr_reg, page_reg, par_bit, sign_bit, state_reg, tflg_reg, vector_int,
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xhlt_reg, zero_bit);
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input carry_bit; /* carry flag */
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input dmar_reg; /* latched dma request */
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input intr_reg; /* latched interrupt request */
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input par_bit; /* parity flag */
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input sign_bit; /* sign flag */
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input tflg_reg; /* temporary flag */
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input vector_int; /* int vector enable */
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input xhlt_reg; /* halt exit */
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input zero_bit; /* zero flag */
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input [3:0] page_reg; /* instruction decode "page" */
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input [7:0] inst_reg; /* instruction register */
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input [`STATE_IDX:0] state_reg; /* current processor state */
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output cflg_en; /* carry flag control */
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output ex_af_pls; /* exchange af,af' */
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output ex_bank_pls; /* exchange register bank */
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output ex_dehl_inst; /* exchange de,hl */
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output halt_nxt; /* halt cycle next */
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output if_frst; /* ifetch first cycle */
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output inta_frst; /* intack first cycle */
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output ld_dmaa; /* load dma request */
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output ld_inst; /* load instruction register */
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output ld_inta; /* load interrupt request */
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output ld_page; /* load page register */
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output ld_wait; /* load wait request */
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output output_inh; /* disable cpu outputs */
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output rd_frst; /* read first cycle */
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output rd_nxt; /* read cycle identifier */
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output reti_nxt; /* reti identifier */
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output sflg_en; /* sign flag control */
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output wr_frst; /* write first cycle */
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output zflg_en; /* zero flag control */
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output [3:0] page_sel; /* instruction decode "page" control */
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output [`ADCTL_IDX:0] add_sel; /* address output mux control */
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output [`ALUA_IDX:0] alua_sel; /* alu input a mux control */
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output [`ALUB_IDX:0] alub_sel; /* alu input b mux control */
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output [`ALUOP_IDX:0] aluop_sel; /* alu operation control */
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output [`DI_IDX:0] di_ctl; /* data input control */
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output [`DO_IDX:0] do_ctl; /* data output control */
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output [`HFLG_IDX:0] hflg_ctl; /* half-carry flag control */
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output [`IEF_IDX:0] ief_ctl; /* interrupt enable control */
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output [`IMD_IDX:0] imd_ctl; /* interrupt mode control */
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output [`NFLG_IDX:0] nflg_ctl; /* negate flag control */
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output [`PCCTL_IDX:0] pc_sel; /* program counter source control */
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output [`PFLG_IDX:0] pflg_ctl; /* parity/overflow flag control */
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output [`STATE_IDX:0] state_nxt; /* next processor state */
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output [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
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output [`TTYPE_IDX:0] tran_sel; /* transaction type select */
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output [`WREG_IDX:0] wr_addr; /* register write address bus */
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/*****************************************************************************************/
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/* */
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/* signal declarations */
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/* */
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/*****************************************************************************************/
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reg cflg_en; /* carry flag control */
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reg ex_af_pls; /* exchange af,af' */
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reg ex_bank_pls; /* exchange register bank */
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reg ex_dehl_inst; /* exchange de,hl */
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reg halt_nxt; /* halt transaction */
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reg if_frst; /* first clock if ifetch */
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reg inta_frst; /* first clock of intack */
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reg ld_inst; /* load instruction register */
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reg ld_inta; /* sample latched int */
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reg ld_dmaa; /* sample latched dma */
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reg ld_page; /* load page register */
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reg ld_wait; /* sample wait input */
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reg output_inh; /* disable cpu outputs */
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reg rd_frst; /* first clock of read */
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reg rd_nxt; /* read trans next */
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reg reti_nxt; /* reti trans next */
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reg sflg_en; /* sign flag control */
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reg wr_frst; /* first clock of write */
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reg zflg_en; /* zero flag control */
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reg [3:0] page_sel; /* inst decode page control */
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reg [`ADCTL_IDX:0] add_sel; /* address output mux control */
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reg [`ALUA_IDX:0] alua_sel; /* alu input a mux control */
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reg [`ALUB_IDX:0] alub_sel; /* alu input b mux control */
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reg [`ALUOP_IDX:0] aluop_sel; /* alu operation control */
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reg [`DI_IDX:0] di_ctl; /* data input control */
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reg [`DO_IDX:0] do_ctl; /* data output control */
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reg [`HFLG_IDX:0] hflg_ctl; /* half-carry flag control */
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reg [`IEF_IDX:0] ief_ctl; /* interrupt enable control */
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reg [`IMD_IDX:0] imd_ctl; /* interrupt mode control */
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reg [`NFLG_IDX:0] nflg_ctl; /* negate flag control */
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reg [`PCCTL_IDX:0] pc_sel; /* pc source control */
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reg [`PFLG_IDX:0] pflg_ctl; /* parity/overflow flag control */
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reg [`STATE_IDX:0] state_nxt; /* machine state */
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reg [`TFLG_IDX:0] tflg_ctl; /* temp flag control */
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reg [`TTYPE_IDX:0] tran_sel; /* transaction type */
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reg [`WREG_IDX:0] wr_addr; /* register write address bus */
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/*****************************************************************************************/
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/* */
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/* exchange instruction control */
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/* */
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/*****************************************************************************************/
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg)
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`IF1B: begin
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case ({page_reg, inst_reg})
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12'b000000001000: ex_af_pls = 1'b1;
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default: ex_af_pls = 1'b0;
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endcase
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end
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default: ex_af_pls = 1'b0;
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endcase
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end
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg)
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`IF1B: begin
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case ({page_reg, inst_reg})
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12'b000011011001: ex_bank_pls = 1'b1;
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default: ex_bank_pls = 1'b0;
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endcase
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end
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default: ex_bank_pls = 1'b0;
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endcase
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end
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg)
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`DEC1: begin
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case (inst_reg)
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8'b11101011: ex_dehl_inst = 1'b1;
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default: ex_dehl_inst = 1'b0;
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endcase
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end
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default: ex_dehl_inst = 1'b0;
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endcase
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end
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/*****************************************************************************************/
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/* */
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/* interrupt control */
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/* */
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/*****************************************************************************************/
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg)
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`IF1B: begin
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casex ({page_reg, inst_reg})
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12'b000011110011: ief_ctl = `IEF_0;
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12'b000011111011: ief_ctl = `IEF_1;
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12'b0001xxxxxxxx: ief_ctl = `IEF_NMI;
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12'b1xxx01000101: ief_ctl = `IEF_RTN;
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default: ief_ctl = `IEF_NUL;
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endcase
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end
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default: ief_ctl = `IEF_NUL;
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endcase
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end
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg)
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`IF1B: begin
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casex ({page_reg, inst_reg})
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12'b1xxx01000110: imd_ctl = `IMD_0;
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12'b1xxx01010110: imd_ctl = `IMD_1;
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12'b1xxx01011110: imd_ctl = `IMD_2;
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default: imd_ctl = `IMD_NUL;
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endcase
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end
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default: imd_ctl = `IMD_NUL;
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endcase
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end
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/*****************************************************************************************/
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/* */
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/* identifiers to create timing signals */
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/* */
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/*****************************************************************************************/
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always @ (state_reg) begin
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casex (state_reg) //synopsys parallel_case
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`DEC1,
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`DEC2,
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`OF2A,
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`IF3A,
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`IF1A: if_frst = 1'b1;
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default: if_frst = 1'b0;
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endcase
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end
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always @ (state_reg) begin
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casex (state_reg) //synopsys parallel_case
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`INTA,
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`RSTE: inta_frst = 1'b1;
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default: inta_frst = 1'b0;
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endcase
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end
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always @ (inst_reg or page_reg or state_nxt) begin
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casex (state_nxt) //synopsys parallel_case
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`RD1A,
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`RD2A: rd_nxt = 1'b1;
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default: rd_nxt = 1'b0;
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endcase
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end
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg) //synopsys parallel_case
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`RD1A,
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`RD2A: rd_frst = 1'b1;
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default: rd_frst = 1'b0;
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endcase
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end
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always @ (state_reg) begin
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casex (state_reg) //synopsys parallel_case
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`WR1A,
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`WR2A: wr_frst = 1'b1;
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default: wr_frst = 1'b0;
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endcase
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end
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/*****************************************************************************************/
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/* */
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/* wait sample */
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/* */
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/*****************************************************************************************/
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always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or
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sign_bit or zero_bit) begin
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casex (state_reg) //synopsys parallel_case
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`DEC1: begin
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casex (inst_reg) //synopsys parallel_case
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8'b00000010,
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8'b00001010,
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8'b00010010,
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8'b00011010,
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8'b00110100,
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8'b00110101,
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8'b011100xx,
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8'b0111010x,
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8'b01110111,
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8'b010xx110,
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8'b0110x110,
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8'b01111110,
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8'b10000110,
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8'b10001110,
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8'b10010110,
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8'b10011110,
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8'b10100110,
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8'b10101110,
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8'b10110110,
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8'b10111110,
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8'b11001001,
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8'b11100011,
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8'b11xx0001,
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8'b11xx0101,
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8'b11xxx111,
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8'b01110110,
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8'b11101001: ld_wait = 1'b0;
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8'b11000000: ld_wait = zero_bit;
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8'b11001000: ld_wait = !zero_bit;
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8'b11010000: ld_wait = carry_bit;
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8'b11011000: ld_wait = !carry_bit;
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8'b11100000: ld_wait = par_bit;
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8'b11101000: ld_wait = !par_bit;
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8'b11110000: ld_wait = sign_bit;
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8'b11111000: ld_wait = !sign_bit;
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default: ld_wait = 1'b1;
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endcase
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end
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`DEC2: begin
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casex ({page_reg, inst_reg}) //synopsys parallel_case
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12'b0010xxxxx110,
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12'b010x11100001,
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12'b010x11100011,
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12'b010x11100101,
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12'b1xxx0100x101,
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12'b1xxx0110x111,
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12'b1xxx01xxx00x,
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12'b1xxx101xx0xx,
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12'b010x11101001: ld_wait = 1'b0;
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default: ld_wait = 1'b1;
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endcase
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end
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`OF2A,
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`IF3A,
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`RD1A,
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`RD2A,
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`WR1A,
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`WR2A,
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`IF1A,
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`INTA: ld_wait = 1'b1;
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default: ld_wait = 1'b0;
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endcase
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end
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/*****************************************************************************************/
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/* */
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307 |
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/* instruction register and page register control */
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308 |
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/* */
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309 |
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/*****************************************************************************************/
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310 |
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg) //synopsys parallel_case
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`IF2B,
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`IF3B,
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`IF1B: ld_inst = 1'b1;
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default: ld_inst = 1'b0;
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endcase
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end
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always @ (inst_reg or page_reg or state_reg) begin
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casex (state_reg)
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321 |
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`DEC1: begin
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322 |
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case (inst_reg)
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8'b11001011: page_sel = `CB_PAGE;
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8'b11011101: page_sel = `DD_PAGE;
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8'b11101101: page_sel = `ED_PAGE;
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|
|
8'b11111101: page_sel = `FD_PAGE;
|
327 |
|
|
default: page_sel = `MAIN_PG;
|
328 |
|
|
endcase
|
329 |
|
|
end
|
330 |
|
|
`DEC2: begin
|
331 |
|
|
casex ({page_reg, inst_reg})
|
332 |
|
|
12'bx10011001011: page_sel = `DDCB_PG;
|
333 |
|
|
12'bx10111001011: page_sel = `FDCB_PG;
|
334 |
|
|
default: page_sel = `MAIN_PG;
|
335 |
|
|
endcase
|
336 |
|
|
end
|
337 |
|
|
`INTA: page_sel = `INTR_PG;
|
338 |
|
|
`DMA1: page_sel = `DMA_PG;
|
339 |
|
|
default: page_sel = `MAIN_PG;
|
340 |
|
|
endcase
|
341 |
|
|
end
|
342 |
|
|
|
343 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
344 |
|
|
casex (state_reg) //synopsys parallel_case
|
345 |
|
|
`DEC1: ld_page = 1'b1;
|
346 |
|
|
`DEC2: begin
|
347 |
|
|
casex ({page_reg, inst_reg})
|
348 |
|
|
12'bx10x11001011: ld_page = 1'b1;
|
349 |
|
|
default: ld_page = 1'b0;
|
350 |
|
|
endcase
|
351 |
|
|
end
|
352 |
|
|
`INTA,
|
353 |
|
|
`DMA1: ld_page = 1'b1;
|
354 |
|
|
default: ld_page = 1'b0;
|
355 |
|
|
endcase
|
356 |
|
|
end
|
357 |
|
|
|
358 |
|
|
/*****************************************************************************************/
|
359 |
|
|
/* */
|
360 |
|
|
/* next state control */
|
361 |
|
|
/* */
|
362 |
|
|
/*****************************************************************************************/
|
363 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or dmar_reg or intr_reg or
|
364 |
|
|
par_bit or sign_bit or tflg_reg or vector_int or xhlt_reg or zero_bit) begin
|
365 |
|
|
casex (state_reg) //synopsys parallel_case
|
366 |
|
|
`DEC1: begin
|
367 |
|
|
casex (inst_reg) //synopsys parallel_case
|
368 |
|
|
8'b00000010,
|
369 |
|
|
8'b00001010,
|
370 |
|
|
8'b00010010,
|
371 |
|
|
8'b00011010,
|
372 |
|
|
8'b00110100,
|
373 |
|
|
8'b00110101,
|
374 |
|
|
8'b011100xx,
|
375 |
|
|
8'b0111010x,
|
376 |
|
|
8'b01110111,
|
377 |
|
|
8'b010xx110,
|
378 |
|
|
8'b0110x110,
|
379 |
|
|
8'b01111110,
|
380 |
|
|
8'b10000110,
|
381 |
|
|
8'b10001110,
|
382 |
|
|
8'b10010110,
|
383 |
|
|
8'b10011110,
|
384 |
|
|
8'b10100110,
|
385 |
|
|
8'b10101110,
|
386 |
|
|
8'b10110110,
|
387 |
|
|
8'b10111110,
|
388 |
|
|
8'b11001001,
|
389 |
|
|
8'b11100011,
|
390 |
|
|
8'b11xx0001,
|
391 |
|
|
8'b11xx0101,
|
392 |
|
|
8'b11xxx111: state_nxt = `sADR2;
|
393 |
|
|
8'b11000000: state_nxt = ( !zero_bit) ? `sADR2 : `sIF1B;
|
394 |
|
|
8'b11001000: state_nxt = ( zero_bit) ? `sADR2 : `sIF1B;
|
395 |
|
|
8'b11010000: state_nxt = (!carry_bit) ? `sADR2 : `sIF1B;
|
396 |
|
|
8'b11011000: state_nxt = ( carry_bit) ? `sADR2 : `sIF1B;
|
397 |
|
|
8'b11100000: state_nxt = ( !par_bit) ? `sADR2 : `sIF1B;
|
398 |
|
|
8'b11101000: state_nxt = ( par_bit) ? `sADR2 : `sIF1B;
|
399 |
|
|
8'b11110000: state_nxt = ( !sign_bit) ? `sADR2 : `sIF1B;
|
400 |
|
|
8'b11111000: state_nxt = ( sign_bit) ? `sADR2 : `sIF1B;
|
401 |
|
|
8'b11001011,
|
402 |
|
|
8'b11011101,
|
403 |
|
|
8'b11101101,
|
404 |
|
|
8'b11111101: state_nxt = `sIF2B;
|
405 |
|
|
8'b00010000,
|
406 |
|
|
8'b00011000,
|
407 |
|
|
8'b00100010,
|
408 |
|
|
8'b00101010,
|
409 |
|
|
8'b00110010,
|
410 |
|
|
8'b00111010,
|
411 |
|
|
8'b001xx000,
|
412 |
|
|
8'b00xx0001,
|
413 |
|
|
8'b00xxx110,
|
414 |
|
|
8'b11000011,
|
415 |
|
|
8'b11000110,
|
416 |
|
|
8'b11001101,
|
417 |
|
|
8'b11001110,
|
418 |
|
|
8'b11010011,
|
419 |
|
|
8'b11010110,
|
420 |
|
|
8'b11011011,
|
421 |
|
|
8'b11011110,
|
422 |
|
|
8'b11100110,
|
423 |
|
|
8'b11101110,
|
424 |
|
|
8'b11110110,
|
425 |
|
|
8'b11111110,
|
426 |
|
|
8'b11xxx010,
|
427 |
|
|
8'b11xxx100: state_nxt = `sOF1B;
|
428 |
|
|
8'b01110110,
|
429 |
|
|
8'b11101001: state_nxt = `sPCO;
|
430 |
|
|
default: state_nxt = `sIF1B;
|
431 |
|
|
endcase
|
432 |
|
|
end
|
433 |
|
|
`IF2B: state_nxt = `sDEC2;
|
434 |
|
|
`DEC2: begin
|
435 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
436 |
|
|
12'b001000000110,
|
437 |
|
|
12'b001000001110,
|
438 |
|
|
12'b001000010110,
|
439 |
|
|
12'b001000011110,
|
440 |
|
|
12'b001000100110,
|
441 |
|
|
12'b001000101110,
|
442 |
|
|
12'b001000111110,
|
443 |
|
|
12'b001001xxx110,
|
444 |
|
|
12'b001010xxx110,
|
445 |
|
|
12'b001011xxx110,
|
446 |
|
|
12'b010011100001,
|
447 |
|
|
12'b010011100011,
|
448 |
|
|
12'b010011100101,
|
449 |
|
|
12'b010111100001,
|
450 |
|
|
12'b010111100011,
|
451 |
|
|
12'b010111100101,
|
452 |
|
|
12'b1xxx01000101,
|
453 |
|
|
12'b1xxx01001101,
|
454 |
|
|
12'b1xxx01100111,
|
455 |
|
|
12'b1xxx01101111,
|
456 |
|
|
12'b1xxx01xxx000,
|
457 |
|
|
12'b1xxx01xxx001,
|
458 |
|
|
12'b1xxx10100000,
|
459 |
|
|
12'b1xxx10100001,
|
460 |
|
|
12'b1xxx10100010,
|
461 |
|
|
12'b1xxx10100011,
|
462 |
|
|
12'b1xxx10101000,
|
463 |
|
|
12'b1xxx10101001,
|
464 |
|
|
12'b1xxx10101010,
|
465 |
|
|
12'b1xxx10101011,
|
466 |
|
|
12'b1xxx10110000,
|
467 |
|
|
12'b1xxx10110001,
|
468 |
|
|
12'b1xxx10110010,
|
469 |
|
|
12'b1xxx10110011,
|
470 |
|
|
12'b1xxx10111000,
|
471 |
|
|
12'b1xxx10111001,
|
472 |
|
|
12'b1xxx10111010,
|
473 |
|
|
12'b1xxx10111011: state_nxt = `sADR2;
|
474 |
|
|
12'b001000000xxx,
|
475 |
|
|
12'b001000001xxx,
|
476 |
|
|
12'b001000010xxx,
|
477 |
|
|
12'b001000011xxx,
|
478 |
|
|
12'b001000100xxx,
|
479 |
|
|
12'b001000101xxx,
|
480 |
|
|
12'b001000111xxx,
|
481 |
|
|
12'b001001xxxxxx,
|
482 |
|
|
12'b001010xxxxxx,
|
483 |
|
|
12'b001011xxxxxx,
|
484 |
|
|
12'b010000100011,
|
485 |
|
|
12'b010000101011,
|
486 |
|
|
12'b010000xx1001,
|
487 |
|
|
12'b010011111001,
|
488 |
|
|
12'b010100100011,
|
489 |
|
|
12'b010100101011,
|
490 |
|
|
12'b010100xx1001,
|
491 |
|
|
12'b010111111001,
|
492 |
|
|
12'b1xxx01000100,
|
493 |
|
|
12'b1xxx01000110,
|
494 |
|
|
12'b1xxx01000111,
|
495 |
|
|
12'b1xxx01001111,
|
496 |
|
|
12'b1xxx01010110,
|
497 |
|
|
12'b1xxx01010111,
|
498 |
|
|
12'b1xxx01011110,
|
499 |
|
|
12'b1xxx01011111,
|
500 |
|
|
12'b1xxx01xx0010,
|
501 |
|
|
12'b1xxx01xx1010: state_nxt = `sIF1B;
|
502 |
|
|
12'b010011101001,
|
503 |
|
|
12'b010111101001: state_nxt = `sPCO;
|
504 |
|
|
default: state_nxt = `sOF1B;
|
505 |
|
|
endcase
|
506 |
|
|
end
|
507 |
|
|
`OF1B: begin
|
508 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
509 |
|
|
12'b000011010011,
|
510 |
|
|
12'b000011011011,
|
511 |
|
|
12'b010000110100,
|
512 |
|
|
12'b010000110101,
|
513 |
|
|
12'b010001110xxx,
|
514 |
|
|
12'b010001xxx110,
|
515 |
|
|
12'b010010000110,
|
516 |
|
|
12'b010010001110,
|
517 |
|
|
12'b010010010110,
|
518 |
|
|
12'b010010011110,
|
519 |
|
|
12'b010010100110,
|
520 |
|
|
12'b010010101110,
|
521 |
|
|
12'b010010110110,
|
522 |
|
|
12'b010010111110,
|
523 |
|
|
12'b010100110100,
|
524 |
|
|
12'b010100110101,
|
525 |
|
|
12'b010101110xxx,
|
526 |
|
|
12'b010101xxx110,
|
527 |
|
|
12'b010110000110,
|
528 |
|
|
12'b010110001110,
|
529 |
|
|
12'b010110010110,
|
530 |
|
|
12'b010110011110,
|
531 |
|
|
12'b010110100110,
|
532 |
|
|
12'b010110101110,
|
533 |
|
|
12'b010110110110,
|
534 |
|
|
12'b010110111110: state_nxt = `sADR1;
|
535 |
|
|
12'b0000000xx110,12'b00000010x110,12'b000000111110,//12'b000000rrr110,
|
536 |
|
|
12'b000011000110,
|
537 |
|
|
12'b000011001110,
|
538 |
|
|
12'b000011010110,
|
539 |
|
|
12'b000011011110,
|
540 |
|
|
12'b000011100110,
|
541 |
|
|
12'b000011101110,
|
542 |
|
|
12'b000011110110,
|
543 |
|
|
12'b000011111110: state_nxt = `sIF1A;
|
544 |
|
|
12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
|
545 |
|
|
12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
|
546 |
|
|
12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
|
547 |
|
|
12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
|
548 |
|
|
12'b000000100010,
|
549 |
|
|
12'b000000101010,
|
550 |
|
|
12'b000000110010,
|
551 |
|
|
12'b000000111010,
|
552 |
|
|
12'b000000xx0001,
|
553 |
|
|
12'b000011000011,
|
554 |
|
|
12'b000011001101,
|
555 |
|
|
12'b000011xxx010,
|
556 |
|
|
12'b000011xxx100,
|
557 |
|
|
12'b010000100001,
|
558 |
|
|
12'b010000100010,
|
559 |
|
|
12'b010000101010,
|
560 |
|
|
12'b010000110110,
|
561 |
|
|
12'b010100100001,
|
562 |
|
|
12'b010100100010,
|
563 |
|
|
12'b010100101010,
|
564 |
|
|
12'b010100110110,
|
565 |
|
|
12'b1xxx01xx0011,
|
566 |
|
|
12'b1xxx01xx1011: state_nxt = `sOF2A;
|
567 |
|
|
12'b000000010000,
|
568 |
|
|
12'b000000011000: state_nxt = `sPCA;
|
569 |
|
|
12'b000000110110: state_nxt = `sWR2A;
|
570 |
|
|
default: state_nxt = `sIF3A;
|
571 |
|
|
endcase
|
572 |
|
|
end
|
573 |
|
|
`OF2A: state_nxt = `sOF2B;
|
574 |
|
|
`OF2B: begin
|
575 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
576 |
|
|
12'b000000xx0001,
|
577 |
|
|
12'b010000100001,
|
578 |
|
|
12'b010100100001: state_nxt = `sIF1A;
|
579 |
|
|
12'b000011000010: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
|
580 |
|
|
12'b000011001010: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
|
581 |
|
|
12'b000011010010: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
|
582 |
|
|
12'b000011011010: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
|
583 |
|
|
12'b000011100010: state_nxt = ( !par_bit) ? `sPCA : `sIF1A;
|
584 |
|
|
12'b000011101010: state_nxt = ( par_bit) ? `sPCA : `sIF1A;
|
585 |
|
|
12'b000011110010: state_nxt = ( !sign_bit) ? `sPCA : `sIF1A;
|
586 |
|
|
12'b000011111010: state_nxt = ( sign_bit) ? `sPCA : `sIF1A;
|
587 |
|
|
12'b000011000100: state_nxt = ( !zero_bit) ? `sWR1A : `sIF1A;
|
588 |
|
|
12'b000011001100: state_nxt = ( zero_bit) ? `sWR1A : `sIF1A;
|
589 |
|
|
12'b000011010100: state_nxt = (!carry_bit) ? `sWR1A : `sIF1A;
|
590 |
|
|
12'b000011011100: state_nxt = ( carry_bit) ? `sWR1A : `sIF1A;
|
591 |
|
|
12'b000011100100: state_nxt = ( !par_bit) ? `sWR1A : `sIF1A;
|
592 |
|
|
12'b000011101100: state_nxt = ( par_bit) ? `sWR1A : `sIF1A;
|
593 |
|
|
12'b000011110100: state_nxt = ( !sign_bit) ? `sWR1A : `sIF1A;
|
594 |
|
|
12'b000011111100: state_nxt = ( sign_bit) ? `sWR1A : `sIF1A;
|
595 |
|
|
12'b000011000011: state_nxt = `sPCA;
|
596 |
|
|
12'b000011001101: state_nxt = `sWR1A;
|
597 |
|
|
12'b010000110110,
|
598 |
|
|
12'b010100110110: state_nxt = `sWR2A;
|
599 |
|
|
default: state_nxt = `sADR1;
|
600 |
|
|
endcase
|
601 |
|
|
end
|
602 |
|
|
`IF3A: state_nxt = `sIF3B;
|
603 |
|
|
`IF3B: state_nxt = `sRD2A;
|
604 |
|
|
`ADR1: state_nxt = `sADR2;
|
605 |
|
|
`ADR2: begin
|
606 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
607 |
|
|
12'b000000101010,
|
608 |
|
|
12'b000011001001,
|
609 |
|
|
12'b000011100011,
|
610 |
|
|
12'b000011xxx000,
|
611 |
|
|
12'b000011xx0001,
|
612 |
|
|
12'b0001xxxxxxxx,
|
613 |
|
|
12'b010000101010,
|
614 |
|
|
12'b010011100001,
|
615 |
|
|
12'b010011100011,
|
616 |
|
|
12'b010100101010,
|
617 |
|
|
12'b010111100001,
|
618 |
|
|
12'b010111100011,
|
619 |
|
|
12'b1xxx01000101,
|
620 |
|
|
12'b1xxx01001101,
|
621 |
|
|
12'b1xxx01xx1011,
|
622 |
|
|
12'b1xxx10100000,
|
623 |
|
|
12'b1xxx10100001,
|
624 |
|
|
12'b1xxx10100010,
|
625 |
|
|
12'b1xxx10100011,
|
626 |
|
|
12'b1xxx10101000,
|
627 |
|
|
12'b1xxx10101001,
|
628 |
|
|
12'b1xxx10101010,
|
629 |
|
|
12'b1xxx10101011,
|
630 |
|
|
12'b1xxx10110000,
|
631 |
|
|
12'b1xxx10110001,
|
632 |
|
|
12'b1xxx10110010,
|
633 |
|
|
12'b1xxx10110011,
|
634 |
|
|
12'b1xxx10111000,
|
635 |
|
|
12'b1xxx10111001,
|
636 |
|
|
12'b1xxx10111010,
|
637 |
|
|
12'b1xxx10111011: state_nxt = `sRD1A;
|
638 |
|
|
12'b000000100010,
|
639 |
|
|
12'b000011xxx111,
|
640 |
|
|
12'b000011xx0101,
|
641 |
|
|
12'b010000100010,
|
642 |
|
|
12'b010011100101,
|
643 |
|
|
12'b010100100010,
|
644 |
|
|
12'b010111100101,
|
645 |
|
|
12'b1xxx01xx0011: state_nxt = `sWR1A;
|
646 |
|
|
12'b000000000010,
|
647 |
|
|
12'b000000010010,
|
648 |
|
|
12'b000000110010,
|
649 |
|
|
12'b000001110xxx,
|
650 |
|
|
12'b000011010011,
|
651 |
|
|
12'b010001110xxx,
|
652 |
|
|
12'b010101110xxx,
|
653 |
|
|
12'b1xxx01xxx001: state_nxt = `sWR2A;
|
654 |
|
|
default: state_nxt = `sRD2A;
|
655 |
|
|
endcase
|
656 |
|
|
end
|
657 |
|
|
`RD1A: state_nxt = `sRD1B;
|
658 |
|
|
`RD1B: begin
|
659 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
660 |
|
|
12'b1xxx10100001,
|
661 |
|
|
12'b1xxx10101001,
|
662 |
|
|
12'b1xxx10110001,
|
663 |
|
|
12'b1xxx10111001: state_nxt = `sBLK1;
|
664 |
|
|
12'b1xxx10100000,
|
665 |
|
|
12'b1xxx10100010,
|
666 |
|
|
12'b1xxx10100011,
|
667 |
|
|
12'b1xxx10101000,
|
668 |
|
|
12'b1xxx10101010,
|
669 |
|
|
12'b1xxx10101011,
|
670 |
|
|
12'b1xxx10110000,
|
671 |
|
|
12'b1xxx10110010,
|
672 |
|
|
12'b1xxx10110011,
|
673 |
|
|
12'b1xxx10111000,
|
674 |
|
|
12'b1xxx10111010,
|
675 |
|
|
12'b1xxx10111011: state_nxt = `sWR1A;
|
676 |
|
|
default: state_nxt = `sRD2A;
|
677 |
|
|
endcase
|
678 |
|
|
end
|
679 |
|
|
`RD2A: state_nxt = `sRD2B;
|
680 |
|
|
`RD2B: begin
|
681 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
682 |
|
|
12'b1xxx10100001,
|
683 |
|
|
12'b1xxx10101001,
|
684 |
|
|
12'b1xxx10110001,
|
685 |
|
|
12'b1xxx10111001: state_nxt = `sBLK1;
|
686 |
|
|
12'b000000001010,
|
687 |
|
|
12'b000000011010,
|
688 |
|
|
12'b000000101010,
|
689 |
|
|
12'b000000111010,
|
690 |
|
|
12'b000001xxxxxx,
|
691 |
|
|
12'b000001xxx110,
|
692 |
|
|
12'b000010000110,
|
693 |
|
|
12'b000010000xxx,
|
694 |
|
|
12'b000010001110,
|
695 |
|
|
12'b000010001xxx,
|
696 |
|
|
12'b000010010110,
|
697 |
|
|
12'b000010011110,
|
698 |
|
|
12'b000010100110,
|
699 |
|
|
12'b000010100xxx,
|
700 |
|
|
12'b000010101110,
|
701 |
|
|
12'b000010110110,
|
702 |
|
|
12'b000010110xxx,
|
703 |
|
|
12'b000010111110,
|
704 |
|
|
12'b000010111xxx,
|
705 |
|
|
12'b000011011011,
|
706 |
|
|
12'b000011xx0001,
|
707 |
|
|
12'b001001xxx110,
|
708 |
|
|
12'b001001xxxxxx,
|
709 |
|
|
12'b010000101010,
|
710 |
|
|
12'b010001xxx110,
|
711 |
|
|
12'b010010000110,
|
712 |
|
|
12'b010010001110,
|
713 |
|
|
12'b010010010110,
|
714 |
|
|
12'b010010011110,
|
715 |
|
|
12'b010010100110,
|
716 |
|
|
12'b010010101110,
|
717 |
|
|
12'b010010110110,
|
718 |
|
|
12'b010010111110,
|
719 |
|
|
12'b010011100001,
|
720 |
|
|
12'b010100101010,
|
721 |
|
|
12'b010101xxx110,
|
722 |
|
|
12'b010110000110,
|
723 |
|
|
12'b010110001110,
|
724 |
|
|
12'b010110010110,
|
725 |
|
|
12'b010110011110,
|
726 |
|
|
12'b010110100110,
|
727 |
|
|
12'b010110101110,
|
728 |
|
|
12'b010110110110,
|
729 |
|
|
12'b010110111110,
|
730 |
|
|
12'b010111100001,
|
731 |
|
|
12'b011001xxx110,
|
732 |
|
|
12'b011101xxx110,
|
733 |
|
|
12'b1xxx01xxx000,
|
734 |
|
|
12'b1xxx01xx1011: state_nxt = `sIF1A;
|
735 |
|
|
12'b000011001001,
|
736 |
|
|
12'b000011xxx000,
|
737 |
|
|
12'b1xxx01000101,
|
738 |
|
|
12'b1xxx01001101: state_nxt = `sPCA;
|
739 |
|
|
12'b000011100011,
|
740 |
|
|
12'b0001xxxxxxxx,
|
741 |
|
|
12'b010011100011,
|
742 |
|
|
12'b010111100011: state_nxt = `sWR1A;
|
743 |
|
|
default: state_nxt = `sWR2A;
|
744 |
|
|
endcase
|
745 |
|
|
end
|
746 |
|
|
`WR1A: state_nxt = `sWR1B;
|
747 |
|
|
`WR1B: begin
|
748 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
749 |
|
|
12'b1xxx10100000,
|
750 |
|
|
12'b1xxx10100010,
|
751 |
|
|
12'b1xxx10100011,
|
752 |
|
|
12'b1xxx10101000,
|
753 |
|
|
12'b1xxx10101010,
|
754 |
|
|
12'b1xxx10101011: state_nxt = `sIF1A;
|
755 |
|
|
12'b1xxx10110010,
|
756 |
|
|
12'b1xxx10111010,
|
757 |
|
|
12'b1xxx10110011,
|
758 |
|
|
12'b1xxx10111011,
|
759 |
|
|
12'b1xxx10110000,
|
760 |
|
|
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
|
761 |
|
|
default: state_nxt = `sWR2A;
|
762 |
|
|
endcase
|
763 |
|
|
end
|
764 |
|
|
`WR2A: state_nxt = `sWR2B;
|
765 |
|
|
`WR2B: begin
|
766 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
767 |
|
|
12'b1xxx10110010,
|
768 |
|
|
12'b1xxx10111010,
|
769 |
|
|
12'b1xxx10110011,
|
770 |
|
|
12'b1xxx10111011,
|
771 |
|
|
12'b1xxx10110000,
|
772 |
|
|
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
|
773 |
|
|
default: state_nxt = `sIF1A;
|
774 |
|
|
endcase
|
775 |
|
|
end
|
776 |
|
|
`BLK1: state_nxt = `sBLK2;
|
777 |
|
|
`BLK2: begin
|
778 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
779 |
|
|
12'b1xxx10110001,
|
780 |
|
|
12'b1xxx10111001: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
|
781 |
|
|
default: state_nxt = `sIF1A;
|
782 |
|
|
endcase
|
783 |
|
|
end
|
784 |
|
|
`PCA: state_nxt = `sPCO;
|
785 |
|
|
`PCO: begin
|
786 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
787 |
|
|
12'b000001110110: state_nxt = `sHLTA;
|
788 |
|
|
default: state_nxt = `sIF1A;
|
789 |
|
|
endcase
|
790 |
|
|
end
|
791 |
|
|
`HLTA: state_nxt = `sHLTB;
|
792 |
|
|
`HLTB: state_nxt = (xhlt_reg) ? `sIF1A : `sHLTA;
|
793 |
|
|
`IF1A: state_nxt = `sIF1B;
|
794 |
|
|
`IF1B: state_nxt = `sDEC1;
|
795 |
|
|
`INTA: state_nxt = `sINTB;
|
796 |
|
|
`INTB: state_nxt = (vector_int) ? `sADR1 : `sWR1A;
|
797 |
|
|
`DMA1: state_nxt = `sDMA2;
|
798 |
|
|
`DMA2: state_nxt = (dmar_reg) ? `sDMA1 : `sIF1A;
|
799 |
|
|
`RSTE: state_nxt = `sIF1A;
|
800 |
|
|
default: state_nxt = `sRSTE;
|
801 |
|
|
endcase
|
802 |
|
|
end
|
803 |
|
|
|
804 |
|
|
/*****************************************************************************************/
|
805 |
|
|
/* */
|
806 |
|
|
/* transaction type control */
|
807 |
|
|
/* */
|
808 |
|
|
/*****************************************************************************************/
|
809 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or dmar_reg or intr_reg or
|
810 |
|
|
par_bit or sign_bit or tflg_reg or vector_int or xhlt_reg or zero_bit) begin
|
811 |
|
|
casex (state_reg) //synopsys parallel_case
|
812 |
|
|
`IF2B: tran_sel = `TRAN_IF;
|
813 |
|
|
`OF1B: begin
|
814 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
815 |
|
|
12'b000000010000,
|
816 |
|
|
12'b000000011000,
|
817 |
|
|
12'b000011010011,
|
818 |
|
|
12'b000011011011,
|
819 |
|
|
12'b010x00110100,
|
820 |
|
|
12'b010x00110101,
|
821 |
|
|
12'b010x011100xx,
|
822 |
|
|
12'b010x0111010x,
|
823 |
|
|
12'b010x01110111,
|
824 |
|
|
12'b010x010xx110,
|
825 |
|
|
12'b010x0110x110,
|
826 |
|
|
12'b010x01111110,
|
827 |
|
|
12'b010x10000110,
|
828 |
|
|
12'b010x10001110,
|
829 |
|
|
12'b010x10010110,
|
830 |
|
|
12'b010x10011110,
|
831 |
|
|
12'b010x10100110,
|
832 |
|
|
12'b010x10101110,
|
833 |
|
|
12'b010x10110110,
|
834 |
|
|
12'b010x10111110: tran_sel = `TRAN_IDL;
|
835 |
|
|
12'b000000100000: tran_sel = ( zero_bit) ? `TRAN_IF : `TRAN_IDL;
|
836 |
|
|
12'b000000101000: tran_sel = ( !zero_bit) ? `TRAN_IF : `TRAN_IDL;
|
837 |
|
|
12'b000000110000: tran_sel = ( carry_bit) ? `TRAN_IF : `TRAN_IDL;
|
838 |
|
|
12'b000000111000: tran_sel = (!carry_bit) ? `TRAN_IF : `TRAN_IDL;
|
839 |
|
|
12'b000000110110: tran_sel = `TRAN_MEM;
|
840 |
|
|
default: tran_sel = `TRAN_IF;
|
841 |
|
|
endcase
|
842 |
|
|
end
|
843 |
|
|
`OF2B: begin
|
844 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
845 |
|
|
12'b000000xx0001,
|
846 |
|
|
12'b010000100001,
|
847 |
|
|
12'b010100100001: tran_sel = `TRAN_IF;
|
848 |
|
|
12'b010000110110,
|
849 |
|
|
12'b010100110110: tran_sel = `TRAN_MEM;
|
850 |
|
|
12'b000011001101: tran_sel = `TRAN_STK;
|
851 |
|
|
12'b000011000010: tran_sel = ( !zero_bit) ? `TRAN_IDL : `TRAN_IF;
|
852 |
|
|
12'b000011001010: tran_sel = ( zero_bit) ? `TRAN_IDL : `TRAN_IF;
|
853 |
|
|
12'b000011010010: tran_sel = (!carry_bit) ? `TRAN_IDL : `TRAN_IF;
|
854 |
|
|
12'b000011011010: tran_sel = ( carry_bit) ? `TRAN_IDL : `TRAN_IF;
|
855 |
|
|
12'b000011100010: tran_sel = ( !par_bit) ? `TRAN_IDL : `TRAN_IF;
|
856 |
|
|
12'b000011101010: tran_sel = ( par_bit) ? `TRAN_IDL : `TRAN_IF;
|
857 |
|
|
12'b000011110010: tran_sel = ( !sign_bit) ? `TRAN_IDL : `TRAN_IF;
|
858 |
|
|
12'b000011111010: tran_sel = ( sign_bit) ? `TRAN_IDL : `TRAN_IF;
|
859 |
|
|
12'b000011000100: tran_sel = ( !zero_bit) ? `TRAN_STK : `TRAN_IF;
|
860 |
|
|
12'b000011001100: tran_sel = ( zero_bit) ? `TRAN_STK : `TRAN_IF;
|
861 |
|
|
12'b000011010100: tran_sel = (!carry_bit) ? `TRAN_STK : `TRAN_IF;
|
862 |
|
|
12'b000011011100: tran_sel = ( carry_bit) ? `TRAN_STK : `TRAN_IF;
|
863 |
|
|
12'b000011100100: tran_sel = ( !par_bit) ? `TRAN_STK : `TRAN_IF;
|
864 |
|
|
12'b000011101100: tran_sel = ( par_bit) ? `TRAN_STK : `TRAN_IF;
|
865 |
|
|
12'b000011110100: tran_sel = ( !sign_bit) ? `TRAN_STK : `TRAN_IF;
|
866 |
|
|
12'b000011111100: tran_sel = ( sign_bit) ? `TRAN_STK : `TRAN_IF;
|
867 |
|
|
default: tran_sel = `TRAN_IDL;
|
868 |
|
|
endcase
|
869 |
|
|
end
|
870 |
|
|
`IF3B: tran_sel = `TRAN_MEM;
|
871 |
|
|
`ADR2: begin
|
872 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
873 |
|
|
12'b000011010011,
|
874 |
|
|
12'b000011011011,
|
875 |
|
|
12'b1xxx01xxx000,
|
876 |
|
|
12'b1xxx01xxx001,
|
877 |
|
|
12'b1xxx10100010,
|
878 |
|
|
12'b1xxx10101010,
|
879 |
|
|
12'b1xxx10110010,
|
880 |
|
|
12'b1xxx10111010: tran_sel = `TRAN_IO;
|
881 |
|
|
12'b000011001001,
|
882 |
|
|
12'b000011xxx000,
|
883 |
|
|
12'b000011xxx111,
|
884 |
|
|
12'b000011xx0001,
|
885 |
|
|
12'b000011xx0101,
|
886 |
|
|
12'b010011100001,
|
887 |
|
|
12'b010011100101,
|
888 |
|
|
12'b010111100001,
|
889 |
|
|
12'b010111100101,
|
890 |
|
|
12'b1xxx01000101,
|
891 |
|
|
12'b1xxx01001101: tran_sel = `TRAN_STK;
|
892 |
|
|
default: tran_sel = `TRAN_MEM;
|
893 |
|
|
endcase
|
894 |
|
|
end
|
895 |
|
|
`RD1B: begin
|
896 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
897 |
|
|
12'b1xxx10100001,
|
898 |
|
|
12'b1xxx10101001,
|
899 |
|
|
12'b1xxx10110001,
|
900 |
|
|
12'b1xxx10111001: tran_sel = `TRAN_IDL;
|
901 |
|
|
12'b1xxx10100011,
|
902 |
|
|
12'b1xxx10101011,
|
903 |
|
|
12'b1xxx10110011,
|
904 |
|
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
905 |
|
|
12'b000011001001,
|
906 |
|
|
12'b000011xxx000,
|
907 |
|
|
12'b000011xx0001,
|
908 |
|
|
12'b010011100001,
|
909 |
|
|
12'b010111100001,
|
910 |
|
|
12'b1xxx01000101,
|
911 |
|
|
12'b1xxx01001101: tran_sel = `TRAN_STK;
|
912 |
|
|
default: tran_sel = `TRAN_MEM;
|
913 |
|
|
endcase
|
914 |
|
|
end
|
915 |
|
|
`RD2B: begin
|
916 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
917 |
|
|
12'b000011001001,
|
918 |
|
|
12'b000011xxx000,
|
919 |
|
|
12'b1xxx01000101,
|
920 |
|
|
12'b1xxx01001101,
|
921 |
|
|
12'b1xxx10100001,
|
922 |
|
|
12'b1xxx10101001,
|
923 |
|
|
12'b1xxx10110001,
|
924 |
|
|
12'b1xxx10111001: tran_sel = `TRAN_IDL;
|
925 |
|
|
12'b000000001010,
|
926 |
|
|
12'b000000011010,
|
927 |
|
|
12'b000000101010,
|
928 |
|
|
12'b000000111010,
|
929 |
|
|
12'b000001xxx110,
|
930 |
|
|
12'b000010000110,
|
931 |
|
|
12'b000010001110,
|
932 |
|
|
12'b000010010110,
|
933 |
|
|
12'b000010011110,
|
934 |
|
|
12'b000010100110,
|
935 |
|
|
12'b000010101110,
|
936 |
|
|
12'b000010110110,
|
937 |
|
|
12'b000010111110,
|
938 |
|
|
12'b000011011011,
|
939 |
|
|
12'b000011xx0001,
|
940 |
|
|
12'b001001xxx110,
|
941 |
|
|
12'b010000101010,
|
942 |
|
|
12'b010001xxx110,
|
943 |
|
|
12'b010010000110,
|
944 |
|
|
12'b010010001110,
|
945 |
|
|
12'b010010010110,
|
946 |
|
|
12'b010010011110,
|
947 |
|
|
12'b010010100110,
|
948 |
|
|
12'b010010101110,
|
949 |
|
|
12'b010010110110,
|
950 |
|
|
12'b010010111110,
|
951 |
|
|
12'b010011100001,
|
952 |
|
|
12'b010100101010,
|
953 |
|
|
12'b010101xxx110,
|
954 |
|
|
12'b010110000110,
|
955 |
|
|
12'b010110001110,
|
956 |
|
|
12'b010110010110,
|
957 |
|
|
12'b010110011110,
|
958 |
|
|
12'b010110100110,
|
959 |
|
|
12'b010110101110,
|
960 |
|
|
12'b010110110110,
|
961 |
|
|
12'b010110111110,
|
962 |
|
|
12'b010111100001,
|
963 |
|
|
12'b011001xxx110,
|
964 |
|
|
12'b011101xxx110,
|
965 |
|
|
12'b1xxx01xxx000,
|
966 |
|
|
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
|
967 |
|
|
12'b1xxx10100011,
|
968 |
|
|
12'b1xxx10101011,
|
969 |
|
|
12'b1xxx10110011,
|
970 |
|
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
971 |
|
|
12'b000011100011,
|
972 |
|
|
12'b0001xxxxxxxx,
|
973 |
|
|
12'b010011100011,
|
974 |
|
|
12'b010111100011: tran_sel = `TRAN_STK;
|
975 |
|
|
default: tran_sel = `TRAN_MEM;
|
976 |
|
|
endcase
|
977 |
|
|
end
|
978 |
|
|
`WR1B: begin
|
979 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
980 |
|
|
12'b1xxx10110010,
|
981 |
|
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
982 |
|
|
12'b1xxx10110000,
|
983 |
|
|
12'b1xxx10111000,
|
984 |
|
|
12'b1xxx10110011,
|
985 |
|
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
986 |
|
|
12'b1xxx10100000,
|
987 |
|
|
12'b1xxx10100010,
|
988 |
|
|
12'b1xxx10100011,
|
989 |
|
|
12'b1xxx10101000,
|
990 |
|
|
12'b1xxx10101010,
|
991 |
|
|
12'b1xxx10101011: tran_sel = `TRAN_IF;
|
992 |
|
|
12'b000000100010,
|
993 |
|
|
12'b010000100010,
|
994 |
|
|
12'b010100100010,
|
995 |
|
|
12'b1xxx01xx0011: tran_sel = `TRAN_MEM;
|
996 |
|
|
default: tran_sel = `TRAN_STK;
|
997 |
|
|
endcase
|
998 |
|
|
end
|
999 |
|
|
`WR2B: begin
|
1000 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1001 |
|
|
12'b1xxx10110010,
|
1002 |
|
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
1003 |
|
|
12'b1xxx10110000,
|
1004 |
|
|
12'b1xxx10111000,
|
1005 |
|
|
12'b1xxx10110011,
|
1006 |
|
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
1007 |
|
|
default: tran_sel = `TRAN_IF;
|
1008 |
|
|
endcase
|
1009 |
|
|
end
|
1010 |
|
|
`BLK2: begin
|
1011 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1012 |
|
|
12'b1xxx10110001,
|
1013 |
|
|
12'b1xxx10111001: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
1014 |
|
|
default: tran_sel = `TRAN_IF;
|
1015 |
|
|
endcase
|
1016 |
|
|
end
|
1017 |
|
|
`PCO: begin
|
1018 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1019 |
|
|
12'b000001110110: tran_sel = `TRAN_IDL;
|
1020 |
|
|
default: tran_sel = `TRAN_IF;
|
1021 |
|
|
endcase
|
1022 |
|
|
end
|
1023 |
|
|
`IF1B: begin
|
1024 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1025 |
|
|
12'b1xxx01000101,
|
1026 |
|
|
12'b1xxx01001101,
|
1027 |
|
|
12'b000011110011,
|
1028 |
|
|
12'b0001xxxxxxxx: tran_sel = `TRAN_IF;
|
1029 |
|
|
default: tran_sel = (dmar_reg) ? `TRAN_IDL :
|
1030 |
|
|
(intr_reg) ? `TRAN_IAK : `TRAN_IF;
|
1031 |
|
|
endcase
|
1032 |
|
|
end
|
1033 |
|
|
`HLTB: tran_sel = (xhlt_reg) ? `TRAN_IF : `TRAN_IDL;
|
1034 |
|
|
`INTB: tran_sel = (vector_int) ? `TRAN_IDL : `TRAN_MEM;
|
1035 |
|
|
`DMA2: tran_sel = (dmar_reg) ? `TRAN_IDL : `TRAN_IF;
|
1036 |
|
|
`RSTE: tran_sel = `TRAN_IF;
|
1037 |
|
|
default: tran_sel = `TRAN_RSTVAL;
|
1038 |
|
|
endcase
|
1039 |
|
|
end
|
1040 |
|
|
|
1041 |
|
|
/*****************************************************************************************/
|
1042 |
|
|
/* */
|
1043 |
|
|
/* special transaction identifiers */
|
1044 |
|
|
/* */
|
1045 |
|
|
/*****************************************************************************************/
|
1046 |
|
|
always @ (inst_reg or page_reg or state_reg or xhlt_reg) begin
|
1047 |
|
|
casex (state_reg)
|
1048 |
|
|
`PCO,
|
1049 |
|
|
`HLTB: begin
|
1050 |
|
|
casex ({page_reg, inst_reg})
|
1051 |
|
|
12'b000001110110: halt_nxt = !xhlt_reg;
|
1052 |
|
|
default: halt_nxt = 1'b0;
|
1053 |
|
|
endcase
|
1054 |
|
|
end
|
1055 |
|
|
default: halt_nxt = 1'b0;
|
1056 |
|
|
endcase
|
1057 |
|
|
end
|
1058 |
|
|
|
1059 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
1060 |
|
|
casex (state_reg)
|
1061 |
|
|
`RD2B: begin
|
1062 |
|
|
casex ({page_reg, inst_reg})
|
1063 |
|
|
12'b1xxx01001101: reti_nxt = 1'b1;
|
1064 |
|
|
default: reti_nxt = 1'b0;
|
1065 |
|
|
endcase
|
1066 |
|
|
end
|
1067 |
|
|
default: reti_nxt = 1'b0;
|
1068 |
|
|
endcase
|
1069 |
|
|
end
|
1070 |
|
|
|
1071 |
|
|
/*****************************************************************************************/
|
1072 |
|
|
/* */
|
1073 |
|
|
/* output inhibit */
|
1074 |
|
|
/* */
|
1075 |
|
|
/*****************************************************************************************/
|
1076 |
|
|
always @ (inst_reg or page_reg or state_reg or dmar_reg or xhlt_reg) begin
|
1077 |
|
|
casex (state_reg)
|
1078 |
|
|
`IF1B: begin
|
1079 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1080 |
|
|
12'b1xxx01000101,
|
1081 |
|
|
12'b1xxx01001101,
|
1082 |
|
|
12'b000011110011,
|
1083 |
|
|
12'b0001xxxxxxxx: output_inh = 1'b0;
|
1084 |
|
|
default: output_inh = dmar_reg;
|
1085 |
|
|
endcase
|
1086 |
|
|
end
|
1087 |
|
|
`DMA2: output_inh = dmar_reg;
|
1088 |
|
|
`PCO,
|
1089 |
|
|
`HLTB: begin
|
1090 |
|
|
casex ({page_reg, inst_reg})
|
1091 |
|
|
12'b000001110110: output_inh = !xhlt_reg;
|
1092 |
|
|
default: output_inh = 1'b0;
|
1093 |
|
|
endcase
|
1094 |
|
|
end
|
1095 |
|
|
default: output_inh = 1'b0;
|
1096 |
|
|
endcase
|
1097 |
|
|
end
|
1098 |
|
|
|
1099 |
|
|
/*****************************************************************************************/
|
1100 |
|
|
/* */
|
1101 |
|
|
/* address output control */
|
1102 |
|
|
/* */
|
1103 |
|
|
/*****************************************************************************************/
|
1104 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
|
1105 |
|
|
vector_int or zero_bit) begin
|
1106 |
|
|
casex (state_reg) //synopsys parallel_case
|
1107 |
|
|
`DEC1: begin
|
1108 |
|
|
casex (inst_reg) //synopsys parallel_case
|
1109 |
|
|
8'b00000010,
|
1110 |
|
|
8'b00001010,
|
1111 |
|
|
8'b00010010,
|
1112 |
|
|
8'b00011010,
|
1113 |
|
|
8'b11101001,
|
1114 |
|
|
8'b11xx0101,
|
1115 |
|
|
8'b11xxx111: add_sel = `ADD_ALU;
|
1116 |
|
|
8'b00110100,
|
1117 |
|
|
8'b00110101,
|
1118 |
|
|
8'b00110110,
|
1119 |
|
|
8'b011100xx,
|
1120 |
|
|
8'b0111010x,
|
1121 |
|
|
8'b01110111,
|
1122 |
|
|
8'b010xx110,
|
1123 |
|
|
8'b0110x110,
|
1124 |
|
|
8'b01111110,
|
1125 |
|
|
8'b10000110,
|
1126 |
|
|
8'b10001110,
|
1127 |
|
|
8'b10010110,
|
1128 |
|
|
8'b10011110,
|
1129 |
|
|
8'b10100110,
|
1130 |
|
|
8'b10101110,
|
1131 |
|
|
8'b10110110,
|
1132 |
|
|
8'b10111110: add_sel = `ADD_HL;
|
1133 |
|
|
8'b11000000: add_sel = ( !zero_bit) ? `ADD_SP : `ADD_PC;
|
1134 |
|
|
8'b11001000: add_sel = ( zero_bit) ? `ADD_SP : `ADD_PC;
|
1135 |
|
|
8'b11010000: add_sel = (!carry_bit) ? `ADD_SP : `ADD_PC;
|
1136 |
|
|
8'b11011000: add_sel = ( carry_bit) ? `ADD_SP : `ADD_PC;
|
1137 |
|
|
8'b11100000: add_sel = ( !par_bit) ? `ADD_SP : `ADD_PC;
|
1138 |
|
|
8'b11101000: add_sel = ( par_bit) ? `ADD_SP : `ADD_PC;
|
1139 |
|
|
8'b11110000: add_sel = ( !sign_bit) ? `ADD_SP : `ADD_PC;
|
1140 |
|
|
8'b11111000: add_sel = ( sign_bit) ? `ADD_SP : `ADD_PC;
|
1141 |
|
|
8'b11xx0001,
|
1142 |
|
|
8'b11100011,
|
1143 |
|
|
8'b11001001: add_sel = `ADD_SP;
|
1144 |
|
|
default: add_sel = `ADD_PC;
|
1145 |
|
|
endcase
|
1146 |
|
|
end
|
1147 |
|
|
`DEC2: begin
|
1148 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1149 |
|
|
12'b010011100101,
|
1150 |
|
|
12'b010011101001,
|
1151 |
|
|
12'b010111100101,
|
1152 |
|
|
12'b010111101001,
|
1153 |
|
|
12'b1xxx01xxx000,
|
1154 |
|
|
12'b1xxx01xxx001,
|
1155 |
|
|
12'b1xxx10100000,
|
1156 |
|
|
12'b1xxx10100001,
|
1157 |
|
|
12'b1xxx10100010,
|
1158 |
|
|
12'b1xxx10100011,
|
1159 |
|
|
12'b1xxx10101000,
|
1160 |
|
|
12'b1xxx10101001,
|
1161 |
|
|
12'b1xxx10101010,
|
1162 |
|
|
12'b1xxx10101011,
|
1163 |
|
|
12'b1xxx10110000,
|
1164 |
|
|
12'b1xxx10110001,
|
1165 |
|
|
12'b1xxx10110010,
|
1166 |
|
|
12'b1xxx10110011,
|
1167 |
|
|
12'b1xxx10111000,
|
1168 |
|
|
12'b1xxx10111001,
|
1169 |
|
|
12'b1xxx10111010,
|
1170 |
|
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
1171 |
|
|
12'b001000000110,
|
1172 |
|
|
12'b001000001110,
|
1173 |
|
|
12'b001000010110,
|
1174 |
|
|
12'b001000011110,
|
1175 |
|
|
12'b001000100110,
|
1176 |
|
|
12'b001000101110,
|
1177 |
|
|
12'b001000111110,
|
1178 |
|
|
12'b001001xxx110,
|
1179 |
|
|
12'b001010xxx110,
|
1180 |
|
|
12'b001011xxx110,
|
1181 |
|
|
12'b1xxx01100111,
|
1182 |
|
|
12'b1xxx01101111: add_sel = `ADD_HL;
|
1183 |
|
|
12'b010011100001,
|
1184 |
|
|
12'b010011100011,
|
1185 |
|
|
12'b010111100001,
|
1186 |
|
|
12'b010111100011,
|
1187 |
|
|
12'b1xxx01000101,
|
1188 |
|
|
12'b1xxx01001101: add_sel = `ADD_SP;
|
1189 |
|
|
default: add_sel = `ADD_PC;
|
1190 |
|
|
endcase
|
1191 |
|
|
end
|
1192 |
|
|
`OF2A: begin
|
1193 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1194 |
|
|
12'b000011001101,
|
1195 |
|
|
12'b010000110110,
|
1196 |
|
|
12'b010100110110: add_sel = `ADD_ALU;
|
1197 |
|
|
12'b000011000100: add_sel = ( !zero_bit) ? `ADD_ALU : `ADD_PC;
|
1198 |
|
|
12'b000011001100: add_sel = ( zero_bit) ? `ADD_ALU : `ADD_PC;
|
1199 |
|
|
12'b000011010100: add_sel = (!carry_bit) ? `ADD_ALU : `ADD_PC;
|
1200 |
|
|
12'b000011011100: add_sel = ( carry_bit) ? `ADD_ALU : `ADD_PC;
|
1201 |
|
|
12'b000011100100: add_sel = ( !par_bit) ? `ADD_ALU : `ADD_PC;
|
1202 |
|
|
12'b000011101100: add_sel = ( par_bit) ? `ADD_ALU : `ADD_PC;
|
1203 |
|
|
12'b000011110100: add_sel = ( !sign_bit) ? `ADD_ALU : `ADD_PC;
|
1204 |
|
|
12'b000011111100: add_sel = ( sign_bit) ? `ADD_ALU : `ADD_PC;
|
1205 |
|
|
default: add_sel = `ADD_PC;
|
1206 |
|
|
endcase
|
1207 |
|
|
end
|
1208 |
|
|
`IF3A,
|
1209 |
|
|
`ADR1,
|
1210 |
|
|
`RD1A: add_sel = `ADD_ALU;
|
1211 |
|
|
`RD2A: begin
|
1212 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1213 |
|
|
12'b000011100011,
|
1214 |
|
|
12'b0001xxxxxxxx,
|
1215 |
|
|
12'b010000110100,
|
1216 |
|
|
12'b010000110101,
|
1217 |
|
|
12'b010011100011,
|
1218 |
|
|
12'b010100110100,
|
1219 |
|
|
12'b010100110101,
|
1220 |
|
|
12'b010111100011,
|
1221 |
|
|
12'b011000000110,
|
1222 |
|
|
12'b011000001110,
|
1223 |
|
|
12'b011000010110,
|
1224 |
|
|
12'b011000011110,
|
1225 |
|
|
12'b011000100110,
|
1226 |
|
|
12'b011000101110,
|
1227 |
|
|
12'b011000111110,
|
1228 |
|
|
12'b011010xxx110,
|
1229 |
|
|
12'b011011xxx110,
|
1230 |
|
|
12'b011100000110,
|
1231 |
|
|
12'b011100001110,
|
1232 |
|
|
12'b011100010110,
|
1233 |
|
|
12'b011100011110,
|
1234 |
|
|
12'b011100100110,
|
1235 |
|
|
12'b011100101110,
|
1236 |
|
|
12'b011100111110,
|
1237 |
|
|
12'b011110xxx110,
|
1238 |
|
|
12'b011111xxx110,
|
1239 |
|
|
12'b1xxx10100000,
|
1240 |
|
|
12'b1xxx10100001,
|
1241 |
|
|
12'b1xxx10100010,
|
1242 |
|
|
12'b1xxx10100011,
|
1243 |
|
|
12'b1xxx10101000,
|
1244 |
|
|
12'b1xxx10101001,
|
1245 |
|
|
12'b1xxx10101010,
|
1246 |
|
|
12'b1xxx10101011,
|
1247 |
|
|
12'b1xxx10110000,
|
1248 |
|
|
12'b1xxx10110001,
|
1249 |
|
|
12'b1xxx10110010,
|
1250 |
|
|
12'b1xxx10110011,
|
1251 |
|
|
12'b1xxx10111000,
|
1252 |
|
|
12'b1xxx10111001,
|
1253 |
|
|
12'b1xxx10111010,
|
1254 |
|
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
1255 |
|
|
12'b000000110100,
|
1256 |
|
|
12'b000000110101,
|
1257 |
|
|
12'b000000xxx100,
|
1258 |
|
|
12'b000000xxx101,
|
1259 |
|
|
12'b001000000110,
|
1260 |
|
|
12'b001000000xxx,
|
1261 |
|
|
12'b001000001110,
|
1262 |
|
|
12'b001000001xxx,
|
1263 |
|
|
12'b001000010110,
|
1264 |
|
|
12'b001000010xxx,
|
1265 |
|
|
12'b001000011110,
|
1266 |
|
|
12'b001000011xxx,
|
1267 |
|
|
12'b001000100110,
|
1268 |
|
|
12'b001000100xxx,
|
1269 |
|
|
12'b001000101110,
|
1270 |
|
|
12'b001000101xxx,
|
1271 |
|
|
12'b001000111110,
|
1272 |
|
|
12'b001000111xxx,
|
1273 |
|
|
12'b001010xxx110,
|
1274 |
|
|
12'b001010xxxxxx,
|
1275 |
|
|
12'b001011xxx110,
|
1276 |
|
|
12'b001011xxxxxx,
|
1277 |
|
|
12'b1xxx01100111,
|
1278 |
|
|
12'b1xxx01101111: add_sel = `ADD_HL;
|
1279 |
|
|
default: add_sel = `ADD_PC;
|
1280 |
|
|
endcase
|
1281 |
|
|
end
|
1282 |
|
|
`WR1A: begin
|
1283 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1284 |
|
|
12'b1xxx10100000,
|
1285 |
|
|
12'b1xxx10100010,
|
1286 |
|
|
12'b1xxx10100011,
|
1287 |
|
|
12'b1xxx10101000,
|
1288 |
|
|
12'b1xxx10101010,
|
1289 |
|
|
12'b1xxx10101011: add_sel = `ADD_PC;
|
1290 |
|
|
default: add_sel = `ADD_ALU;
|
1291 |
|
|
endcase
|
1292 |
|
|
end
|
1293 |
|
|
`WR2A: begin
|
1294 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1295 |
|
|
12'b000011001101,
|
1296 |
|
|
12'b000011xxx100,
|
1297 |
|
|
12'b000011xxx111,
|
1298 |
|
|
12'b0001xxxxxxxx,
|
1299 |
|
|
12'b1xxx10100000,
|
1300 |
|
|
12'b1xxx10100010,
|
1301 |
|
|
12'b1xxx10100011,
|
1302 |
|
|
12'b1xxx10101000,
|
1303 |
|
|
12'b1xxx10101010,
|
1304 |
|
|
12'b1xxx10101011,
|
1305 |
|
|
12'b1xxx10110000,
|
1306 |
|
|
12'b1xxx10110010,
|
1307 |
|
|
12'b1xxx10110011,
|
1308 |
|
|
12'b1xxx10111000,
|
1309 |
|
|
12'b1xxx10111010,
|
1310 |
|
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
1311 |
|
|
default: add_sel = `ADD_PC;
|
1312 |
|
|
endcase
|
1313 |
|
|
end
|
1314 |
|
|
`BLK1: begin
|
1315 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1316 |
|
|
12'b1xxx10110001,
|
1317 |
|
|
12'b1xxx10111001: add_sel = `ADD_ALU;
|
1318 |
|
|
default: add_sel = `ADD_PC;
|
1319 |
|
|
endcase
|
1320 |
|
|
end
|
1321 |
|
|
`PCA: begin
|
1322 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1323 |
|
|
12'b000000010000,
|
1324 |
|
|
12'b000000011000,
|
1325 |
|
|
12'b0000001xx000,
|
1326 |
|
|
12'b000011000011,
|
1327 |
|
|
12'b000011001001,
|
1328 |
|
|
12'b000011xxx000,
|
1329 |
|
|
12'b000011xxx010,
|
1330 |
|
|
12'b1xxx01000101,
|
1331 |
|
|
12'b1xxx01001101: add_sel = `ADD_PC;
|
1332 |
|
|
default: add_sel = `ADD_ALU;
|
1333 |
|
|
endcase
|
1334 |
|
|
end
|
1335 |
|
|
`IF1A: add_sel = `ADD_PC;
|
1336 |
|
|
`INTA: add_sel = (vector_int) ? `ADD_PC : `ADD_ALU;
|
1337 |
|
|
`DMA1: add_sel = `ADD_PC;
|
1338 |
|
|
default: add_sel = `ADD_RSTVAL;
|
1339 |
|
|
endcase
|
1340 |
|
|
end
|
1341 |
|
|
|
1342 |
|
|
/*****************************************************************************************/
|
1343 |
|
|
/* */
|
1344 |
|
|
/* program counter control */
|
1345 |
|
|
/* */
|
1346 |
|
|
/*****************************************************************************************/
|
1347 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
|
1348 |
|
|
tflg_reg or zero_bit) begin
|
1349 |
|
|
casex (state_reg) //synopsys parallel_case
|
1350 |
|
|
`DEC1: begin
|
1351 |
|
|
casex (inst_reg) //synopsys parallel_case
|
1352 |
|
|
8'b00000000,
|
1353 |
|
|
8'b00000111,
|
1354 |
|
|
8'b00001000,
|
1355 |
|
|
8'b00001111,
|
1356 |
|
|
8'b00010111,
|
1357 |
|
|
8'b00011111,
|
1358 |
|
|
8'b00100111,
|
1359 |
|
|
8'b00101111,
|
1360 |
|
|
8'b00110111,
|
1361 |
|
|
8'b00111111,
|
1362 |
|
|
8'b000xx10x,
|
1363 |
|
|
8'b0010x10x,
|
1364 |
|
|
8'b0011110x,
|
1365 |
|
|
8'b00xx0011,
|
1366 |
|
|
8'b00xx1001,
|
1367 |
|
|
8'b00xx1011,
|
1368 |
|
|
8'b010xx0xx,
|
1369 |
|
|
8'b0110x0xx,
|
1370 |
|
|
8'b011110xx,
|
1371 |
|
|
8'b010xx10x,
|
1372 |
|
|
8'b0110x10x,
|
1373 |
|
|
8'b0111110x,
|
1374 |
|
|
8'b010xx111,
|
1375 |
|
|
8'b0110x111,
|
1376 |
|
|
8'b01111111,
|
1377 |
|
|
8'b10xxx0xx,
|
1378 |
|
|
8'b10xxx10x,
|
1379 |
|
|
8'b10xxx111,
|
1380 |
|
|
8'b11011001,
|
1381 |
|
|
8'b11101011,
|
1382 |
|
|
8'b11111001,
|
1383 |
|
|
8'b11111011: pc_sel = `PC_NILD;
|
1384 |
|
|
8'b01110110,
|
1385 |
|
|
8'b11xxx111,
|
1386 |
|
|
8'b00000010,
|
1387 |
|
|
8'b00001010,
|
1388 |
|
|
8'b00010010,
|
1389 |
|
|
8'b00011010,
|
1390 |
|
|
8'b00110100,
|
1391 |
|
|
8'b00110101,
|
1392 |
|
|
8'b011100xx,
|
1393 |
|
|
8'b0111010x,
|
1394 |
|
|
8'b01110111,
|
1395 |
|
|
8'b010xx110,
|
1396 |
|
|
8'b0110x110,
|
1397 |
|
|
8'b01111110,
|
1398 |
|
|
8'b10000110,
|
1399 |
|
|
8'b10001110,
|
1400 |
|
|
8'b10010110,
|
1401 |
|
|
8'b10011110,
|
1402 |
|
|
8'b10100110,
|
1403 |
|
|
8'b10101110,
|
1404 |
|
|
8'b10110110,
|
1405 |
|
|
8'b10111110,
|
1406 |
|
|
8'b11xx0001,
|
1407 |
|
|
8'b11xx0101,
|
1408 |
|
|
8'b11100011: pc_sel = `PC_NUL;
|
1409 |
|
|
default: pc_sel = `PC_LD;
|
1410 |
|
|
endcase
|
1411 |
|
|
end
|
1412 |
|
|
`DEC2: begin
|
1413 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1414 |
|
|
12'b010011001011, //DD+CB prefix
|
1415 |
|
|
12'b010111001011, //FD+CB prefix
|
1416 |
|
|
12'b010000100001,
|
1417 |
|
|
12'b010000100010,
|
1418 |
|
|
12'b010000101010,
|
1419 |
|
|
12'b010000110100,
|
1420 |
|
|
12'b010000110101,
|
1421 |
|
|
12'b010000110110,
|
1422 |
|
|
12'b010001110xxx,
|
1423 |
|
|
12'b010001xxx110,
|
1424 |
|
|
12'b010010000110,
|
1425 |
|
|
12'b010010001110,
|
1426 |
|
|
12'b010010010110,
|
1427 |
|
|
12'b010010011110,
|
1428 |
|
|
12'b010010100110,
|
1429 |
|
|
12'b010010101110,
|
1430 |
|
|
12'b010010110110,
|
1431 |
|
|
12'b010010111110,
|
1432 |
|
|
12'b010011101001,
|
1433 |
|
|
12'b010100100001,
|
1434 |
|
|
12'b010100100010,
|
1435 |
|
|
12'b010100101010,
|
1436 |
|
|
12'b010100110100,
|
1437 |
|
|
12'b010100110101,
|
1438 |
|
|
12'b010100110110,
|
1439 |
|
|
12'b010101110xxx,
|
1440 |
|
|
12'b010101xxx110,
|
1441 |
|
|
12'b010110000110,
|
1442 |
|
|
12'b010110001110,
|
1443 |
|
|
12'b010110010110,
|
1444 |
|
|
12'b010110011110,
|
1445 |
|
|
12'b010110100110,
|
1446 |
|
|
12'b010110101110,
|
1447 |
|
|
12'b010110110110,
|
1448 |
|
|
12'b010110111110,
|
1449 |
|
|
12'b010111101001,
|
1450 |
|
|
12'b011000000110,
|
1451 |
|
|
12'b011000001110,
|
1452 |
|
|
12'b011000010110,
|
1453 |
|
|
12'b011000011110,
|
1454 |
|
|
12'b011000100110,
|
1455 |
|
|
12'b011000101110,
|
1456 |
|
|
12'b011000111110,
|
1457 |
|
|
12'b011001xxx110,
|
1458 |
|
|
12'b011010xxx110,
|
1459 |
|
|
12'b011011xxx110,
|
1460 |
|
|
12'b011100000110,
|
1461 |
|
|
12'b011100001110,
|
1462 |
|
|
12'b011100010110,
|
1463 |
|
|
12'b011100011110,
|
1464 |
|
|
12'b011100100110,
|
1465 |
|
|
12'b011100101110,
|
1466 |
|
|
12'b011100111110,
|
1467 |
|
|
12'b011101xxx110,
|
1468 |
|
|
12'b011110xxx110,
|
1469 |
|
|
12'b011111xxx110,
|
1470 |
|
|
12'b1xxx01000101,
|
1471 |
|
|
12'b1xxx01001101,
|
1472 |
|
|
12'b1xxx01xx0011,
|
1473 |
|
|
12'b1xxx01xx1011: pc_sel = `PC_LD;
|
1474 |
|
|
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr,
|
1475 |
|
|
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr,
|
1476 |
|
|
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr,
|
1477 |
|
|
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr,
|
1478 |
|
|
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr,
|
1479 |
|
|
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr,
|
1480 |
|
|
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr,
|
1481 |
|
|
12'b001001xxx0xx,12'b001001xxx10x,12'b001001xxx111,//12'b001001xxxrrr,
|
1482 |
|
|
12'b001010xxx0xx,12'b001010xxx10x,12'b001010xxx111,//12'b001010xxxrrr,
|
1483 |
|
|
12'b001011xxx0xx,12'b001011xxx10x,12'b001011xxx111,//12'b001011xxxrrr,
|
1484 |
|
|
12'b010000100011,
|
1485 |
|
|
12'b010000101011,
|
1486 |
|
|
12'b010000xx1001,
|
1487 |
|
|
12'b010011111001,
|
1488 |
|
|
12'b010100100011,
|
1489 |
|
|
12'b010100101011,
|
1490 |
|
|
12'b010100xx1001,
|
1491 |
|
|
12'b010111111001,
|
1492 |
|
|
12'b1xxx01000100,
|
1493 |
|
|
12'b1xxx01000110,
|
1494 |
|
|
12'b1xxx01000111,
|
1495 |
|
|
12'b1xxx01001111,
|
1496 |
|
|
12'b1xxx01010110,
|
1497 |
|
|
12'b1xxx01010111,
|
1498 |
|
|
12'b1xxx01011110,
|
1499 |
|
|
12'b1xxx01011111,
|
1500 |
|
|
12'b1xxx01xx0010,
|
1501 |
|
|
12'b1xxx01xx1010: pc_sel = `PC_NILD;
|
1502 |
|
|
default: pc_sel = `PC_NUL;
|
1503 |
|
|
endcase
|
1504 |
|
|
end
|
1505 |
|
|
`OF2A: begin
|
1506 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1507 |
|
|
12'b000000100010,
|
1508 |
|
|
12'b000000101010,
|
1509 |
|
|
12'b000000110010,
|
1510 |
|
|
12'b000000111010,
|
1511 |
|
|
12'b000000xx0001,
|
1512 |
|
|
12'b000011000011,
|
1513 |
|
|
12'b000011001101,
|
1514 |
|
|
12'b000011xxx010,
|
1515 |
|
|
12'b000011xxx100,
|
1516 |
|
|
12'b010000100001,
|
1517 |
|
|
12'b010000100010,
|
1518 |
|
|
12'b010000101010,
|
1519 |
|
|
12'b010000110110,
|
1520 |
|
|
12'b010100100001,
|
1521 |
|
|
12'b010100100010,
|
1522 |
|
|
12'b010100101010,
|
1523 |
|
|
12'b010100110110,
|
1524 |
|
|
12'b1xxx01xx0011,
|
1525 |
|
|
12'b1xxx01xx1011: pc_sel = `PC_LD;
|
1526 |
|
|
default: pc_sel = `PC_NUL;
|
1527 |
|
|
endcase
|
1528 |
|
|
end
|
1529 |
|
|
`IF3A: begin
|
1530 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1531 |
|
|
12'b01xx11001011: pc_sel = `PC_LD;
|
1532 |
|
|
default: pc_sel = `PC_NUL;
|
1533 |
|
|
endcase
|
1534 |
|
|
end
|
1535 |
|
|
`WR2B: begin
|
1536 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1537 |
|
|
12'b000011001101,
|
1538 |
|
|
12'b000011xxx100,
|
1539 |
|
|
12'b000011xxx111,
|
1540 |
|
|
12'b0001xxxxxxxx: pc_sel = `PC_LD;
|
1541 |
|
|
default: pc_sel = `PC_NUL;
|
1542 |
|
|
endcase
|
1543 |
|
|
end
|
1544 |
|
|
// `ADR1: pc_sel = `PC_NUL;
|
1545 |
|
|
`RD1B,
|
1546 |
|
|
`RD2B: begin
|
1547 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1548 |
|
|
12'b1xxx10110000,
|
1549 |
|
|
12'b1xxx10110001,
|
1550 |
|
|
12'b1xxx10110010,
|
1551 |
|
|
12'b1xxx10110011,
|
1552 |
|
|
12'b1xxx10111000,
|
1553 |
|
|
12'b1xxx10111001,
|
1554 |
|
|
12'b1xxx10111010,
|
1555 |
|
|
12'b1xxx10111011: pc_sel = `PC_INT;
|
1556 |
|
|
default: pc_sel = `PC_NUL;
|
1557 |
|
|
endcase
|
1558 |
|
|
end
|
1559 |
|
|
`PCA: begin
|
1560 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1561 |
|
|
12'b000000010000: pc_sel = (tflg_reg) ? `PC_NUL : `PC_LD;
|
1562 |
|
|
12'b000000011000,
|
1563 |
|
|
12'b0000001xx000,
|
1564 |
|
|
12'b000011000011,
|
1565 |
|
|
12'b000011001001,
|
1566 |
|
|
12'b000011xxx000,
|
1567 |
|
|
12'b000011xxx010,
|
1568 |
|
|
12'b1xxx01000101,
|
1569 |
|
|
12'b1xxx01001101: pc_sel = `PC_LD;
|
1570 |
|
|
default: pc_sel = `PC_NUL;
|
1571 |
|
|
endcase
|
1572 |
|
|
end
|
1573 |
|
|
`PCO: begin
|
1574 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1575 |
|
|
12'b000011101001,
|
1576 |
|
|
12'b010011101001,
|
1577 |
|
|
12'b010111101001,
|
1578 |
|
|
12'b1xxx10110000,
|
1579 |
|
|
12'b1xxx10110001,
|
1580 |
|
|
12'b1xxx10110010,
|
1581 |
|
|
12'b1xxx10110011,
|
1582 |
|
|
12'b1xxx10111000,
|
1583 |
|
|
12'b1xxx10111001,
|
1584 |
|
|
12'b1xxx10111010,
|
1585 |
|
|
12'b1xxx10111011: pc_sel = `PC_LD;
|
1586 |
|
|
default: pc_sel = `PC_NUL;
|
1587 |
|
|
endcase
|
1588 |
|
|
end
|
1589 |
|
|
`IF1A: begin
|
1590 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1591 |
|
|
12'b1xxx01000101,
|
1592 |
|
|
12'b1xxx01001101,
|
1593 |
|
|
12'b0001xxxxxxxx: pc_sel = `PC_LD;
|
1594 |
|
|
12'b1xxx10110000,
|
1595 |
|
|
12'b1xxx10110001,
|
1596 |
|
|
12'b1xxx10110010,
|
1597 |
|
|
12'b1xxx10110011,
|
1598 |
|
|
12'b1xxx10111000,
|
1599 |
|
|
12'b1xxx10111001,
|
1600 |
|
|
12'b1xxx10111010,
|
1601 |
|
|
12'b1xxx10111011: pc_sel = `PC_NILD2;
|
1602 |
|
|
default: pc_sel = `PC_NILD;
|
1603 |
|
|
endcase
|
1604 |
|
|
end
|
1605 |
|
|
`HLTA: pc_sel = `PC_INT;
|
1606 |
|
|
`DMA1: pc_sel = `PC_DMA;
|
1607 |
|
|
default: pc_sel = `PC_NUL;
|
1608 |
|
|
endcase
|
1609 |
|
|
end
|
1610 |
|
|
|
1611 |
|
|
/*****************************************************************************************/
|
1612 |
|
|
/* */
|
1613 |
|
|
/* interrupt ack and dma ack */
|
1614 |
|
|
/* */
|
1615 |
|
|
/*****************************************************************************************/
|
1616 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
1617 |
|
|
casex (state_reg) //synopsys parallel_case
|
1618 |
|
|
`IF1B: begin
|
1619 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1620 |
|
|
12'b1xxx01000101,
|
1621 |
|
|
12'b1xxx01001101,
|
1622 |
|
|
12'b000011110011,
|
1623 |
|
|
12'b0001xxxxxxxx: ld_inta = 1'b0;
|
1624 |
|
|
default: ld_inta = 1'b1;
|
1625 |
|
|
endcase
|
1626 |
|
|
end
|
1627 |
|
|
default: ld_inta = 1'b0;
|
1628 |
|
|
endcase
|
1629 |
|
|
end
|
1630 |
|
|
|
1631 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
1632 |
|
|
casex (state_reg) //synopsys parallel_case
|
1633 |
|
|
`IF1B: begin
|
1634 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1635 |
|
|
12'b1xxx01000101,
|
1636 |
|
|
12'b1xxx01001101,
|
1637 |
|
|
12'b000011110011,
|
1638 |
|
|
12'b0001xxxxxxxx: ld_dmaa = 1'b0;
|
1639 |
|
|
default: ld_dmaa = 1'b1;
|
1640 |
|
|
endcase
|
1641 |
|
|
end
|
1642 |
|
|
`HLTB,
|
1643 |
|
|
`DMA2: ld_dmaa = 1'b1;
|
1644 |
|
|
default: ld_dmaa = 1'b0;
|
1645 |
|
|
endcase
|
1646 |
|
|
end
|
1647 |
|
|
|
1648 |
|
|
/*****************************************************************************************/
|
1649 |
|
|
/* */
|
1650 |
|
|
/* data input register control */
|
1651 |
|
|
/* */
|
1652 |
|
|
/*****************************************************************************************/
|
1653 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
1654 |
|
|
casex (state_reg) //synopsys parallel_case
|
1655 |
|
|
`OF1B: di_ctl = `DI_DI10;
|
1656 |
|
|
`OF2B: begin
|
1657 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1658 |
|
|
12'b010000110110,
|
1659 |
|
|
12'b010100110110: di_ctl = `DI_DI0;
|
1660 |
|
|
default: di_ctl = `DI_DI1;
|
1661 |
|
|
endcase
|
1662 |
|
|
end
|
1663 |
|
|
`RD1B: di_ctl = `DI_DI0;
|
1664 |
|
|
`RD2B: begin
|
1665 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1666 |
|
|
12'b000000101010,
|
1667 |
|
|
12'b000011001001,
|
1668 |
|
|
12'b010x00101010,
|
1669 |
|
|
12'b010x11100001,
|
1670 |
|
|
12'b010x11100011,
|
1671 |
|
|
12'b000011100011,
|
1672 |
|
|
12'b1xxx01000101,
|
1673 |
|
|
12'b1xxx01001101,
|
1674 |
|
|
12'b1xxx01xx1011,
|
1675 |
|
|
12'b000011xxx000,
|
1676 |
|
|
12'b000011xx0001,
|
1677 |
|
|
12'b0001xxxxxxxx: di_ctl = `DI_DI1;
|
1678 |
|
|
default: di_ctl = `DI_DI0;
|
1679 |
|
|
endcase
|
1680 |
|
|
end
|
1681 |
|
|
`INTB: di_ctl = `DI_DI0;
|
1682 |
|
|
default: di_ctl = `DI_NUL;
|
1683 |
|
|
endcase
|
1684 |
|
|
end
|
1685 |
|
|
|
1686 |
|
|
/*****************************************************************************************/
|
1687 |
|
|
/* */
|
1688 |
|
|
/* data output register control */
|
1689 |
|
|
/* */
|
1690 |
|
|
/*****************************************************************************************/
|
1691 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
1692 |
|
|
casex (state_reg) //synopsys parallel_case
|
1693 |
|
|
`WR1A: begin
|
1694 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1695 |
|
|
12'b000011001101,
|
1696 |
|
|
12'b010x11100101,
|
1697 |
|
|
12'b000011xxx100,
|
1698 |
|
|
12'b000011xx0101,
|
1699 |
|
|
12'b000011xxx111,
|
1700 |
|
|
12'b0001xxxxxxxx: do_ctl = `DO_MSB;
|
1701 |
|
|
12'b1xxx10100011,
|
1702 |
|
|
12'b1xxx10101011,
|
1703 |
|
|
12'b1xxx10110011,
|
1704 |
|
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
1705 |
|
|
default: do_ctl = `DO_LSB;
|
1706 |
|
|
endcase
|
1707 |
|
|
end
|
1708 |
|
|
`WR2A: begin
|
1709 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1710 |
|
|
12'b000000100010,
|
1711 |
|
|
12'b010x00100010,
|
1712 |
|
|
12'b010x11100011,
|
1713 |
|
|
12'b000011100011,
|
1714 |
|
|
12'b1xxx01xx0011: do_ctl = `DO_MSB;
|
1715 |
|
|
12'b000011010011,
|
1716 |
|
|
12'b1xxx0x0xx001,
|
1717 |
|
|
12'b1xxx0x10x001,
|
1718 |
|
|
12'b1xxx0x111001,
|
1719 |
|
|
12'b1xxx10100011,
|
1720 |
|
|
12'b1xxx10101011,
|
1721 |
|
|
12'b1xxx10110011,
|
1722 |
|
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
1723 |
|
|
default: do_ctl = `DO_LSB;
|
1724 |
|
|
endcase
|
1725 |
|
|
end
|
1726 |
|
|
default: do_ctl = `DO_NUL;
|
1727 |
|
|
endcase
|
1728 |
|
|
end
|
1729 |
|
|
|
1730 |
|
|
/*****************************************************************************************/
|
1731 |
|
|
/* */
|
1732 |
|
|
/* alu operation control */
|
1733 |
|
|
/* */
|
1734 |
|
|
/*****************************************************************************************/
|
1735 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
|
1736 |
|
|
zero_bit) begin
|
1737 |
|
|
casex (state_reg) //synopsys parallel_case
|
1738 |
|
|
`DEC1: begin
|
1739 |
|
|
casex (inst_reg) //synopsys parallel_case
|
1740 |
|
|
8'b00xx0011,
|
1741 |
|
|
8'b00xx1001,
|
1742 |
|
|
8'b00xx1011,
|
1743 |
|
|
8'b11100011,
|
1744 |
|
|
8'b11xx0101,
|
1745 |
|
|
8'b11xxx111: aluop_sel = `ALUOP_ADD;
|
1746 |
|
|
8'b10001xxx: aluop_sel = `ALUOP_BADC;
|
1747 |
|
|
8'b00010000,
|
1748 |
|
|
8'b00xxx100,
|
1749 |
|
|
8'b10000xxx: aluop_sel = `ALUOP_BADD;
|
1750 |
|
|
8'b10100xxx: aluop_sel = `ALUOP_BAND;
|
1751 |
|
|
8'b00xxx101: aluop_sel = `ALUOP_BDEC;
|
1752 |
|
|
8'b10110xxx: aluop_sel = `ALUOP_BOR;
|
1753 |
|
|
8'b10011xxx: aluop_sel = `ALUOP_BSBC;
|
1754 |
|
|
8'b10010xxx,
|
1755 |
|
|
8'b10111xxx: aluop_sel = `ALUOP_BSUB;
|
1756 |
|
|
8'b00101111,
|
1757 |
|
|
8'b10101xxx: aluop_sel = `ALUOP_BXOR;
|
1758 |
|
|
8'b00111111: aluop_sel = `ALUOP_CCF;
|
1759 |
|
|
8'b00100111: aluop_sel = `ALUOP_DAA;
|
1760 |
|
|
8'b00010111: aluop_sel = `ALUOP_RLA;
|
1761 |
|
|
8'b00000111: aluop_sel = `ALUOP_RLCA;
|
1762 |
|
|
8'b00011111: aluop_sel = `ALUOP_RRA;
|
1763 |
|
|
8'b00001111: aluop_sel = `ALUOP_RRCA;
|
1764 |
|
|
8'b00110111: aluop_sel = `ALUOP_SCF;
|
1765 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
1766 |
|
|
endcase
|
1767 |
|
|
end
|
1768 |
|
|
`IF2B: aluop_sel = `ALUOP_ADD;
|
1769 |
|
|
`DEC2: begin
|
1770 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1771 |
|
|
12'b1xxx01xx1010: aluop_sel = `ALUOP_ADC;
|
1772 |
|
|
12'b010000100011,
|
1773 |
|
|
12'b010000101011,
|
1774 |
|
|
12'b010000xx1001,
|
1775 |
|
|
12'b010011100101,
|
1776 |
|
|
12'b010100100011,
|
1777 |
|
|
12'b010100101011,
|
1778 |
|
|
12'b010100xx1001,
|
1779 |
|
|
12'b010111100101: aluop_sel = `ALUOP_ADD;
|
1780 |
|
|
12'b1xxx01010111,
|
1781 |
|
|
12'b1xxx01011111: aluop_sel = `ALUOP_APAS;
|
1782 |
|
|
//12'b001001xxx110,
|
1783 |
|
|
//12'b001001xxxrrr,
|
1784 |
|
|
12'b001001xxxxxx,
|
1785 |
|
|
//12'b001010xxx110,
|
1786 |
|
|
//12'b001010xxxrrr,
|
1787 |
|
|
12'b001010xxxxxx: aluop_sel = `ALUOP_BAND;
|
1788 |
|
|
//12'b001011xxx110,
|
1789 |
|
|
//12'b001011xxxrrr,
|
1790 |
|
|
12'b001011xxxxxx: aluop_sel = `ALUOP_BOR;
|
1791 |
|
|
12'b1xxx01000100: aluop_sel = `ALUOP_BSUB;
|
1792 |
|
|
//12'b001000010110,
|
1793 |
|
|
//12'b001000010rrr,
|
1794 |
|
|
12'b001000010xxx: aluop_sel = `ALUOP_RL;
|
1795 |
|
|
//12'b001000000110,
|
1796 |
|
|
//12'b001000000rrr,
|
1797 |
|
|
12'b001000000xxx: aluop_sel = `ALUOP_RLC;
|
1798 |
|
|
//12'b001000011110,
|
1799 |
|
|
//12'b001000011rrr,
|
1800 |
|
|
12'b001000011xxx: aluop_sel = `ALUOP_RR;
|
1801 |
|
|
//12'b001000001110,
|
1802 |
|
|
//12'b001000001rrr,
|
1803 |
|
|
12'b001000001xxx: aluop_sel = `ALUOP_RRC;
|
1804 |
|
|
12'b1xxx01xx0010: aluop_sel = `ALUOP_SBC;
|
1805 |
|
|
//12'b001000100110,
|
1806 |
|
|
//12'b001000100rrr,
|
1807 |
|
|
12'b001000100xxx: aluop_sel = `ALUOP_SLA;
|
1808 |
|
|
//12'b001000101110,
|
1809 |
|
|
//12'b001000101rrr,
|
1810 |
|
|
12'b001000101xxx: aluop_sel = `ALUOP_SRA;
|
1811 |
|
|
//12'b001000111110,
|
1812 |
|
|
//12'b001000111rrr,
|
1813 |
|
|
12'b001000111xxx: aluop_sel = `ALUOP_SRL;
|
1814 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
1815 |
|
|
endcase
|
1816 |
|
|
end
|
1817 |
|
|
`OF1B: begin
|
1818 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1819 |
|
|
12'b000000100000: aluop_sel = ( !zero_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
1820 |
|
|
12'b000000101000: aluop_sel = ( zero_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
1821 |
|
|
12'b000000110000: aluop_sel = (!carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
1822 |
|
|
12'b000000111000: aluop_sel = ( carry_bit) ? `ALUOP_ADS : `ALUOP_ADD;
|
1823 |
|
|
12'b000000010000,
|
1824 |
|
|
12'b000000011000: aluop_sel = `ALUOP_ADS;
|
1825 |
|
|
12'b000000110110: aluop_sel = `ALUOP_PASS;
|
1826 |
|
|
default: aluop_sel = `ALUOP_ADD;
|
1827 |
|
|
endcase
|
1828 |
|
|
end
|
1829 |
|
|
`OF2A: begin
|
1830 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1831 |
|
|
12'b010000110110,
|
1832 |
|
|
12'b010100110110: aluop_sel = `ALUOP_ADS;
|
1833 |
|
|
default: aluop_sel = `ALUOP_ADD;
|
1834 |
|
|
endcase
|
1835 |
|
|
end
|
1836 |
|
|
`OF2B: begin
|
1837 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1838 |
|
|
12'b000000xx0001,
|
1839 |
|
|
12'b010000100001,
|
1840 |
|
|
12'b010100100001: aluop_sel = `ALUOP_ADD;
|
1841 |
|
|
12'b000011000010,
|
1842 |
|
|
12'b000011000100: aluop_sel = ( !zero_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1843 |
|
|
12'b000011001010,
|
1844 |
|
|
12'b000011001100: aluop_sel = ( zero_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1845 |
|
|
12'b000011010010,
|
1846 |
|
|
12'b000011010100: aluop_sel = (!carry_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1847 |
|
|
12'b000011011010,
|
1848 |
|
|
12'b000011011100: aluop_sel = ( carry_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1849 |
|
|
12'b000011100010,
|
1850 |
|
|
12'b000011100100: aluop_sel = ( !par_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1851 |
|
|
12'b000011101010,
|
1852 |
|
|
12'b000011101100: aluop_sel = ( par_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1853 |
|
|
12'b000011110010,
|
1854 |
|
|
12'b000011110100: aluop_sel = ( !sign_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1855 |
|
|
12'b000011111010,
|
1856 |
|
|
12'b000011111100: aluop_sel = ( sign_bit) ? `ALUOP_PASS : `ALUOP_ADD;
|
1857 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
1858 |
|
|
endcase
|
1859 |
|
|
end
|
1860 |
|
|
`IF3A: aluop_sel = `ALUOP_ADS;
|
1861 |
|
|
`ADR1: begin
|
1862 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1863 |
|
|
12'b000000100010,
|
1864 |
|
|
12'b000000101010,
|
1865 |
|
|
12'b000000110010,
|
1866 |
|
|
12'b000000111010,
|
1867 |
|
|
12'b000011010011,
|
1868 |
|
|
12'b000011011011,
|
1869 |
|
|
12'b0001xxxxxxxx,
|
1870 |
|
|
12'b010000100010,
|
1871 |
|
|
12'b010000101010,
|
1872 |
|
|
12'b010100100010,
|
1873 |
|
|
12'b010100101010,
|
1874 |
|
|
12'b1xxx01xx0011,
|
1875 |
|
|
12'b1xxx01xx1011: aluop_sel = `ALUOP_PASS;
|
1876 |
|
|
default: aluop_sel = `ALUOP_ADS;
|
1877 |
|
|
endcase
|
1878 |
|
|
end
|
1879 |
|
|
`ADR2: begin
|
1880 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1881 |
|
|
12'b1xxx10100000,
|
1882 |
|
|
12'b1xxx10100001,
|
1883 |
|
|
12'b1xxx10101000,
|
1884 |
|
|
12'b1xxx10101001,
|
1885 |
|
|
12'b1xxx10110000,
|
1886 |
|
|
12'b1xxx10110001,
|
1887 |
|
|
12'b1xxx10111000,
|
1888 |
|
|
12'b1xxx10111001: aluop_sel = `ALUOP_ADD;
|
1889 |
|
|
12'b1xxx10100010,
|
1890 |
|
|
12'b1xxx10101010,
|
1891 |
|
|
12'b1xxx10110010,
|
1892 |
|
|
12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
|
1893 |
|
|
12'b1xxx10100011,
|
1894 |
|
|
12'b1xxx10101011,
|
1895 |
|
|
12'b1xxx10110011,
|
1896 |
|
|
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
|
1897 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
1898 |
|
|
endcase
|
1899 |
|
|
end
|
1900 |
|
|
`RD1A: begin
|
1901 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1902 |
|
|
12'b1xxx10100000,
|
1903 |
|
|
12'b1xxx10100010,
|
1904 |
|
|
12'b1xxx10100011,
|
1905 |
|
|
12'b1xxx10101000,
|
1906 |
|
|
12'b1xxx10101010,
|
1907 |
|
|
12'b1xxx10101011,
|
1908 |
|
|
12'b1xxx10110000,
|
1909 |
|
|
12'b1xxx10110010,
|
1910 |
|
|
12'b1xxx10110011,
|
1911 |
|
|
12'b1xxx10111000,
|
1912 |
|
|
12'b1xxx10111010,
|
1913 |
|
|
12'b1xxx10111011: aluop_sel = `ALUOP_PASS;
|
1914 |
|
|
default: aluop_sel = `ALUOP_ADD;
|
1915 |
|
|
endcase
|
1916 |
|
|
end
|
1917 |
|
|
`RD1B: begin
|
1918 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1919 |
|
|
12'b1xxx10100001,
|
1920 |
|
|
12'b1xxx10101001,
|
1921 |
|
|
12'b1xxx10110001,
|
1922 |
|
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
1923 |
|
|
12'b1xxx10100000,
|
1924 |
|
|
12'b1xxx10101000,
|
1925 |
|
|
12'b1xxx10110000,
|
1926 |
|
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
1927 |
|
|
default: aluop_sel = `ALUOP_BAND;
|
1928 |
|
|
endcase
|
1929 |
|
|
end
|
1930 |
|
|
`RD2A: begin
|
1931 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1932 |
|
|
12'b000011001001,
|
1933 |
|
|
12'b000011xxx000,
|
1934 |
|
|
12'b000011xx0001,
|
1935 |
|
|
12'b0001xxxxxxxx,
|
1936 |
|
|
12'b010011100001,
|
1937 |
|
|
12'b010111100001,
|
1938 |
|
|
12'b1xxx01000101,
|
1939 |
|
|
12'b1xxx01001101,
|
1940 |
|
|
12'b1xxx10100000,
|
1941 |
|
|
12'b1xxx10100010,
|
1942 |
|
|
12'b1xxx10101000,
|
1943 |
|
|
12'b1xxx10101010,
|
1944 |
|
|
12'b1xxx10110000,
|
1945 |
|
|
12'b1xxx10110010,
|
1946 |
|
|
12'b1xxx10111000,
|
1947 |
|
|
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
|
1948 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
1949 |
|
|
endcase
|
1950 |
|
|
end
|
1951 |
|
|
`RD2B: begin
|
1952 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
1953 |
|
|
12'b000000xxx100,//12'b000000110100,12'b000000rrr100,
|
1954 |
|
|
12'b010000110100,
|
1955 |
|
|
12'b010100110100: aluop_sel = `ALUOP_BADD;
|
1956 |
|
|
12'b001010xxxxxx,//12'b001010xxx110,12'b001010xxxrrr,
|
1957 |
|
|
12'b011010xxx110,
|
1958 |
|
|
12'b011110xxx110,
|
1959 |
|
|
12'b1xxx10100010,
|
1960 |
|
|
12'b1xxx10100011,
|
1961 |
|
|
12'b1xxx10101010,
|
1962 |
|
|
12'b1xxx10101011,
|
1963 |
|
|
12'b1xxx10110010,
|
1964 |
|
|
12'b1xxx10110011,
|
1965 |
|
|
12'b1xxx10111010,
|
1966 |
|
|
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
|
1967 |
|
|
12'b000000xxx101,//12'b000000110101,12'b000000rrr101,
|
1968 |
|
|
12'b010000110101,
|
1969 |
|
|
12'b010100110101: aluop_sel = `ALUOP_BDEC;
|
1970 |
|
|
12'b001011xxxxxx,//12'b001011xxx110,12'b001011xxxrrr,
|
1971 |
|
|
12'b011011xxx110,
|
1972 |
|
|
12'b011111xxx110: aluop_sel = `ALUOP_BOR;
|
1973 |
|
|
12'b1xxx10100001,
|
1974 |
|
|
12'b1xxx10101001,
|
1975 |
|
|
12'b1xxx10110001,
|
1976 |
|
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
1977 |
|
|
12'b000011001001,
|
1978 |
|
|
12'b000011100011,
|
1979 |
|
|
12'b000011xxx000,
|
1980 |
|
|
12'b0001xxxxxxxx,
|
1981 |
|
|
12'b010011100011,
|
1982 |
|
|
12'b010111100011,
|
1983 |
|
|
12'b1xxx01000101,
|
1984 |
|
|
12'b1xxx01001101,
|
1985 |
|
|
12'b1xxx10100000,
|
1986 |
|
|
12'b1xxx10101000,
|
1987 |
|
|
12'b1xxx10110000,
|
1988 |
|
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
1989 |
|
|
12'b001000010xxx,//12'b001000010110,12'b001000010rrr,
|
1990 |
|
|
12'b011000010110,
|
1991 |
|
|
12'b011100010110: aluop_sel = `ALUOP_RL;
|
1992 |
|
|
12'b001000000xxx,//12'b001000000110,12'b001000000rrr,
|
1993 |
|
|
12'b011000000110,
|
1994 |
|
|
12'b011100000110: aluop_sel = `ALUOP_RLC;
|
1995 |
|
|
12'b1xxx01101111: aluop_sel = `ALUOP_RLD1;
|
1996 |
|
|
12'b001000011xxx,//12'b001000011110,12'b001000011rrr,
|
1997 |
|
|
12'b011000011110,
|
1998 |
|
|
12'b011100011110: aluop_sel = `ALUOP_RR;
|
1999 |
|
|
12'b001000001xxx,//12'b001000001110,12'b001000001rrr,
|
2000 |
|
|
12'b011000001110,
|
2001 |
|
|
12'b011100001110: aluop_sel = `ALUOP_RRC;
|
2002 |
|
|
12'b1xxx01100111: aluop_sel = `ALUOP_RRD1;
|
2003 |
|
|
12'b001000100xxx,//12'b001000100110,12'b001000100rrr,
|
2004 |
|
|
12'b011000100110,
|
2005 |
|
|
12'b011100100110: aluop_sel = `ALUOP_SLA;
|
2006 |
|
|
12'b001000101xxx,//12'b001000101110,12'b001000101rrr,
|
2007 |
|
|
12'b011000101110,
|
2008 |
|
|
12'b011100101110: aluop_sel = `ALUOP_SRA;
|
2009 |
|
|
12'b001000111xxx,//12'b001000111110,12'b001000111rrr,
|
2010 |
|
|
12'b011000111110,
|
2011 |
|
|
12'b011100111110: aluop_sel = `ALUOP_SRL;
|
2012 |
|
|
default: aluop_sel = `ALUOP_ADD;
|
2013 |
|
|
endcase
|
2014 |
|
|
end
|
2015 |
|
|
`WR1A: begin
|
2016 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2017 |
|
|
12'b1xxx10100010,
|
2018 |
|
|
12'b1xxx10101010,
|
2019 |
|
|
12'b1xxx10110010,
|
2020 |
|
|
12'b1xxx10111010: aluop_sel = `ALUOP_PASS;
|
2021 |
|
|
default: aluop_sel = `ALUOP_ADD;
|
2022 |
|
|
endcase
|
2023 |
|
|
end
|
2024 |
|
|
`WR1B: begin
|
2025 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2026 |
|
|
12'b1xxx10100000,
|
2027 |
|
|
12'b1xxx10100010,
|
2028 |
|
|
12'b1xxx10100011,
|
2029 |
|
|
12'b1xxx10101000,
|
2030 |
|
|
12'b1xxx10101010,
|
2031 |
|
|
12'b1xxx10101011,
|
2032 |
|
|
12'b1xxx10110000,
|
2033 |
|
|
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
|
2034 |
|
|
12'b1xxx10110010,
|
2035 |
|
|
12'b1xxx10110011,
|
2036 |
|
|
12'b1xxx10111010,
|
2037 |
|
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
2038 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
2039 |
|
|
endcase
|
2040 |
|
|
end
|
2041 |
|
|
`WR2A: begin
|
2042 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2043 |
|
|
12'b1xxx10100000,
|
2044 |
|
|
12'b1xxx10100011,
|
2045 |
|
|
12'b1xxx10101000,
|
2046 |
|
|
12'b1xxx10101011,
|
2047 |
|
|
12'b1xxx10110000,
|
2048 |
|
|
12'b1xxx10110011,
|
2049 |
|
|
12'b1xxx10111000,
|
2050 |
|
|
12'b1xxx10111011: aluop_sel = `ALUOP_ADD;
|
2051 |
|
|
12'b000011xxx111,
|
2052 |
|
|
12'b0001xxxxxxxx: aluop_sel = `ALUOP_APAS;
|
2053 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
2054 |
|
|
endcase
|
2055 |
|
|
end
|
2056 |
|
|
`WR2B: begin
|
2057 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2058 |
|
|
12'b1xxx10100010,
|
2059 |
|
|
12'b1xxx10100011,
|
2060 |
|
|
12'b1xxx10101010,
|
2061 |
|
|
12'b1xxx10101011,
|
2062 |
|
|
12'b1xxx10110010,
|
2063 |
|
|
12'b1xxx10110011,
|
2064 |
|
|
12'b1xxx10111010,
|
2065 |
|
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
2066 |
|
|
default: aluop_sel = `ALUOP_ADD;
|
2067 |
|
|
endcase
|
2068 |
|
|
end
|
2069 |
|
|
// `BLK1,
|
2070 |
|
|
// `BLK2,
|
2071 |
|
|
// `PCA,
|
2072 |
|
|
// `PCO: aluop_sel = `ALUOP_ADD;
|
2073 |
|
|
`IF1A: begin
|
2074 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2075 |
|
|
12'b1xxx10100000,
|
2076 |
|
|
12'b1xxx10100010,
|
2077 |
|
|
12'b1xxx10101000,
|
2078 |
|
|
12'b1xxx10101010,
|
2079 |
|
|
12'b1xxx10110000,
|
2080 |
|
|
12'b1xxx10110010,
|
2081 |
|
|
12'b1xxx10111000,
|
2082 |
|
|
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
|
2083 |
|
|
12'b000010001xxx,
|
2084 |
|
|
12'b000011001110,
|
2085 |
|
|
12'b010x10001110: aluop_sel = `ALUOP_BADC;
|
2086 |
|
|
12'b000010000xxx,
|
2087 |
|
|
12'b000011000110,
|
2088 |
|
|
12'b010x10000110,
|
2089 |
|
|
12'b1xxx10100011,
|
2090 |
|
|
12'b1xxx10101011,
|
2091 |
|
|
12'b1xxx10110011,
|
2092 |
|
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
2093 |
|
|
12'b000010100xxx,
|
2094 |
|
|
12'b001001xxxxxx,
|
2095 |
|
|
12'b010x10100110,
|
2096 |
|
|
12'b011x01xxx110,
|
2097 |
|
|
12'b000011100110,
|
2098 |
|
|
12'b1xxx01xxx000: aluop_sel = `ALUOP_BAND;
|
2099 |
|
|
12'b000010110xxx,
|
2100 |
|
|
12'b010x10110110,
|
2101 |
|
|
12'b000011110110: aluop_sel = `ALUOP_BOR;
|
2102 |
|
|
12'b000010011xxx,
|
2103 |
|
|
12'b010x10011110,
|
2104 |
|
|
12'b000011011110: aluop_sel = `ALUOP_BSBC;
|
2105 |
|
|
12'b000010010xxx,
|
2106 |
|
|
12'b000010111xxx,
|
2107 |
|
|
12'b000011010110,
|
2108 |
|
|
12'b010x10010110,
|
2109 |
|
|
12'b010x10111110,
|
2110 |
|
|
12'b000011111110: aluop_sel = `ALUOP_BSUB;
|
2111 |
|
|
12'b000010101xxx,
|
2112 |
|
|
12'b010x10101110,
|
2113 |
|
|
12'b000011101110: aluop_sel = `ALUOP_BXOR;
|
2114 |
|
|
12'b1xxx01101111: aluop_sel = `ALUOP_RLD2;
|
2115 |
|
|
12'b1xxx01100111: aluop_sel = `ALUOP_RRD2;
|
2116 |
|
|
default: aluop_sel = `ALUOP_PASS;
|
2117 |
|
|
endcase
|
2118 |
|
|
end
|
2119 |
|
|
`INTB: aluop_sel = `ALUOP_PASS;
|
2120 |
|
|
default: aluop_sel = `ALUOP_ADD;
|
2121 |
|
|
endcase
|
2122 |
|
|
end
|
2123 |
|
|
|
2124 |
|
|
/*****************************************************************************************/
|
2125 |
|
|
/* */
|
2126 |
|
|
/* alu a input control */
|
2127 |
|
|
/* */
|
2128 |
|
|
/*****************************************************************************************/
|
2129 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
|
2130 |
|
|
tflg_reg or zero_bit) begin
|
2131 |
|
|
casex (state_reg) //synopsys parallel_case
|
2132 |
|
|
`DEC1: begin
|
2133 |
|
|
casex (inst_reg) //synopsys parallel_case
|
2134 |
|
|
8'b10000xxx,
|
2135 |
|
|
8'b10001xxx,
|
2136 |
|
|
8'b10010xxx,
|
2137 |
|
|
8'b10011xxx,
|
2138 |
|
|
8'b10100xxx,
|
2139 |
|
|
8'b10101xxx,
|
2140 |
|
|
8'b10110xxx,
|
2141 |
|
|
8'b10111xxx: alua_sel = `ALUA_AA;
|
2142 |
|
|
8'b00100111: alua_sel = `ALUA_DAA;
|
2143 |
|
|
8'b00xx1001: alua_sel = `ALUA_HL;
|
2144 |
|
|
8'b00010000,
|
2145 |
|
|
8'b00101111,
|
2146 |
|
|
8'b00xxx101,
|
2147 |
|
|
8'b00xx1011,
|
2148 |
|
|
8'b11xx0101,
|
2149 |
|
|
8'b11xxx111: alua_sel = `ALUA_M1;
|
2150 |
|
|
default: alua_sel = `ALUA_ONE;
|
2151 |
|
|
endcase
|
2152 |
|
|
end
|
2153 |
|
|
// `IF2B: alua_sel = `ALUA_ONE;
|
2154 |
|
|
`DEC2: begin
|
2155 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2156 |
|
|
12'b1xxx01xx0010,
|
2157 |
|
|
12'b1xxx01xx1010: alua_sel = `ALUA_HL;
|
2158 |
|
|
12'b1xxx01010111: alua_sel = `ALUA_II;
|
2159 |
|
|
12'b010000xx1001: alua_sel = `ALUA_IX;
|
2160 |
|
|
12'b010100xx1001: alua_sel = `ALUA_IY;
|
2161 |
|
|
12'b010000101011,
|
2162 |
|
|
12'b010011100101,
|
2163 |
|
|
12'b010100101011,
|
2164 |
|
|
12'b010111100101: alua_sel = `ALUA_M1;
|
2165 |
|
|
12'b010000100011,
|
2166 |
|
|
12'b010100100011: alua_sel = `ALUA_ONE;
|
2167 |
|
|
12'b1xxx01011111: alua_sel = `ALUA_RR;
|
2168 |
|
|
12'b1xxx01000100: alua_sel = `ALUA_ZER;
|
2169 |
|
|
default: alua_sel = `ALUA_BIT;
|
2170 |
|
|
endcase
|
2171 |
|
|
end
|
2172 |
|
|
`OF1B: begin
|
2173 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2174 |
|
|
12'b000000100000: alua_sel = ( !zero_bit) ? `ALUA_PC : `ALUA_ONE;
|
2175 |
|
|
12'b000000101000: alua_sel = ( zero_bit) ? `ALUA_PC : `ALUA_ONE;
|
2176 |
|
|
12'b000000110000: alua_sel = (!carry_bit) ? `ALUA_PC : `ALUA_ONE;
|
2177 |
|
|
12'b000000111000: alua_sel = ( carry_bit) ? `ALUA_PC : `ALUA_ONE;
|
2178 |
|
|
12'b000000010000,
|
2179 |
|
|
12'b000000011000: alua_sel = `ALUA_PC;
|
2180 |
|
|
default: alua_sel = `ALUA_ONE;
|
2181 |
|
|
endcase
|
2182 |
|
|
end
|
2183 |
|
|
`OF2A: begin
|
2184 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2185 |
|
|
12'b010000110110: alua_sel = `ALUA_IX;
|
2186 |
|
|
12'b010100110110: alua_sel = `ALUA_IY;
|
2187 |
|
|
default: alua_sel = `ALUA_M1;
|
2188 |
|
|
endcase
|
2189 |
|
|
end
|
2190 |
|
|
// `OF2B: alua_sel = `ALUA_ONE;
|
2191 |
|
|
`IF3A: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
|
2192 |
|
|
`ADR1: alua_sel = (page_reg[2]) ? ((page_reg[0]) ? `ALUA_IY : `ALUA_IX) : `ALUA_M1;
|
2193 |
|
|
`ADR2: alua_sel = `ALUA_M1;
|
2194 |
|
|
// `RD1A: alua_sel = `ALUA_ONE;
|
2195 |
|
|
`RD1B: begin
|
2196 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2197 |
|
|
12'b1xxx10100001,
|
2198 |
|
|
12'b1xxx10101001,
|
2199 |
|
|
12'b1xxx10110001,
|
2200 |
|
|
12'b1xxx10111001: alua_sel = `ALUA_AA;
|
2201 |
|
|
default: alua_sel = `ALUA_M1;
|
2202 |
|
|
endcase
|
2203 |
|
|
end
|
2204 |
|
|
`RD2A: begin
|
2205 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2206 |
|
|
12'b0001xxxxxxxx,
|
2207 |
|
|
12'b1xxx10101000,
|
2208 |
|
|
12'b1xxx10101010,
|
2209 |
|
|
12'b1xxx10111000,
|
2210 |
|
|
12'b1xxx10111010: alua_sel = `ALUA_M1;
|
2211 |
|
|
default: alua_sel = `ALUA_ONE;
|
2212 |
|
|
endcase
|
2213 |
|
|
end
|
2214 |
|
|
`RD2B: begin
|
2215 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2216 |
|
|
12'b1xxx01100111,
|
2217 |
|
|
12'b1xxx01101111,
|
2218 |
|
|
12'b1xxx10100001,
|
2219 |
|
|
12'b1xxx10101001,
|
2220 |
|
|
12'b1xxx10110001,
|
2221 |
|
|
12'b1xxx10111001: alua_sel = `ALUA_AA;
|
2222 |
|
|
12'b001010xxxxxx,//12'b001010xxx110,12'b001010xxxrrr,
|
2223 |
|
|
12'b001011xxxxxx,//12'b001011xxx110,12'b001011xxxrrr,
|
2224 |
|
|
12'b011010xxx110,
|
2225 |
|
|
12'b011011xxx110,
|
2226 |
|
|
12'b011110xxx110,
|
2227 |
|
|
12'b011111xxx110: alua_sel = `ALUA_BIT;
|
2228 |
|
|
12'b000000xxx101,//12'b000000110101,12'b000000rrr101,
|
2229 |
|
|
12'b010000110101,
|
2230 |
|
|
12'b010100110101,
|
2231 |
|
|
12'b1xxx10100010,
|
2232 |
|
|
12'b1xxx10100011,
|
2233 |
|
|
12'b1xxx10101010,
|
2234 |
|
|
12'b1xxx10101011,
|
2235 |
|
|
12'b1xxx10110010,
|
2236 |
|
|
12'b1xxx10110011,
|
2237 |
|
|
12'b1xxx10111010,
|
2238 |
|
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
2239 |
|
|
default: alua_sel = `ALUA_ONE;
|
2240 |
|
|
endcase
|
2241 |
|
|
end
|
2242 |
|
|
`WR1A: begin
|
2243 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2244 |
|
|
12'b000000100010,
|
2245 |
|
|
12'b000011100011,
|
2246 |
|
|
12'b010000100010,
|
2247 |
|
|
12'b010011100011,
|
2248 |
|
|
12'b010100100010,
|
2249 |
|
|
12'b010111100011,
|
2250 |
|
|
12'b1xxx01xx0011,
|
2251 |
|
|
12'b1xxx10100000,
|
2252 |
|
|
12'b1xxx10100011,
|
2253 |
|
|
12'b1xxx10110000,
|
2254 |
|
|
12'b1xxx10110011: alua_sel = `ALUA_ONE;
|
2255 |
|
|
default: alua_sel = `ALUA_M1;
|
2256 |
|
|
endcase
|
2257 |
|
|
end
|
2258 |
|
|
`WR1B: begin
|
2259 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2260 |
|
|
12'b1xxx10110000,
|
2261 |
|
|
12'b1xxx10110010,
|
2262 |
|
|
12'b1xxx10110011,
|
2263 |
|
|
12'b1xxx10111000,
|
2264 |
|
|
12'b1xxx10111010,
|
2265 |
|
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
2266 |
|
|
default: alua_sel = `ALUA_ONE;
|
2267 |
|
|
endcase
|
2268 |
|
|
end
|
2269 |
|
|
`WR2A: begin
|
2270 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2271 |
|
|
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
|
2272 |
|
|
12'b1xxx10101000,
|
2273 |
|
|
12'b1xxx10101011,
|
2274 |
|
|
12'b1xxx10111000,
|
2275 |
|
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
2276 |
|
|
12'b000011xxx111: alua_sel = `ALUA_RST;
|
2277 |
|
|
default: alua_sel = `ALUA_ONE;
|
2278 |
|
|
endcase
|
2279 |
|
|
end
|
2280 |
|
|
`WR2B: begin
|
2281 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2282 |
|
|
12'b1xxx10100000,
|
2283 |
|
|
12'b1xxx10100010,
|
2284 |
|
|
12'b1xxx10100011,
|
2285 |
|
|
12'b1xxx10101000,
|
2286 |
|
|
12'b1xxx10101010,
|
2287 |
|
|
12'b1xxx10101011,
|
2288 |
|
|
12'b1xxx10110000,
|
2289 |
|
|
12'b1xxx10110010,
|
2290 |
|
|
12'b1xxx10110011,
|
2291 |
|
|
12'b1xxx10111000,
|
2292 |
|
|
12'b1xxx10111010,
|
2293 |
|
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
2294 |
|
|
default: alua_sel = `ALUA_ONE;
|
2295 |
|
|
endcase
|
2296 |
|
|
end
|
2297 |
|
|
`BLK1: begin
|
2298 |
|
|
/*casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2299 |
|
|
12'b1xxx10101001,
|
2300 |
|
|
12'b1xxx10111001: alua_sel = `ALUA_NEG1;
|
2301 |
|
|
12'b1xxx10100001,
|
2302 |
|
|
12'b1xxx10110001: alua_sel = `ALUA_ONE;
|
2303 |
|
|
default: alua_sel = `ALUA_ONE;
|
2304 |
|
|
endcase*/
|
2305 |
|
|
alua_sel = (inst_reg[3]) ? `ALUA_M1 : `ALUA_ONE;
|
2306 |
|
|
end
|
2307 |
|
|
`BLK2: begin
|
2308 |
|
|
/*casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2309 |
|
|
12'b1xxx10110001,
|
2310 |
|
|
12'b1xxx10111001: alua_sel = `ALUA_NEG1;
|
2311 |
|
|
12'b1xxx10100001,
|
2312 |
|
|
12'b1xxx10101001: alua_sel = `ALUA_ONE;
|
2313 |
|
|
default: alua_sel = `ALUA_ONE;
|
2314 |
|
|
endcase*/
|
2315 |
|
|
alua_sel = (inst_reg[4]) ? `ALUA_M1 : `ALUA_ONE;
|
2316 |
|
|
end
|
2317 |
|
|
`PCA: alua_sel = (tflg_reg) ? `ALUA_ZER : `ALUA_M2;
|
2318 |
|
|
// `PCO: alua_sel = `ALUA_ONE;
|
2319 |
|
|
`IF1A: begin
|
2320 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2321 |
|
|
12'b001001xxxxxx,
|
2322 |
|
|
12'b011x01xxx110: alua_sel = `ALUA_BIT;
|
2323 |
|
|
12'b1xxx01xxx000,
|
2324 |
|
|
12'b1xxx10100011,
|
2325 |
|
|
12'b1xxx10101000,
|
2326 |
|
|
12'b1xxx10101010,
|
2327 |
|
|
12'b1xxx10101011,
|
2328 |
|
|
12'b1xxx10110011,
|
2329 |
|
|
12'b1xxx10111000,
|
2330 |
|
|
12'b1xxx10111010,
|
2331 |
|
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
2332 |
|
|
12'b1xxx10100000,
|
2333 |
|
|
12'b1xxx10100010,
|
2334 |
|
|
12'b1xxx10110000,
|
2335 |
|
|
12'b1xxx10110010: alua_sel = `ALUA_ONE;
|
2336 |
|
|
default: alua_sel = `ALUA_AA;
|
2337 |
|
|
endcase
|
2338 |
|
|
end
|
2339 |
|
|
`INTA: alua_sel = `ALUA_M1;
|
2340 |
|
|
default: alua_sel = `ALUA_ONE;
|
2341 |
|
|
endcase
|
2342 |
|
|
end
|
2343 |
|
|
|
2344 |
|
|
/*****************************************************************************************/
|
2345 |
|
|
/* */
|
2346 |
|
|
/* alu b input control */
|
2347 |
|
|
/* */
|
2348 |
|
|
/*****************************************************************************************/
|
2349 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
|
2350 |
|
|
zero_bit) begin
|
2351 |
|
|
casex (state_reg) //synopsys parallel_case
|
2352 |
|
|
`DEC1: begin
|
2353 |
|
|
casex (inst_reg) //synopsys parallel_case
|
2354 |
|
|
8'b00000111,
|
2355 |
|
|
8'b00001111,
|
2356 |
|
|
8'b00010111,
|
2357 |
|
|
8'b00011111,
|
2358 |
|
|
8'b00100111,
|
2359 |
|
|
8'b00101111: alub_sel = `ALUB_AA;
|
2360 |
|
|
8'b00010000: alub_sel = `ALUB_BB;
|
2361 |
|
|
8'b00000010,
|
2362 |
|
|
8'b00001010: alub_sel = `ALUB_BC;
|
2363 |
|
|
8'b00010010,
|
2364 |
|
|
8'b00011010,
|
2365 |
|
|
8'b11101011: alub_sel = `ALUB_DE;
|
2366 |
|
|
8'b11101001,
|
2367 |
|
|
8'b11111001: alub_sel = `ALUB_HL;
|
2368 |
|
|
8'b01xxx000,
|
2369 |
|
|
8'b10xxx000: alub_sel = `ALUB_BB;
|
2370 |
|
|
8'b01xxx001,
|
2371 |
|
|
8'b10xxx001: alub_sel = `ALUB_CC;
|
2372 |
|
|
8'b01xxx010,
|
2373 |
|
|
8'b10xxx010: alub_sel = `ALUB_DD;
|
2374 |
|
|
8'b01xxx011,
|
2375 |
|
|
8'b10xxx011: alub_sel = `ALUB_EE;
|
2376 |
|
|
8'b01xxx100,
|
2377 |
|
|
8'b10xxx100: alub_sel = `ALUB_HH;
|
2378 |
|
|
8'b01xxx101,
|
2379 |
|
|
8'b10xxx101: alub_sel = `ALUB_LL;
|
2380 |
|
|
8'b01xxx111,
|
2381 |
|
|
8'b10xxx111: alub_sel = `ALUB_AA;
|
2382 |
|
|
8'b0000010x: alub_sel = `ALUB_BB;
|
2383 |
|
|
8'b0000110x: alub_sel = `ALUB_CC;
|
2384 |
|
|
8'b0001010x: alub_sel = `ALUB_DD;
|
2385 |
|
|
8'b0001110x: alub_sel = `ALUB_EE;
|
2386 |
|
|
8'b0010010x: alub_sel = `ALUB_HH;
|
2387 |
|
|
8'b0010110x: alub_sel = `ALUB_LL;
|
2388 |
|
|
8'b0011110x: alub_sel = `ALUB_AA;
|
2389 |
|
|
8'b00000011,
|
2390 |
|
|
8'b00001001,
|
2391 |
|
|
8'b00001011: alub_sel = `ALUB_BC;
|
2392 |
|
|
8'b00010011,
|
2393 |
|
|
8'b00011001,
|
2394 |
|
|
8'b00011011: alub_sel = `ALUB_DE;
|
2395 |
|
|
8'b00100011,
|
2396 |
|
|
8'b00101001,
|
2397 |
|
|
8'b00101011: alub_sel = `ALUB_HL;
|
2398 |
|
|
8'b00110011,
|
2399 |
|
|
8'b00111001,
|
2400 |
|
|
8'b00111011: alub_sel = `ALUB_SP;
|
2401 |
|
|
8'b11xx0101,
|
2402 |
|
|
8'b11xxx111: alub_sel = `ALUB_SP;
|
2403 |
|
|
default: alub_sel = `ALUB_PC;
|
2404 |
|
|
endcase
|
2405 |
|
|
end
|
2406 |
|
|
`IF2B: alub_sel = `ALUB_PC;
|
2407 |
|
|
`DEC2: begin
|
2408 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2409 |
|
|
12'b1xxx01000100,
|
2410 |
|
|
12'b1xxx01000111,
|
2411 |
|
|
12'b1xxx01001111: alub_sel = `ALUB_AA;
|
2412 |
|
|
12'b1xxx01xxx000,
|
2413 |
|
|
12'b1xxx01xxx001,
|
2414 |
|
|
12'b1xxx10100010,
|
2415 |
|
|
12'b1xxx10101010,
|
2416 |
|
|
12'b1xxx10110010,
|
2417 |
|
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
2418 |
|
|
12'b010000100011,
|
2419 |
|
|
12'b010000101011,
|
2420 |
|
|
12'b010011101001,
|
2421 |
|
|
12'b010011111001: alub_sel = `ALUB_IX;
|
2422 |
|
|
12'b010100100011,
|
2423 |
|
|
12'b010100101011,
|
2424 |
|
|
12'b010111101001,
|
2425 |
|
|
12'b010111111001: alub_sel = `ALUB_IY;
|
2426 |
|
|
12'b1xxx01000101,
|
2427 |
|
|
12'b1xxx01001101: alub_sel = `ALUB_PC;
|
2428 |
|
|
//12'b001000000110,12'b001000000rrr,12'b001000001110,12'b001000001rrr,12'b001000010110,12'b001000010rrr,12'b001000011110,12'b001000011rrr
|
2429 |
|
|
//12'b001000100110,12'b001000100rrr,12'b001000101110,12'b001000101rrr
|
2430 |
|
|
//12'b001000111110,12'b001000111rrr
|
2431 |
|
|
//12'b001001xxx110,12'b001001xxxrrr
|
2432 |
|
|
//12'b001010xxx110,12'b001010xxxrrr,12'b001011xxx110,12'b001011xxxrrr
|
2433 |
|
|
12'b0010000xx000,
|
2434 |
|
|
12'b00100010x000,
|
2435 |
|
|
12'b001000111000,
|
2436 |
|
|
12'b001001xxx000,
|
2437 |
|
|
12'b00101xxxx000: alub_sel = `ALUB_BB;
|
2438 |
|
|
12'b0010000xx001,
|
2439 |
|
|
12'b00100010x001,
|
2440 |
|
|
12'b001000111001,
|
2441 |
|
|
12'b001001xxx001,
|
2442 |
|
|
12'b00101xxxx001: alub_sel = `ALUB_CC;
|
2443 |
|
|
12'b0010000xx010,
|
2444 |
|
|
12'b00100010x010,
|
2445 |
|
|
12'b001000111010,
|
2446 |
|
|
12'b001001xxx010,
|
2447 |
|
|
12'b00101xxxx010: alub_sel = `ALUB_DD;
|
2448 |
|
|
12'b0010000xx011,
|
2449 |
|
|
12'b00100010x011,
|
2450 |
|
|
12'b001000111011,
|
2451 |
|
|
12'b001001xxx011,
|
2452 |
|
|
12'b00101xxxx011: alub_sel = `ALUB_EE;
|
2453 |
|
|
12'b0010000xx100,
|
2454 |
|
|
12'b00100010x100,
|
2455 |
|
|
12'b001000111100,
|
2456 |
|
|
12'b001001xxx100,
|
2457 |
|
|
12'b00101xxxx100: alub_sel = `ALUB_HH;
|
2458 |
|
|
12'b0010000xx101,
|
2459 |
|
|
12'b00100010x101,
|
2460 |
|
|
12'b001000111101,
|
2461 |
|
|
12'b001001xxx101,
|
2462 |
|
|
12'b00101xxxx101: alub_sel = `ALUB_LL;
|
2463 |
|
|
12'b0010000xx111,
|
2464 |
|
|
12'b00100010x111,
|
2465 |
|
|
12'b001000111111,
|
2466 |
|
|
12'b001001xxx111,
|
2467 |
|
|
12'b00101xxxx111: alub_sel = `ALUB_AA;
|
2468 |
|
|
//12'b1xxx01xx0010,
|
2469 |
|
|
//12'b1xxx01xx1010:
|
2470 |
|
|
12'b1xxx0100x010: alub_sel = `ALUB_BC;
|
2471 |
|
|
12'b1xxx0101x010: alub_sel = `ALUB_DE;
|
2472 |
|
|
//12'b1xxx0110x010: alub_sel = `ALUB_HL;
|
2473 |
|
|
12'b1xxx0111x010: alub_sel = `ALUB_SP;
|
2474 |
|
|
12'b010011100101,
|
2475 |
|
|
12'b010111100101: alub_sel = `ALUB_SP;
|
2476 |
|
|
//12'b010000xx1001
|
2477 |
|
|
//12'b010100xx1001
|
2478 |
|
|
12'b010x00001001: alub_sel = `ALUB_BC;
|
2479 |
|
|
12'b010x00011001: alub_sel = `ALUB_DE;
|
2480 |
|
|
12'b010x00101001: alub_sel = (page_reg[0]) ? `ALUB_IY : `ALUB_IX;
|
2481 |
|
|
12'b010x00111001: alub_sel = `ALUB_SP;
|
2482 |
|
|
default: alub_sel = `ALUB_HL;
|
2483 |
|
|
endcase
|
2484 |
|
|
end
|
2485 |
|
|
`OF1B: begin
|
2486 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2487 |
|
|
12'b000000010000,
|
2488 |
|
|
12'b000000011000,
|
2489 |
|
|
12'b000000110110: alub_sel = `ALUB_DIN;
|
2490 |
|
|
12'b000000100000: alub_sel = ( !zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
2491 |
|
|
12'b000000101000: alub_sel = ( zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
2492 |
|
|
12'b000000110000: alub_sel = (!carry_bit) ? `ALUB_DIN : `ALUB_PC;
|
2493 |
|
|
12'b000000111000: alub_sel = ( carry_bit) ? `ALUB_DIN : `ALUB_PC;
|
2494 |
|
|
default: alub_sel = `ALUB_PC;
|
2495 |
|
|
endcase
|
2496 |
|
|
end
|
2497 |
|
|
`OF2A: begin
|
2498 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2499 |
|
|
12'b010000110110,
|
2500 |
|
|
12'b010100110110: alub_sel = `ALUB_DIN;
|
2501 |
|
|
default: alub_sel = `ALUB_SP;
|
2502 |
|
|
endcase
|
2503 |
|
|
end
|
2504 |
|
|
`OF2B: begin
|
2505 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2506 |
|
|
12'b000011000011,
|
2507 |
|
|
12'b010000110110,
|
2508 |
|
|
12'b010100110110: alub_sel = `ALUB_DIN;
|
2509 |
|
|
12'b000011000010: alub_sel = ( !zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
2510 |
|
|
12'b000011001010: alub_sel = ( zero_bit) ? `ALUB_DIN : `ALUB_PC;
|
2511 |
|
|
12'b000011010010: alub_sel = (!carry_bit) ? `ALUB_DIN : `ALUB_PC;
|
2512 |
|
|
12'b000011011010: alub_sel = ( carry_bit) ? `ALUB_DIN : `ALUB_PC;
|
2513 |
|
|
12'b000011100010: alub_sel = ( !par_bit) ? `ALUB_DIN : `ALUB_PC;
|
2514 |
|
|
12'b000011101010: alub_sel = ( par_bit) ? `ALUB_DIN : `ALUB_PC;
|
2515 |
|
|
12'b000011110010: alub_sel = ( !sign_bit) ? `ALUB_DIN : `ALUB_PC;
|
2516 |
|
|
12'b000011111010: alub_sel = ( sign_bit) ? `ALUB_DIN : `ALUB_PC;
|
2517 |
|
|
12'b000011001101: alub_sel = `ALUB_PCH;
|
2518 |
|
|
12'b000011000100: alub_sel = ( !zero_bit) ? `ALUB_PCH : `ALUB_PC;
|
2519 |
|
|
12'b000011001100: alub_sel = ( zero_bit) ? `ALUB_PCH : `ALUB_PC;
|
2520 |
|
|
12'b000011010100: alub_sel = (!carry_bit) ? `ALUB_PCH : `ALUB_PC;
|
2521 |
|
|
12'b000011011100: alub_sel = ( carry_bit) ? `ALUB_PCH : `ALUB_PC;
|
2522 |
|
|
12'b000011100100: alub_sel = ( !par_bit) ? `ALUB_PCH : `ALUB_PC;
|
2523 |
|
|
12'b000011101100: alub_sel = ( par_bit) ? `ALUB_PCH : `ALUB_PC;
|
2524 |
|
|
12'b000011110100: alub_sel = ( !sign_bit) ? `ALUB_PCH : `ALUB_PC;
|
2525 |
|
|
12'b000011111100: alub_sel = ( sign_bit) ? `ALUB_PCH : `ALUB_PC;
|
2526 |
|
|
default: alub_sel = `ALUB_PC;
|
2527 |
|
|
endcase
|
2528 |
|
|
end
|
2529 |
|
|
`IF3A: alub_sel = `ALUB_DIN;
|
2530 |
|
|
`ADR1: begin
|
2531 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2532 |
|
|
12'b000011010011,
|
2533 |
|
|
12'b000011011011: alub_sel = `ALUB_IO;
|
2534 |
|
|
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
|
2535 |
|
|
default: alub_sel = `ALUB_DIN;
|
2536 |
|
|
endcase
|
2537 |
|
|
end
|
2538 |
|
|
`ADR2: begin
|
2539 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2540 |
|
|
12'b000000000010,
|
2541 |
|
|
12'b000000010010,
|
2542 |
|
|
12'b000000110010,
|
2543 |
|
|
12'b000011010011: alub_sel = `ALUB_AA;
|
2544 |
|
|
12'b1xxx10100010,
|
2545 |
|
|
12'b1xxx10100011,
|
2546 |
|
|
12'b1xxx10101010,
|
2547 |
|
|
12'b1xxx10101011,
|
2548 |
|
|
12'b1xxx10110010,
|
2549 |
|
|
12'b1xxx10110011,
|
2550 |
|
|
12'b1xxx10111010,
|
2551 |
|
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
2552 |
|
|
12'b1xxx10100000,
|
2553 |
|
|
12'b1xxx10100001,
|
2554 |
|
|
12'b1xxx10101000,
|
2555 |
|
|
12'b1xxx10101001,
|
2556 |
|
|
12'b1xxx10110000,
|
2557 |
|
|
12'b1xxx10110001,
|
2558 |
|
|
12'b1xxx10111000,
|
2559 |
|
|
12'b1xxx10111001: alub_sel = `ALUB_BC;
|
2560 |
|
|
//12'b000000100010: alub_sel = `ALUB_HL;
|
2561 |
|
|
12'b010000100010: alub_sel = `ALUB_IX;
|
2562 |
|
|
12'b010011100101: alub_sel = `ALUB_IXH;
|
2563 |
|
|
12'b010100100010: alub_sel = `ALUB_IY;
|
2564 |
|
|
12'b010111100101: alub_sel = `ALUB_IYH;
|
2565 |
|
|
12'b000011xxx111: alub_sel = `ALUB_PCH;
|
2566 |
|
|
//12'b000001110110,12'b000001110rrr,
|
2567 |
|
|
//12'b000001rdrrsr,12'b000001rrr110,
|
2568 |
|
|
//12'b010001110rrr,12'b010101110rrr,
|
2569 |
|
|
//12'b1xxx01rrr001
|
2570 |
|
|
12'b000001xxx000,
|
2571 |
|
|
12'b010x01110000,
|
2572 |
|
|
12'b1xxx01000001: alub_sel = `ALUB_BB;
|
2573 |
|
|
12'b000001xxx001,
|
2574 |
|
|
12'b010x01110001,
|
2575 |
|
|
12'b1xxx01001001: alub_sel = `ALUB_CC;
|
2576 |
|
|
12'b000001xxx010,
|
2577 |
|
|
12'b010x01110010,
|
2578 |
|
|
12'b1xxx01010001: alub_sel = `ALUB_DD;
|
2579 |
|
|
12'b000001xxx011,
|
2580 |
|
|
12'b010x01110011,
|
2581 |
|
|
12'b1xxx01011001: alub_sel = `ALUB_EE;
|
2582 |
|
|
12'b000001xxx100,
|
2583 |
|
|
12'b010x01110100,
|
2584 |
|
|
12'b1xxx01100001: alub_sel = `ALUB_HH;
|
2585 |
|
|
12'b000001xxx101,
|
2586 |
|
|
12'b010x01110101,
|
2587 |
|
|
12'b1xxx01101001: alub_sel = `ALUB_LL;
|
2588 |
|
|
//12'b000001xxx110,
|
2589 |
|
|
//12'b010101110110,
|
2590 |
|
|
//12'b1xxx01110001: alub_sel = `ALUB_HL;
|
2591 |
|
|
12'b000001xxx111,
|
2592 |
|
|
12'b010x01110111,
|
2593 |
|
|
12'b1xxx01111001: alub_sel = `ALUB_AA;
|
2594 |
|
|
12'b1xxx01000011: alub_sel = `ALUB_BC;
|
2595 |
|
|
12'b1xxx01010011: alub_sel = `ALUB_DE;
|
2596 |
|
|
//12'b1xxx01100011: alub_sel = `ALUB_HL;
|
2597 |
|
|
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
2598 |
|
|
12'b000011000101: alub_sel = `ALUB_BB;
|
2599 |
|
|
12'b000011010101: alub_sel = `ALUB_DD;
|
2600 |
|
|
12'b000011100101: alub_sel = `ALUB_HH;
|
2601 |
|
|
12'b000011110101: alub_sel = `ALUB_AA;
|
2602 |
|
|
default: alub_sel = `ALUB_HL;
|
2603 |
|
|
endcase
|
2604 |
|
|
end
|
2605 |
|
|
`RD1A: begin
|
2606 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2607 |
|
|
12'b1xxx10100011,
|
2608 |
|
|
12'b1xxx10101011,
|
2609 |
|
|
12'b1xxx10110011,
|
2610 |
|
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
2611 |
|
|
12'b1xxx10100000,
|
2612 |
|
|
12'b1xxx10101000,
|
2613 |
|
|
12'b1xxx10110000,
|
2614 |
|
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
2615 |
|
|
12'b1xxx10100001,
|
2616 |
|
|
12'b1xxx10100010,
|
2617 |
|
|
12'b1xxx10101001,
|
2618 |
|
|
12'b1xxx10101010,
|
2619 |
|
|
12'b1xxx10110001,
|
2620 |
|
|
12'b1xxx10110010,
|
2621 |
|
|
12'b1xxx10111001,
|
2622 |
|
|
12'b1xxx10111010: alub_sel = `ALUB_HL;
|
2623 |
|
|
12'b000000101010,
|
2624 |
|
|
12'b0001xxxxxxxx,
|
2625 |
|
|
12'b010000101010,
|
2626 |
|
|
12'b010100101010,
|
2627 |
|
|
12'b1xxx01xx1011: alub_sel = `ALUB_TMP;
|
2628 |
|
|
default: alub_sel = `ALUB_SP;
|
2629 |
|
|
endcase
|
2630 |
|
|
end
|
2631 |
|
|
`RD1B: alub_sel = `ALUB_DIN;
|
2632 |
|
|
`RD2A: begin
|
2633 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2634 |
|
|
12'b1xxx10100011,
|
2635 |
|
|
12'b1xxx10101011,
|
2636 |
|
|
12'b1xxx10110011,
|
2637 |
|
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
2638 |
|
|
12'b1xxx10100000,
|
2639 |
|
|
12'b1xxx10101000,
|
2640 |
|
|
12'b1xxx10110000,
|
2641 |
|
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
2642 |
|
|
12'b001010xxxxxx,//12'b001010xxx110,12'b001010xxxrrr,
|
2643 |
|
|
12'b1xxx10100001,
|
2644 |
|
|
12'b1xxx10100010,
|
2645 |
|
|
12'b1xxx10101001,
|
2646 |
|
|
12'b1xxx10101010,
|
2647 |
|
|
12'b1xxx10110001,
|
2648 |
|
|
12'b1xxx10110010,
|
2649 |
|
|
12'b1xxx10111001,
|
2650 |
|
|
12'b1xxx10111010: alub_sel = `ALUB_HL;
|
2651 |
|
|
12'b000011001001,
|
2652 |
|
|
12'b000011100011,
|
2653 |
|
|
12'b000011xxx000,
|
2654 |
|
|
12'b000011xx0001,
|
2655 |
|
|
12'b0001xxxxxxxx,
|
2656 |
|
|
12'b010011100001,
|
2657 |
|
|
12'b010011100011,
|
2658 |
|
|
12'b010111100001,
|
2659 |
|
|
12'b010111100011,
|
2660 |
|
|
12'b1xxx01000101,
|
2661 |
|
|
12'b1xxx01001101: alub_sel = `ALUB_SP;
|
2662 |
|
|
default: alub_sel = `ALUB_TMP;
|
2663 |
|
|
endcase
|
2664 |
|
|
end
|
2665 |
|
|
`RD2B: begin
|
2666 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2667 |
|
|
12'b000011100011: alub_sel = `ALUB_HL;
|
2668 |
|
|
12'b010011100011: alub_sel = `ALUB_IX;
|
2669 |
|
|
12'b010111100011: alub_sel = `ALUB_IY;
|
2670 |
|
|
12'b000000001010,
|
2671 |
|
|
12'b000000011010,
|
2672 |
|
|
12'b000000101010,
|
2673 |
|
|
12'b000000111010,
|
2674 |
|
|
12'b000001xxxxxx,//12'b000001rdrrsr,12'b000001rrr110,
|
2675 |
|
|
12'b000010000xxx,//12'b000010000110,12'b000010000rrr,
|
2676 |
|
|
12'b000010001xxx,//12'b000010001110,12'b000010001rrr,
|
2677 |
|
|
12'b000010010xxx,//12'b000010010110,12'b000010010rrr,
|
2678 |
|
|
12'b000010011xxx,//12'b000010011110,12'b000010011rrr,
|
2679 |
|
|
12'b000010100xxx,//12'b000010100110,12'b000010100rrr,
|
2680 |
|
|
12'b000010101xxx,//12'b000010101110,12'b000010101rrr,
|
2681 |
|
|
12'b000010110xxx,//12'b000010110110,12'b000010110rrr,
|
2682 |
|
|
12'b000010111xxx,//12'b000010111110,12'b000010111rrr,
|
2683 |
|
|
12'b000011011011,
|
2684 |
|
|
12'b000011xx0001,
|
2685 |
|
|
12'b001001xxx110,
|
2686 |
|
|
12'b001001xxxxxx,
|
2687 |
|
|
12'b010000101010,
|
2688 |
|
|
12'b010001xxx110,
|
2689 |
|
|
12'b010010000110,
|
2690 |
|
|
12'b010010001110,
|
2691 |
|
|
12'b010010010110,
|
2692 |
|
|
12'b010010011110,
|
2693 |
|
|
12'b010010100110,
|
2694 |
|
|
12'b010010101110,
|
2695 |
|
|
12'b010010110110,
|
2696 |
|
|
12'b010010111110,
|
2697 |
|
|
12'b010011100001,
|
2698 |
|
|
12'b010100101010,
|
2699 |
|
|
12'b010101xxx110,
|
2700 |
|
|
12'b010110000110,
|
2701 |
|
|
12'b010110001110,
|
2702 |
|
|
12'b010110010110,
|
2703 |
|
|
12'b010110011110,
|
2704 |
|
|
12'b010110100110,
|
2705 |
|
|
12'b010110101110,
|
2706 |
|
|
12'b010110110110,
|
2707 |
|
|
12'b010110111110,
|
2708 |
|
|
12'b010111100001,
|
2709 |
|
|
12'b011001xxx110,
|
2710 |
|
|
12'b011101xxx110,
|
2711 |
|
|
12'b1xxx01xxx000,
|
2712 |
|
|
12'b1xxx01xx1011: alub_sel = `ALUB_PC;
|
2713 |
|
|
12'b0001xxxxxxxx: alub_sel = `ALUB_PCH;
|
2714 |
|
|
default: alub_sel = `ALUB_DIN;
|
2715 |
|
|
endcase
|
2716 |
|
|
end
|
2717 |
|
|
`WR1A: begin
|
2718 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2719 |
|
|
12'b1xxx10100010,
|
2720 |
|
|
12'b1xxx10101010,
|
2721 |
|
|
12'b1xxx10110010,
|
2722 |
|
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
2723 |
|
|
12'b1xxx10100000,
|
2724 |
|
|
12'b1xxx10100011,
|
2725 |
|
|
12'b1xxx10101000,
|
2726 |
|
|
12'b1xxx10101011,
|
2727 |
|
|
12'b1xxx10110000,
|
2728 |
|
|
12'b1xxx10110011,
|
2729 |
|
|
12'b1xxx10111000,
|
2730 |
|
|
12'b1xxx10111011: alub_sel = `ALUB_HL;
|
2731 |
|
|
12'b000000100010,
|
2732 |
|
|
12'b010000100010,
|
2733 |
|
|
12'b010100100010,
|
2734 |
|
|
12'b1xxx01xx0011: alub_sel = `ALUB_TMP;
|
2735 |
|
|
default: alub_sel = `ALUB_SP;
|
2736 |
|
|
endcase
|
2737 |
|
|
end
|
2738 |
|
|
`WR1B: begin
|
2739 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2740 |
|
|
12'b1xxx10110010,
|
2741 |
|
|
12'b1xxx10110011,
|
2742 |
|
|
12'b1xxx10111010,
|
2743 |
|
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
2744 |
|
|
12'b1xxx10110000,
|
2745 |
|
|
12'b1xxx10111000: alub_sel = `ALUB_BC;
|
2746 |
|
|
12'b000000100010,
|
2747 |
|
|
12'b000011100011: alub_sel = `ALUB_HH;
|
2748 |
|
|
12'b010011100101: alub_sel = `ALUB_IX;
|
2749 |
|
|
12'b010000100010,
|
2750 |
|
|
12'b010011100011: alub_sel = `ALUB_IXH;
|
2751 |
|
|
12'b010111100101: alub_sel = `ALUB_IY;
|
2752 |
|
|
12'b010100100010,
|
2753 |
|
|
12'b010111100011: alub_sel = `ALUB_IYH;
|
2754 |
|
|
12'b1xxx01000011: alub_sel = `ALUB_BC;
|
2755 |
|
|
12'b1xxx01010011: alub_sel = `ALUB_DE;
|
2756 |
|
|
12'b1xxx01100011: alub_sel = `ALUB_HL;
|
2757 |
|
|
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
2758 |
|
|
12'b000011000101: alub_sel = `ALUB_BC;
|
2759 |
|
|
12'b000011010101: alub_sel = `ALUB_DE;
|
2760 |
|
|
12'b000011100101: alub_sel = `ALUB_HL;
|
2761 |
|
|
12'b000011110101: alub_sel = `ALUB_AF;
|
2762 |
|
|
default: alub_sel = `ALUB_PC;
|
2763 |
|
|
endcase
|
2764 |
|
|
end
|
2765 |
|
|
`WR2A: begin
|
2766 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2767 |
|
|
12'b1xxx10100010,
|
2768 |
|
|
12'b1xxx10101010,
|
2769 |
|
|
12'b1xxx10110010,
|
2770 |
|
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
2771 |
|
|
12'b000011001101,
|
2772 |
|
|
12'b000011xxx100: alub_sel = `ALUB_DIN;
|
2773 |
|
|
default: alub_sel = `ALUB_HL;
|
2774 |
|
|
endcase
|
2775 |
|
|
end
|
2776 |
|
|
`WR2B: begin
|
2777 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2778 |
|
|
12'b1xxx10100010,
|
2779 |
|
|
12'b1xxx10100011,
|
2780 |
|
|
12'b1xxx10101010,
|
2781 |
|
|
12'b1xxx10101011,
|
2782 |
|
|
12'b1xxx10110010,
|
2783 |
|
|
12'b1xxx10110011,
|
2784 |
|
|
12'b1xxx10111010,
|
2785 |
|
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
2786 |
|
|
12'b1xxx10100000,
|
2787 |
|
|
12'b1xxx10101000,
|
2788 |
|
|
12'b1xxx10110000,
|
2789 |
|
|
12'b1xxx10111000: alub_sel = `ALUB_BC;
|
2790 |
|
|
default: alub_sel = `ALUB_PC;
|
2791 |
|
|
endcase
|
2792 |
|
|
end
|
2793 |
|
|
`BLK1: alub_sel = `ALUB_HL;
|
2794 |
|
|
`BLK2: alub_sel = (inst_reg[4]) ? `ALUB_BC : `ALUB_PC;
|
2795 |
|
|
`PCA,
|
2796 |
|
|
`PCO: alub_sel = `ALUB_PC;
|
2797 |
|
|
`IF1A: begin
|
2798 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2799 |
|
|
12'b1xxx10100011,
|
2800 |
|
|
12'b1xxx10101011,
|
2801 |
|
|
12'b1xxx10110011,
|
2802 |
|
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
2803 |
|
|
12'b1xxx10100000,
|
2804 |
|
|
12'b1xxx10101000,
|
2805 |
|
|
12'b1xxx10110000,
|
2806 |
|
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
2807 |
|
|
12'b1xxx10101010,
|
2808 |
|
|
12'b1xxx10111010,
|
2809 |
|
|
12'b1xxx10100010,
|
2810 |
|
|
12'b1xxx10110010: alub_sel = `ALUB_HL;
|
2811 |
|
|
default: alub_sel = `ALUB_DIN;
|
2812 |
|
|
endcase
|
2813 |
|
|
end
|
2814 |
|
|
`INTA: alub_sel = `ALUB_SP;
|
2815 |
|
|
`INTB: alub_sel = `ALUB_PCH;
|
2816 |
|
|
default: alub_sel = `ALUB_PC;
|
2817 |
|
|
endcase
|
2818 |
|
|
end
|
2819 |
|
|
|
2820 |
|
|
/*****************************************************************************************/
|
2821 |
|
|
/* */
|
2822 |
|
|
/* register write control */
|
2823 |
|
|
/* */
|
2824 |
|
|
/*****************************************************************************************/
|
2825 |
|
|
always @ (inst_reg or page_reg or state_reg or carry_bit or par_bit or sign_bit or
|
2826 |
|
|
vector_int or zero_bit) begin
|
2827 |
|
|
casex (state_reg) //synopsys parallel_case
|
2828 |
|
|
`OF1B: begin
|
2829 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2830 |
|
|
12'b000000010000: wr_addr = `WREG_BB;
|
2831 |
|
|
default: wr_addr = `WREG_NUL;
|
2832 |
|
|
endcase
|
2833 |
|
|
end
|
2834 |
|
|
`OF2B: begin
|
2835 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2836 |
|
|
12'b000011001101: wr_addr = `WREG_SP;
|
2837 |
|
|
12'b000011000100: wr_addr = ( !zero_bit) ? `WREG_SP : `WREG_NUL;
|
2838 |
|
|
12'b000011001100: wr_addr = ( zero_bit) ? `WREG_SP : `WREG_NUL;
|
2839 |
|
|
12'b000011010100: wr_addr = (!carry_bit) ? `WREG_SP : `WREG_NUL;
|
2840 |
|
|
12'b000011011100: wr_addr = ( carry_bit) ? `WREG_SP : `WREG_NUL;
|
2841 |
|
|
12'b000011100100: wr_addr = ( !par_bit) ? `WREG_SP : `WREG_NUL;
|
2842 |
|
|
12'b000011101100: wr_addr = ( par_bit) ? `WREG_SP : `WREG_NUL;
|
2843 |
|
|
12'b000011110100: wr_addr = ( !sign_bit) ? `WREG_SP : `WREG_NUL;
|
2844 |
|
|
12'b000011111100: wr_addr = ( sign_bit) ? `WREG_SP : `WREG_NUL;
|
2845 |
|
|
default: wr_addr = `WREG_NUL;
|
2846 |
|
|
endcase
|
2847 |
|
|
end
|
2848 |
|
|
`IF3B: wr_addr = `WREG_TMP;
|
2849 |
|
|
`ADR2: begin
|
2850 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2851 |
|
|
12'b000011xxx111,
|
2852 |
|
|
12'b000011xx0101,
|
2853 |
|
|
12'b010011100101,
|
2854 |
|
|
12'b010111100101: wr_addr = `WREG_SP;
|
2855 |
|
|
12'b000000100010,
|
2856 |
|
|
12'b000000101010,
|
2857 |
|
|
12'b010000100010,
|
2858 |
|
|
12'b010000101010,
|
2859 |
|
|
12'b010000110100,
|
2860 |
|
|
12'b010000110101,
|
2861 |
|
|
12'b010100100010,
|
2862 |
|
|
12'b010100101010,
|
2863 |
|
|
12'b010100110100,
|
2864 |
|
|
12'b010100110101,
|
2865 |
|
|
12'b1xxx01xx0011,
|
2866 |
|
|
12'b1xxx01xx1011: wr_addr = `WREG_TMP;
|
2867 |
|
|
default: wr_addr = `WREG_NUL;
|
2868 |
|
|
endcase
|
2869 |
|
|
end
|
2870 |
|
|
`RD1A: begin
|
2871 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2872 |
|
|
12'b1xxx10100010,
|
2873 |
|
|
12'b1xxx10100011,
|
2874 |
|
|
12'b1xxx10101010,
|
2875 |
|
|
12'b1xxx10101011,
|
2876 |
|
|
12'b1xxx10110010,
|
2877 |
|
|
12'b1xxx10110011,
|
2878 |
|
|
12'b1xxx10111010,
|
2879 |
|
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
2880 |
|
|
12'b1xxx10100000,
|
2881 |
|
|
12'b1xxx10100001,
|
2882 |
|
|
12'b1xxx10101000,
|
2883 |
|
|
12'b1xxx10101001,
|
2884 |
|
|
12'b1xxx10110000,
|
2885 |
|
|
12'b1xxx10110001,
|
2886 |
|
|
12'b1xxx10111000,
|
2887 |
|
|
12'b1xxx10111001: wr_addr = `WREG_BC;
|
2888 |
|
|
default: wr_addr = `WREG_NUL;
|
2889 |
|
|
endcase
|
2890 |
|
|
end
|
2891 |
|
|
`RD1B: begin
|
2892 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2893 |
|
|
12'b000011001001,
|
2894 |
|
|
12'b000011xxx000,
|
2895 |
|
|
12'b000011xx0001,
|
2896 |
|
|
12'b010011100001,
|
2897 |
|
|
12'b010111100001,
|
2898 |
|
|
12'b1xxx01000101,
|
2899 |
|
|
12'b1xxx01001101: wr_addr = `WREG_SP;
|
2900 |
|
|
default: wr_addr = `WREG_NUL;
|
2901 |
|
|
endcase
|
2902 |
|
|
end
|
2903 |
|
|
`RD2A: begin
|
2904 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2905 |
|
|
12'b1xxx10100010,
|
2906 |
|
|
12'b1xxx10100011,
|
2907 |
|
|
12'b1xxx10101010,
|
2908 |
|
|
12'b1xxx10101011,
|
2909 |
|
|
12'b1xxx10110010,
|
2910 |
|
|
12'b1xxx10110011,
|
2911 |
|
|
12'b1xxx10111010,
|
2912 |
|
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
2913 |
|
|
12'b1xxx10100000,
|
2914 |
|
|
12'b1xxx10100001,
|
2915 |
|
|
12'b1xxx10101000,
|
2916 |
|
|
12'b1xxx10101001,
|
2917 |
|
|
12'b1xxx10110000,
|
2918 |
|
|
12'b1xxx10110001,
|
2919 |
|
|
12'b1xxx10111000,
|
2920 |
|
|
12'b1xxx10111001: wr_addr = `WREG_BC;
|
2921 |
|
|
default: wr_addr = `WREG_NUL;
|
2922 |
|
|
endcase
|
2923 |
|
|
end
|
2924 |
|
|
`RD2B: begin
|
2925 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2926 |
|
|
12'b1xxx10100000,
|
2927 |
|
|
12'b1xxx10101000,
|
2928 |
|
|
12'b1xxx10110000,
|
2929 |
|
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
2930 |
|
|
12'b1xxx10100010,
|
2931 |
|
|
12'b1xxx10101010,
|
2932 |
|
|
12'b1xxx10110010,
|
2933 |
|
|
12'b1xxx10111010: wr_addr = `WREG_HL;
|
2934 |
|
|
12'b000011001001,
|
2935 |
|
|
12'b000011xxx000,
|
2936 |
|
|
12'b000011xx0001,
|
2937 |
|
|
12'b0001xxxxxxxx,
|
2938 |
|
|
12'b010011100001,
|
2939 |
|
|
12'b010111100001,
|
2940 |
|
|
12'b1xxx01000101,
|
2941 |
|
|
12'b1xxx01001101: wr_addr = `WREG_SP;
|
2942 |
|
|
default: wr_addr = `WREG_NUL;
|
2943 |
|
|
endcase
|
2944 |
|
|
end
|
2945 |
|
|
//`WR1A: wr_addr = `WREG_NUL;
|
2946 |
|
|
`WR1B: begin
|
2947 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2948 |
|
|
12'b1xxx10100000,
|
2949 |
|
|
12'b1xxx10100011,
|
2950 |
|
|
12'b1xxx10101000,
|
2951 |
|
|
12'b1xxx10101011,
|
2952 |
|
|
12'b1xxx10110000,
|
2953 |
|
|
12'b1xxx10110011,
|
2954 |
|
|
12'b1xxx10111000,
|
2955 |
|
|
12'b1xxx10111011: wr_addr = `WREG_HL;
|
2956 |
|
|
12'b000011001101,
|
2957 |
|
|
12'b000011xxx100,
|
2958 |
|
|
12'b000011xxx111,
|
2959 |
|
|
12'b000011xx0101,
|
2960 |
|
|
12'b0001xxxxxxxx,
|
2961 |
|
|
12'b010011100101,
|
2962 |
|
|
12'b010111100101: wr_addr = `WREG_SP;
|
2963 |
|
|
default: wr_addr = `WREG_NUL;
|
2964 |
|
|
endcase
|
2965 |
|
|
end
|
2966 |
|
|
//`WR2A: wr_addr = `WREG_NUL;
|
2967 |
|
|
`WR2B: begin
|
2968 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2969 |
|
|
12'b1xxx10100000,
|
2970 |
|
|
12'b1xxx10100011,
|
2971 |
|
|
12'b1xxx10101000,
|
2972 |
|
|
12'b1xxx10101011,
|
2973 |
|
|
12'b1xxx10110000,
|
2974 |
|
|
12'b1xxx10110011,
|
2975 |
|
|
12'b1xxx10111000,
|
2976 |
|
|
12'b1xxx10111011: wr_addr = `WREG_HL;
|
2977 |
|
|
default: wr_addr = `WREG_NUL;
|
2978 |
|
|
endcase
|
2979 |
|
|
end
|
2980 |
|
|
//`BLK1: wr_addr = `WREG_NUL;
|
2981 |
|
|
`BLK2: begin
|
2982 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2983 |
|
|
12'b1xxx10100001,
|
2984 |
|
|
12'b1xxx10101001,
|
2985 |
|
|
12'b1xxx10110001,
|
2986 |
|
|
12'b1xxx10111001: wr_addr = `WREG_HL;
|
2987 |
|
|
default: wr_addr = `WREG_NUL;
|
2988 |
|
|
endcase
|
2989 |
|
|
end
|
2990 |
|
|
//`PCA: wr_addr = `WREG_NUL;
|
2991 |
|
|
//`PCO: wr_addr = `WREG_NUL;
|
2992 |
|
|
`IF1B: begin
|
2993 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
2994 |
|
|
12'b000000000111,
|
2995 |
|
|
12'b000000001010,
|
2996 |
|
|
12'b000000001111,
|
2997 |
|
|
12'b000000010111,
|
2998 |
|
|
12'b000000011010,
|
2999 |
|
|
12'b000000011111,
|
3000 |
|
|
12'b000000100111,
|
3001 |
|
|
12'b000000101111,
|
3002 |
|
|
12'b000000111010,
|
3003 |
|
|
12'b000010000xxx,
|
3004 |
|
|
12'b000010001xxx,
|
3005 |
|
|
12'b000010010xxx,
|
3006 |
|
|
12'b000010011xxx,
|
3007 |
|
|
12'b000010100xxx,
|
3008 |
|
|
12'b000010101xxx,
|
3009 |
|
|
12'b000010110xxx,
|
3010 |
|
|
12'b000011000110,
|
3011 |
|
|
12'b000011001110,
|
3012 |
|
|
12'b000011010110,
|
3013 |
|
|
12'b000011011011,
|
3014 |
|
|
12'b010x10000110,
|
3015 |
|
|
12'b010x10001110,
|
3016 |
|
|
12'b010x10010110,
|
3017 |
|
|
12'b010x10011110,
|
3018 |
|
|
12'b010x10100110,
|
3019 |
|
|
12'b010x10101110,
|
3020 |
|
|
12'b010x10110110,
|
3021 |
|
|
12'b000011011110,
|
3022 |
|
|
12'b000011100110,
|
3023 |
|
|
12'b1xxx01000100,
|
3024 |
|
|
12'b1xxx01010111,
|
3025 |
|
|
12'b1xxx01011111,
|
3026 |
|
|
12'b1xxx01100111,
|
3027 |
|
|
12'b1xxx01101111,
|
3028 |
|
|
12'b000011101110,
|
3029 |
|
|
12'b000011110110: wr_addr = `WREG_AA;
|
3030 |
|
|
12'b1xxx10100011,
|
3031 |
|
|
12'b1xxx10101011,
|
3032 |
|
|
12'b1xxx10110011,
|
3033 |
|
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
3034 |
|
|
12'b000000000001,
|
3035 |
|
|
12'b1xxx01001011: wr_addr = `WREG_BC;
|
3036 |
|
|
12'b000000010001,
|
3037 |
|
|
12'b1xxx01011011: wr_addr = `WREG_DE;
|
3038 |
|
|
12'b000000100001,
|
3039 |
|
|
12'b1xxx01101011: wr_addr = `WREG_HL;
|
3040 |
|
|
12'b000000110001,
|
3041 |
|
|
12'b1xxx01111011: wr_addr = `WREG_SP;
|
3042 |
|
|
12'b1xxx10100000,
|
3043 |
|
|
12'b1xxx10101000,
|
3044 |
|
|
12'b1xxx10110000,
|
3045 |
|
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
3046 |
|
|
12'b000011101011: wr_addr = `WREG_DEHL;
|
3047 |
|
|
12'b000000101010,
|
3048 |
|
|
12'b000000xx1001,
|
3049 |
|
|
12'b000011100011,
|
3050 |
|
|
12'b1xxx01xx0010,
|
3051 |
|
|
12'b1xxx01xx1010,
|
3052 |
|
|
12'b1xxx10100010,
|
3053 |
|
|
12'b1xxx10101010,
|
3054 |
|
|
12'b1xxx10110010,
|
3055 |
|
|
12'b1xxx10111010: wr_addr = `WREG_HL;
|
3056 |
|
|
12'b1xxx01000111: wr_addr = `WREG_II;
|
3057 |
|
|
12'b010000100001,
|
3058 |
|
|
12'b010000100011,
|
3059 |
|
|
12'b010000101010,
|
3060 |
|
|
12'b010000101011,
|
3061 |
|
|
12'b010000xx1001,
|
3062 |
|
|
12'b010011100001,
|
3063 |
|
|
12'b010011100011: wr_addr = `WREG_IX;
|
3064 |
|
|
12'b010100100001,
|
3065 |
|
|
12'b010100100011,
|
3066 |
|
|
12'b010100101010,
|
3067 |
|
|
12'b010100101011,
|
3068 |
|
|
12'b010100xx1001,
|
3069 |
|
|
12'b010111100001,
|
3070 |
|
|
12'b010111100011: wr_addr = `WREG_IY;
|
3071 |
|
|
12'b1xxx01001111: wr_addr = `WREG_RR;
|
3072 |
|
|
12'b0010000xx000,
|
3073 |
|
|
12'b00100010x000,
|
3074 |
|
|
12'b001000111000,
|
3075 |
|
|
12'b00101xxxx000: wr_addr = `WREG_BB;
|
3076 |
|
|
12'b0010000xx001,
|
3077 |
|
|
12'b00100010x001,
|
3078 |
|
|
12'b001000111001,
|
3079 |
|
|
12'b00101xxxx001: wr_addr = `WREG_CC;
|
3080 |
|
|
12'b0010000xx010,
|
3081 |
|
|
12'b00100010x010,
|
3082 |
|
|
12'b001000111010,
|
3083 |
|
|
12'b00101xxxx010: wr_addr = `WREG_DD;
|
3084 |
|
|
12'b0010000xx011,
|
3085 |
|
|
12'b00100010x011,
|
3086 |
|
|
12'b001000111011,
|
3087 |
|
|
12'b00101xxxx011: wr_addr = `WREG_EE;
|
3088 |
|
|
12'b0010000xx100,
|
3089 |
|
|
12'b00100010x100,
|
3090 |
|
|
12'b001000111100,
|
3091 |
|
|
12'b00101xxxx100: wr_addr = `WREG_HH;
|
3092 |
|
|
12'b0010000xx101,
|
3093 |
|
|
12'b00100010x101,
|
3094 |
|
|
12'b001000111101,
|
3095 |
|
|
12'b00101xxxx101: wr_addr = `WREG_LL;
|
3096 |
|
|
12'b0010000xx111,
|
3097 |
|
|
12'b00100010x111,
|
3098 |
|
|
12'b001000111111,
|
3099 |
|
|
12'b00101xxxx111: wr_addr = `WREG_AA;
|
3100 |
|
|
12'b00000000010x,
|
3101 |
|
|
12'b000000000110,
|
3102 |
|
|
12'b000001000xxx,
|
3103 |
|
|
12'b010x01000110,
|
3104 |
|
|
12'b1xxx0x000000: wr_addr = `WREG_BB;
|
3105 |
|
|
12'b00000000110x,
|
3106 |
|
|
12'b000000001110,
|
3107 |
|
|
12'b000001001xxx,
|
3108 |
|
|
12'b010x01001110,
|
3109 |
|
|
12'b1xxx0x001000: wr_addr = `WREG_CC;
|
3110 |
|
|
12'b00000001010x,
|
3111 |
|
|
12'b000000010110,
|
3112 |
|
|
12'b000001010xxx,
|
3113 |
|
|
12'b010x01010110,
|
3114 |
|
|
12'b1xxx0x010000: wr_addr = `WREG_DD;
|
3115 |
|
|
12'b00000001110x,
|
3116 |
|
|
12'b000000011110,
|
3117 |
|
|
12'b000001011xxx,
|
3118 |
|
|
12'b010x01011110,
|
3119 |
|
|
12'b1xxx0x011000: wr_addr = `WREG_EE;
|
3120 |
|
|
12'b00000010010x,
|
3121 |
|
|
12'b000000100110,
|
3122 |
|
|
12'b000001100xxx,
|
3123 |
|
|
12'b010x01100110,
|
3124 |
|
|
12'b1xxx0x100000: wr_addr = `WREG_HH;
|
3125 |
|
|
12'b00000010110x,
|
3126 |
|
|
12'b000000101110,
|
3127 |
|
|
12'b000001101xxx,
|
3128 |
|
|
12'b010x01101110,
|
3129 |
|
|
12'b1xxx0x101000: wr_addr = `WREG_LL;
|
3130 |
|
|
12'b00000011110x,
|
3131 |
|
|
12'b000000111110,
|
3132 |
|
|
12'b000001111xxx,
|
3133 |
|
|
12'b010x01111110,
|
3134 |
|
|
12'b1xxx0x111000: wr_addr = `WREG_AA;
|
3135 |
|
|
12'b00000000x011: wr_addr = `WREG_BC;
|
3136 |
|
|
12'b00000001x011: wr_addr = `WREG_DE;
|
3137 |
|
|
12'b00000010x011: wr_addr = `WREG_HL;
|
3138 |
|
|
12'b00000011x011: wr_addr = `WREG_SP;
|
3139 |
|
|
12'b010x11111001,
|
3140 |
|
|
12'b000011111001: wr_addr = `WREG_SP;
|
3141 |
|
|
12'b000011000001: wr_addr = `WREG_BC;
|
3142 |
|
|
12'b000011010001: wr_addr = `WREG_DE;
|
3143 |
|
|
12'b000011100001: wr_addr = `WREG_HL;
|
3144 |
|
|
12'b000011110001: wr_addr = `WREG_AF;
|
3145 |
|
|
default: wr_addr = `WREG_NUL;
|
3146 |
|
|
endcase
|
3147 |
|
|
end
|
3148 |
|
|
`INTB: wr_addr = (vector_int) ? `WREG_TMP : `WREG_SP;
|
3149 |
|
|
default: wr_addr = `WREG_NUL;
|
3150 |
|
|
endcase
|
3151 |
|
|
end
|
3152 |
|
|
|
3153 |
|
|
/*****************************************************************************************/
|
3154 |
|
|
/* */
|
3155 |
|
|
/* s flag control */
|
3156 |
|
|
/* */
|
3157 |
|
|
/*****************************************************************************************/
|
3158 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
3159 |
|
|
casex (state_reg) //synopsys parallel_case
|
3160 |
|
|
`WR2A: begin
|
3161 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3162 |
|
|
12'b000000110100,
|
3163 |
|
|
12'b000000110101,
|
3164 |
|
|
12'b001000000xxx,
|
3165 |
|
|
12'b001000001xxx,
|
3166 |
|
|
12'b001000010xxx,
|
3167 |
|
|
12'b001000011xxx,
|
3168 |
|
|
12'b001000100xxx,
|
3169 |
|
|
12'b001000101xxx,
|
3170 |
|
|
12'b001000111xxx,
|
3171 |
|
|
12'b010x00110100,
|
3172 |
|
|
12'b010x00110101,
|
3173 |
|
|
12'b011x00010110,
|
3174 |
|
|
12'b011x00000110,
|
3175 |
|
|
12'b011x00011110,
|
3176 |
|
|
12'b011x00001110,
|
3177 |
|
|
12'b011x00100110,
|
3178 |
|
|
12'b011x00101110,
|
3179 |
|
|
12'b011x00111110: sflg_en = 1'b1;
|
3180 |
|
|
default: sflg_en = 1'b0;
|
3181 |
|
|
endcase
|
3182 |
|
|
end
|
3183 |
|
|
`BLK1: begin
|
3184 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3185 |
|
|
12'b1xxx10100001,
|
3186 |
|
|
12'b1xxx10101001,
|
3187 |
|
|
12'b1xxx10110001,
|
3188 |
|
|
12'b1xxx10111001: sflg_en = 1'b1;
|
3189 |
|
|
default: sflg_en = 1'b0;
|
3190 |
|
|
endcase
|
3191 |
|
|
end
|
3192 |
|
|
`IF1B: begin
|
3193 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3194 |
|
|
12'b000000100111,
|
3195 |
|
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100,
|
3196 |
|
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101,
|
3197 |
|
|
12'b000010000110,
|
3198 |
|
|
12'b000010000xxx,
|
3199 |
|
|
12'b000010001110,
|
3200 |
|
|
12'b000010001xxx,
|
3201 |
|
|
12'b000010010110,
|
3202 |
|
|
12'b000010010xxx,
|
3203 |
|
|
12'b000010011110,
|
3204 |
|
|
12'b000010011xxx,
|
3205 |
|
|
12'b000010100110,
|
3206 |
|
|
12'b000010100xxx,
|
3207 |
|
|
12'b000010101110,
|
3208 |
|
|
12'b000010101xxx,
|
3209 |
|
|
12'b000010110110,
|
3210 |
|
|
12'b000010110xxx,
|
3211 |
|
|
12'b000010111110,
|
3212 |
|
|
12'b000010111xxx,
|
3213 |
|
|
12'b000011000110,
|
3214 |
|
|
12'b000011001110,
|
3215 |
|
|
12'b000011010110,
|
3216 |
|
|
12'b000011011110,
|
3217 |
|
|
12'b000011100110,
|
3218 |
|
|
12'b000011101110,
|
3219 |
|
|
12'b000011110110,
|
3220 |
|
|
12'b000011111110,
|
3221 |
|
|
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr,
|
3222 |
|
|
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr,
|
3223 |
|
|
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr,
|
3224 |
|
|
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr,
|
3225 |
|
|
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr,
|
3226 |
|
|
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr,
|
3227 |
|
|
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr,
|
3228 |
|
|
12'b010010000110,
|
3229 |
|
|
12'b010010001110,
|
3230 |
|
|
12'b010010010110,
|
3231 |
|
|
12'b010010011110,
|
3232 |
|
|
12'b010010100110,
|
3233 |
|
|
12'b010010101110,
|
3234 |
|
|
12'b010010110110,
|
3235 |
|
|
12'b010010111110,
|
3236 |
|
|
12'b010110000110,
|
3237 |
|
|
12'b010110001110,
|
3238 |
|
|
12'b010110010110,
|
3239 |
|
|
12'b010110011110,
|
3240 |
|
|
12'b010110100110,
|
3241 |
|
|
12'b010110101110,
|
3242 |
|
|
12'b010110110110,
|
3243 |
|
|
12'b010110111110,
|
3244 |
|
|
12'b1xxx01000100,
|
3245 |
|
|
12'b1xxx01010111,
|
3246 |
|
|
12'b1xxx01011111,
|
3247 |
|
|
12'b1xxx01100111,
|
3248 |
|
|
12'b1xxx01101111,
|
3249 |
|
|
12'b1xxx01xxx000,
|
3250 |
|
|
12'b1xxx01xx0010,
|
3251 |
|
|
12'b1xxx01xx1010: sflg_en = 1'b1;
|
3252 |
|
|
default: sflg_en = 1'b0;
|
3253 |
|
|
endcase
|
3254 |
|
|
end
|
3255 |
|
|
default: sflg_en = 1'b0;
|
3256 |
|
|
endcase
|
3257 |
|
|
end
|
3258 |
|
|
|
3259 |
|
|
/*****************************************************************************************/
|
3260 |
|
|
/* */
|
3261 |
|
|
/* z flag control */
|
3262 |
|
|
/* */
|
3263 |
|
|
/*****************************************************************************************/
|
3264 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
3265 |
|
|
casex (state_reg) //synopsys parallel_case
|
3266 |
|
|
`RD1A,
|
3267 |
|
|
`RD2A: begin
|
3268 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3269 |
|
|
12'b1xxx10100010,
|
3270 |
|
|
12'b1xxx10100011,
|
3271 |
|
|
12'b1xxx10101010,
|
3272 |
|
|
12'b1xxx10101011,
|
3273 |
|
|
12'b1xxx10110010,
|
3274 |
|
|
12'b1xxx10110011,
|
3275 |
|
|
12'b1xxx10111010,
|
3276 |
|
|
12'b1xxx10111011: zflg_en = 1'b1;
|
3277 |
|
|
default: zflg_en = 1'b0;
|
3278 |
|
|
endcase
|
3279 |
|
|
end
|
3280 |
|
|
`WR2A: begin
|
3281 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3282 |
|
|
12'b000000110100,
|
3283 |
|
|
12'b000000110101,
|
3284 |
|
|
12'b001000000110,
|
3285 |
|
|
12'b001000000xxx,
|
3286 |
|
|
12'b001000001110,
|
3287 |
|
|
12'b001000001xxx,
|
3288 |
|
|
12'b001000010110,
|
3289 |
|
|
12'b001000010xxx,
|
3290 |
|
|
12'b001000011110,
|
3291 |
|
|
12'b001000011xxx,
|
3292 |
|
|
12'b001000100110,
|
3293 |
|
|
12'b001000100xxx,
|
3294 |
|
|
12'b001000101110,
|
3295 |
|
|
12'b001000101xxx,
|
3296 |
|
|
12'b001000111110,
|
3297 |
|
|
12'b001000111xxx,
|
3298 |
|
|
12'b010000110100,
|
3299 |
|
|
12'b010000110101,
|
3300 |
|
|
12'b010100110100,
|
3301 |
|
|
12'b010100110101,
|
3302 |
|
|
12'b011000000110,
|
3303 |
|
|
12'b011000001110,
|
3304 |
|
|
12'b011000010110,
|
3305 |
|
|
12'b011000011110,
|
3306 |
|
|
12'b011000100110,
|
3307 |
|
|
12'b011000101110,
|
3308 |
|
|
12'b011000111110,
|
3309 |
|
|
12'b011100000110,
|
3310 |
|
|
12'b011100001110,
|
3311 |
|
|
12'b011100010110,
|
3312 |
|
|
12'b011100011110,
|
3313 |
|
|
12'b011100100110,
|
3314 |
|
|
12'b011100101110,
|
3315 |
|
|
12'b011100111110: zflg_en = 1'b1;
|
3316 |
|
|
default: zflg_en = 1'b0;
|
3317 |
|
|
endcase
|
3318 |
|
|
end
|
3319 |
|
|
`BLK1: begin
|
3320 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3321 |
|
|
12'b1xxx10100001,
|
3322 |
|
|
12'b1xxx10101001,
|
3323 |
|
|
12'b1xxx10110001,
|
3324 |
|
|
12'b1xxx10111001: zflg_en = 1'b1;
|
3325 |
|
|
default: zflg_en = 1'b0;
|
3326 |
|
|
endcase
|
3327 |
|
|
end
|
3328 |
|
|
`IF1B: begin
|
3329 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3330 |
|
|
12'b000000100111,
|
3331 |
|
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100,
|
3332 |
|
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101,
|
3333 |
|
|
12'b000010000110,
|
3334 |
|
|
12'b000010000xxx,
|
3335 |
|
|
12'b000010001110,
|
3336 |
|
|
12'b000010001xxx,
|
3337 |
|
|
12'b000010010110,
|
3338 |
|
|
12'b000010010xxx,
|
3339 |
|
|
12'b000010011110,
|
3340 |
|
|
12'b000010011xxx,
|
3341 |
|
|
12'b000010100110,
|
3342 |
|
|
12'b000010100xxx,
|
3343 |
|
|
12'b000010101110,
|
3344 |
|
|
12'b000010101xxx,
|
3345 |
|
|
12'b000010110110,
|
3346 |
|
|
12'b000010110xxx,
|
3347 |
|
|
12'b000010111110,
|
3348 |
|
|
12'b000010111xxx,
|
3349 |
|
|
12'b000011000110,
|
3350 |
|
|
12'b000011001110,
|
3351 |
|
|
12'b000011010110,
|
3352 |
|
|
12'b000011011110,
|
3353 |
|
|
12'b000011100110,
|
3354 |
|
|
12'b000011101110,
|
3355 |
|
|
12'b000011110110,
|
3356 |
|
|
12'b000011111110,
|
3357 |
|
|
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr,
|
3358 |
|
|
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr,
|
3359 |
|
|
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr,
|
3360 |
|
|
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr,
|
3361 |
|
|
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr,
|
3362 |
|
|
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr,
|
3363 |
|
|
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr,
|
3364 |
|
|
12'b001001xxx110,
|
3365 |
|
|
12'b001001xxxxxx,
|
3366 |
|
|
12'b010010000110,
|
3367 |
|
|
12'b010010001110,
|
3368 |
|
|
12'b010010010110,
|
3369 |
|
|
12'b010010011110,
|
3370 |
|
|
12'b010010100110,
|
3371 |
|
|
12'b010010101110,
|
3372 |
|
|
12'b010010110110,
|
3373 |
|
|
12'b010010111110,
|
3374 |
|
|
12'b010110000110,
|
3375 |
|
|
12'b010110001110,
|
3376 |
|
|
12'b010110010110,
|
3377 |
|
|
12'b010110011110,
|
3378 |
|
|
12'b010110100110,
|
3379 |
|
|
12'b010110101110,
|
3380 |
|
|
12'b010110110110,
|
3381 |
|
|
12'b010110111110,
|
3382 |
|
|
12'b011001xxx110,
|
3383 |
|
|
12'b011101xxx110,
|
3384 |
|
|
12'b1xxx01000100,
|
3385 |
|
|
12'b1xxx01010111,
|
3386 |
|
|
12'b1xxx01011111,
|
3387 |
|
|
12'b1xxx01100111,
|
3388 |
|
|
12'b1xxx01101111,
|
3389 |
|
|
12'b1xxx01xxx000,
|
3390 |
|
|
12'b1xxx01xx0010,
|
3391 |
|
|
12'b1xxx01xx1010,
|
3392 |
|
|
12'b1xxx10100011,
|
3393 |
|
|
12'b1xxx10101011,
|
3394 |
|
|
12'b1xxx10110011,
|
3395 |
|
|
12'b1xxx10111011: zflg_en = 1'b1;
|
3396 |
|
|
default: zflg_en = 1'b0;
|
3397 |
|
|
endcase
|
3398 |
|
|
end
|
3399 |
|
|
default: zflg_en = 1'b0;
|
3400 |
|
|
endcase
|
3401 |
|
|
end
|
3402 |
|
|
|
3403 |
|
|
/*****************************************************************************************/
|
3404 |
|
|
/* */
|
3405 |
|
|
/* h flag control */
|
3406 |
|
|
/* */
|
3407 |
|
|
/*****************************************************************************************/
|
3408 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
3409 |
|
|
casex (state_reg) //synopsys parallel_case
|
3410 |
|
|
`WR2A: begin
|
3411 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3412 |
|
|
12'b001000000xxx,
|
3413 |
|
|
12'b001000001xxx,
|
3414 |
|
|
12'b001000010xxx,
|
3415 |
|
|
12'b001000011xxx,
|
3416 |
|
|
12'b001000100xxx,
|
3417 |
|
|
12'b001000101xxx,
|
3418 |
|
|
12'b001000111xxx,
|
3419 |
|
|
12'b011x00010110,
|
3420 |
|
|
12'b011x00000110,
|
3421 |
|
|
12'b011x00011110,
|
3422 |
|
|
12'b011x00001110,
|
3423 |
|
|
12'b011x00100110,
|
3424 |
|
|
12'b011x00101110,
|
3425 |
|
|
12'b011x00111110,
|
3426 |
|
|
12'b1xxx01100111,
|
3427 |
|
|
12'b1xxx01101111: hflg_ctl = `HFLG_0;
|
3428 |
|
|
12'b000000110100,
|
3429 |
|
|
12'b000000110101,
|
3430 |
|
|
12'b010x00110100,
|
3431 |
|
|
12'b010x00110101: hflg_ctl = `HFLG_H;
|
3432 |
|
|
default: hflg_ctl = `HFLG_NUL;
|
3433 |
|
|
endcase
|
3434 |
|
|
end
|
3435 |
|
|
`BLK1: begin
|
3436 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3437 |
|
|
12'b1xxx10100001,
|
3438 |
|
|
12'b1xxx10101001,
|
3439 |
|
|
12'b1xxx10110001,
|
3440 |
|
|
12'b1xxx10111001: hflg_ctl = `HFLG_H;
|
3441 |
|
|
default: hflg_ctl = `HFLG_NUL;
|
3442 |
|
|
endcase
|
3443 |
|
|
end
|
3444 |
|
|
`IF1B: begin
|
3445 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3446 |
|
|
12'b000000000111,
|
3447 |
|
|
12'b000000001111,
|
3448 |
|
|
12'b000000010111,
|
3449 |
|
|
12'b000000011111,
|
3450 |
|
|
12'b000000110111,
|
3451 |
|
|
12'b000010101110,
|
3452 |
|
|
12'b000010101xxx,
|
3453 |
|
|
12'b000010110110,
|
3454 |
|
|
12'b000010110xxx,
|
3455 |
|
|
12'b000011101110,
|
3456 |
|
|
12'b000011110110,
|
3457 |
|
|
12'b001000000xxx,
|
3458 |
|
|
12'b001000001xxx,
|
3459 |
|
|
12'b001000010xxx,
|
3460 |
|
|
12'b001000011xxx,
|
3461 |
|
|
12'b001000100xxx,
|
3462 |
|
|
12'b001000101xxx,
|
3463 |
|
|
12'b001000111xxx,
|
3464 |
|
|
12'b010010101110,
|
3465 |
|
|
12'b010010110110,
|
3466 |
|
|
12'b010110101110,
|
3467 |
|
|
12'b010110110110,
|
3468 |
|
|
12'b1xxx01010111,
|
3469 |
|
|
12'b1xxx01011111,
|
3470 |
|
|
12'b1xxx01xxx000,
|
3471 |
|
|
12'b1xxx10100000,
|
3472 |
|
|
12'b1xxx10101000,
|
3473 |
|
|
12'b1xxx10110000,
|
3474 |
|
|
12'b1xxx10111000: hflg_ctl = `HFLG_0;
|
3475 |
|
|
12'b000000101111,
|
3476 |
|
|
12'b000010100110,
|
3477 |
|
|
12'b000010100xxx,
|
3478 |
|
|
12'b000011100110,
|
3479 |
|
|
12'b001001xxx110,
|
3480 |
|
|
12'b001001xxxxxx,
|
3481 |
|
|
12'b010010100110,
|
3482 |
|
|
12'b010110100110,
|
3483 |
|
|
12'b011001xxx110,
|
3484 |
|
|
12'b011101xxx110: hflg_ctl = `HFLG_1;
|
3485 |
|
|
12'b000000111111: hflg_ctl = `HFLG_H;
|
3486 |
|
|
12'b000000100111,
|
3487 |
|
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100,
|
3488 |
|
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101,
|
3489 |
|
|
12'b000000xx1001,
|
3490 |
|
|
12'b000010000110,
|
3491 |
|
|
12'b000010000xxx,
|
3492 |
|
|
12'b000010001110,
|
3493 |
|
|
12'b000010001xxx,
|
3494 |
|
|
12'b000010010110,
|
3495 |
|
|
12'b000010010xxx,
|
3496 |
|
|
12'b000010011110,
|
3497 |
|
|
12'b000010011xxx,
|
3498 |
|
|
12'b000010111110,
|
3499 |
|
|
12'b000010111xxx,
|
3500 |
|
|
12'b000011000110,
|
3501 |
|
|
12'b000011001110,
|
3502 |
|
|
12'b000011010110,
|
3503 |
|
|
12'b000011011110,
|
3504 |
|
|
12'b000011111110,
|
3505 |
|
|
12'b010000xx1001,
|
3506 |
|
|
12'b010010000110,
|
3507 |
|
|
12'b010010001110,
|
3508 |
|
|
12'b010010010110,
|
3509 |
|
|
12'b010010011110,
|
3510 |
|
|
12'b010010111110,
|
3511 |
|
|
12'b010100xx1001,
|
3512 |
|
|
12'b010110000110,
|
3513 |
|
|
12'b010110001110,
|
3514 |
|
|
12'b010110010110,
|
3515 |
|
|
12'b010110011110,
|
3516 |
|
|
12'b010110111110,
|
3517 |
|
|
12'b1xxx01000100,
|
3518 |
|
|
12'b1xxx01xx0010,
|
3519 |
|
|
12'b1xxx01xx1010: hflg_ctl = `HFLG_H;
|
3520 |
|
|
default: hflg_ctl = `HFLG_NUL;
|
3521 |
|
|
endcase
|
3522 |
|
|
end
|
3523 |
|
|
default: hflg_ctl = `HFLG_NUL;
|
3524 |
|
|
endcase
|
3525 |
|
|
end
|
3526 |
|
|
|
3527 |
|
|
/*****************************************************************************************/
|
3528 |
|
|
/* */
|
3529 |
|
|
/* pv flag control */
|
3530 |
|
|
/* */
|
3531 |
|
|
/*****************************************************************************************/
|
3532 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
3533 |
|
|
casex (state_reg) //synopsys parallel_case
|
3534 |
|
|
`RD1A,
|
3535 |
|
|
`RD2A: begin
|
3536 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3537 |
|
|
12'b1xxx10100000,
|
3538 |
|
|
12'b1xxx10100001,
|
3539 |
|
|
12'b1xxx10101000,
|
3540 |
|
|
12'b1xxx10101001,
|
3541 |
|
|
12'b1xxx10110000,
|
3542 |
|
|
12'b1xxx10110001,
|
3543 |
|
|
12'b1xxx10111000,
|
3544 |
|
|
12'b1xxx10111001: pflg_ctl = `PFLG_B;
|
3545 |
|
|
default: pflg_ctl = `PFLG_NUL;
|
3546 |
|
|
endcase
|
3547 |
|
|
end
|
3548 |
|
|
`WR2A: begin
|
3549 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3550 |
|
|
12'b001000000110,
|
3551 |
|
|
12'b001000000xxx,
|
3552 |
|
|
12'b001000001110,
|
3553 |
|
|
12'b001000001xxx,
|
3554 |
|
|
12'b001000010110,
|
3555 |
|
|
12'b001000010xxx,
|
3556 |
|
|
12'b001000011110,
|
3557 |
|
|
12'b001000011xxx,
|
3558 |
|
|
12'b001000100110,
|
3559 |
|
|
12'b001000100xxx,
|
3560 |
|
|
12'b001000101110,
|
3561 |
|
|
12'b001000101xxx,
|
3562 |
|
|
12'b001000111110,
|
3563 |
|
|
12'b001000111xxx,
|
3564 |
|
|
12'b011000000110,
|
3565 |
|
|
12'b011000001110,
|
3566 |
|
|
12'b011000010110,
|
3567 |
|
|
12'b011000011110,
|
3568 |
|
|
12'b011000100110,
|
3569 |
|
|
12'b011000101110,
|
3570 |
|
|
12'b011000111110,
|
3571 |
|
|
12'b011100000110,
|
3572 |
|
|
12'b011100001110,
|
3573 |
|
|
12'b011100010110,
|
3574 |
|
|
12'b011100011110,
|
3575 |
|
|
12'b011100100110,
|
3576 |
|
|
12'b011100101110,
|
3577 |
|
|
12'b011100111110: pflg_ctl = `PFLG_P;
|
3578 |
|
|
12'b000000110100,
|
3579 |
|
|
12'b000000110101,
|
3580 |
|
|
12'b010000110100,
|
3581 |
|
|
12'b010000110101,
|
3582 |
|
|
12'b010100110100,
|
3583 |
|
|
12'b010100110101: pflg_ctl = `PFLG_V;
|
3584 |
|
|
default: pflg_ctl = `PFLG_NUL;
|
3585 |
|
|
endcase
|
3586 |
|
|
end
|
3587 |
|
|
`IF1B: begin
|
3588 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3589 |
|
|
12'b1xxx01010111,
|
3590 |
|
|
12'b1xxx01011111: pflg_ctl = `PFLG_F;
|
3591 |
|
|
12'b000000100111,
|
3592 |
|
|
12'b000010100110,
|
3593 |
|
|
12'b000010100xxx,
|
3594 |
|
|
12'b000010101110,
|
3595 |
|
|
12'b000010101xxx,
|
3596 |
|
|
12'b000010110110,
|
3597 |
|
|
12'b000010110xxx,
|
3598 |
|
|
12'b000011100110,
|
3599 |
|
|
12'b000011101110,
|
3600 |
|
|
12'b000011110110,
|
3601 |
|
|
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr,
|
3602 |
|
|
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr,
|
3603 |
|
|
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr,
|
3604 |
|
|
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr,
|
3605 |
|
|
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr,
|
3606 |
|
|
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr,
|
3607 |
|
|
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr,
|
3608 |
|
|
12'b010010100110,
|
3609 |
|
|
12'b010010101110,
|
3610 |
|
|
12'b010010110110,
|
3611 |
|
|
12'b010110100110,
|
3612 |
|
|
12'b010110101110,
|
3613 |
|
|
12'b010110110110,
|
3614 |
|
|
12'b1xxx01100111,
|
3615 |
|
|
12'b1xxx01101111,
|
3616 |
|
|
12'b1xxx01xxx000: pflg_ctl = `PFLG_P;
|
3617 |
|
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100,
|
3618 |
|
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101,
|
3619 |
|
|
12'b000010000110,
|
3620 |
|
|
12'b000010000xxx,
|
3621 |
|
|
12'b000010001110,
|
3622 |
|
|
12'b000010001xxx,
|
3623 |
|
|
12'b000010010110,
|
3624 |
|
|
12'b000010010xxx,
|
3625 |
|
|
12'b000010011110,
|
3626 |
|
|
12'b000010011xxx,
|
3627 |
|
|
12'b000010111110,
|
3628 |
|
|
12'b000010111xxx,
|
3629 |
|
|
12'b000011000110,
|
3630 |
|
|
12'b000011001110,
|
3631 |
|
|
12'b000011010110,
|
3632 |
|
|
12'b000011011110,
|
3633 |
|
|
12'b000011111110,
|
3634 |
|
|
12'b010010000110,
|
3635 |
|
|
12'b010010001110,
|
3636 |
|
|
12'b010010010110,
|
3637 |
|
|
12'b010010011110,
|
3638 |
|
|
12'b010010111110,
|
3639 |
|
|
12'b010110000110,
|
3640 |
|
|
12'b010110001110,
|
3641 |
|
|
12'b010110010110,
|
3642 |
|
|
12'b010110011110,
|
3643 |
|
|
12'b010110111110,
|
3644 |
|
|
12'b1xxx01000100,
|
3645 |
|
|
12'b1xxx01xx0010,
|
3646 |
|
|
12'b1xxx01xx1010: pflg_ctl = `PFLG_V;
|
3647 |
|
|
default: pflg_ctl = `PFLG_NUL;
|
3648 |
|
|
endcase
|
3649 |
|
|
end
|
3650 |
|
|
default: pflg_ctl = `PFLG_NUL;
|
3651 |
|
|
endcase
|
3652 |
|
|
end
|
3653 |
|
|
|
3654 |
|
|
/*****************************************************************************************/
|
3655 |
|
|
/* */
|
3656 |
|
|
/* n flag control */
|
3657 |
|
|
/* */
|
3658 |
|
|
/*****************************************************************************************/
|
3659 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
3660 |
|
|
casex (state_reg) //synopsys parallel_case
|
3661 |
|
|
`WR1A,
|
3662 |
|
|
`WR2A: begin
|
3663 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3664 |
|
|
12'b1xxx10100010,
|
3665 |
|
|
12'b1xxx10100011,
|
3666 |
|
|
12'b1xxx10101010,
|
3667 |
|
|
12'b1xxx10101011,
|
3668 |
|
|
12'b1xxx10110010,
|
3669 |
|
|
12'b1xxx10110011,
|
3670 |
|
|
12'b1xxx10111010,
|
3671 |
|
|
12'b1xxx10111011: nflg_ctl = `NFLG_S;
|
3672 |
|
|
default: nflg_ctl = `NFLG_NUL;
|
3673 |
|
|
endcase
|
3674 |
|
|
end
|
3675 |
|
|
`IF1B: begin
|
3676 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3677 |
|
|
12'b000000000111,
|
3678 |
|
|
12'b000000001111,
|
3679 |
|
|
12'b000000010111,
|
3680 |
|
|
12'b000000011111,
|
3681 |
|
|
12'b000000110100,
|
3682 |
|
|
12'b000000110111,
|
3683 |
|
|
12'b000000111111,
|
3684 |
|
|
12'b0000000xx100,12'b00000010x100,12'b000000111100,//12'b000000rrr100,
|
3685 |
|
|
12'b000000xx1001,
|
3686 |
|
|
12'b000010000110,
|
3687 |
|
|
12'b000010000xxx,
|
3688 |
|
|
12'b000010001110,
|
3689 |
|
|
12'b000010001xxx,
|
3690 |
|
|
12'b000010100110,
|
3691 |
|
|
12'b000010100xxx,
|
3692 |
|
|
12'b000010101110,
|
3693 |
|
|
12'b000010101xxx,
|
3694 |
|
|
12'b000010110110,
|
3695 |
|
|
12'b000010110xxx,
|
3696 |
|
|
12'b000011000110,
|
3697 |
|
|
12'b000011001110,
|
3698 |
|
|
12'b000011100110,
|
3699 |
|
|
12'b000011101110,
|
3700 |
|
|
12'b000011110110,
|
3701 |
|
|
12'b001000000110,
|
3702 |
|
|
12'b001000000xxx,
|
3703 |
|
|
12'b001000001110,
|
3704 |
|
|
12'b001000001xxx,
|
3705 |
|
|
12'b001000010110,
|
3706 |
|
|
12'b001000010xxx,
|
3707 |
|
|
12'b001000011110,
|
3708 |
|
|
12'b001000011xxx,
|
3709 |
|
|
12'b001000100110,
|
3710 |
|
|
12'b001000100xxx,
|
3711 |
|
|
12'b001000101110,
|
3712 |
|
|
12'b001000101xxx,
|
3713 |
|
|
12'b001000111110,
|
3714 |
|
|
12'b001000111xxx,
|
3715 |
|
|
12'b001001xxx110,
|
3716 |
|
|
12'b001001xxxxxx,
|
3717 |
|
|
12'b010000110100,
|
3718 |
|
|
12'b010000xx1001,
|
3719 |
|
|
12'b010010000110,
|
3720 |
|
|
12'b010010001110,
|
3721 |
|
|
12'b010010100110,
|
3722 |
|
|
12'b010010101110,
|
3723 |
|
|
12'b010010110110,
|
3724 |
|
|
12'b010100110100,
|
3725 |
|
|
12'b010100xx1001,
|
3726 |
|
|
12'b010110000110,
|
3727 |
|
|
12'b010110001110,
|
3728 |
|
|
12'b010110100110,
|
3729 |
|
|
12'b010110101110,
|
3730 |
|
|
12'b010110110110,
|
3731 |
|
|
12'b011000000110,
|
3732 |
|
|
12'b011000001110,
|
3733 |
|
|
12'b011000010110,
|
3734 |
|
|
12'b011000011110,
|
3735 |
|
|
12'b011000100110,
|
3736 |
|
|
12'b011000101110,
|
3737 |
|
|
12'b011000111110,
|
3738 |
|
|
12'b011001xxx110,
|
3739 |
|
|
12'b011100000110,
|
3740 |
|
|
12'b011100001110,
|
3741 |
|
|
12'b011100010110,
|
3742 |
|
|
12'b011100011110,
|
3743 |
|
|
12'b011100100110,
|
3744 |
|
|
12'b011100101110,
|
3745 |
|
|
12'b011100111110,
|
3746 |
|
|
12'b011101xxx110,
|
3747 |
|
|
12'b1xxx01010111,
|
3748 |
|
|
12'b1xxx01011111,
|
3749 |
|
|
12'b1xxx01100111,
|
3750 |
|
|
12'b1xxx01101111,
|
3751 |
|
|
12'b1xxx01xxx000,
|
3752 |
|
|
12'b1xxx01xx1010,
|
3753 |
|
|
12'b1xxx10100000,
|
3754 |
|
|
12'b1xxx10101000,
|
3755 |
|
|
12'b1xxx10110000,
|
3756 |
|
|
12'b1xxx10111000: nflg_ctl = `NFLG_0;
|
3757 |
|
|
12'b000000101111,
|
3758 |
|
|
12'b000000110101,
|
3759 |
|
|
12'b0000000xx101,12'b00000010x101,12'b000000111101,//12'b000000rrr101,
|
3760 |
|
|
12'b000010010110,
|
3761 |
|
|
12'b000010010xxx,
|
3762 |
|
|
12'b000010011110,
|
3763 |
|
|
12'b000010011xxx,
|
3764 |
|
|
12'b000010111110,
|
3765 |
|
|
12'b000010111xxx,
|
3766 |
|
|
12'b000011010110,
|
3767 |
|
|
12'b000011011110,
|
3768 |
|
|
12'b000011111110,
|
3769 |
|
|
12'b010000110101,
|
3770 |
|
|
12'b010010010110,
|
3771 |
|
|
12'b010010011110,
|
3772 |
|
|
12'b010010111110,
|
3773 |
|
|
12'b010100110101,
|
3774 |
|
|
12'b010110010110,
|
3775 |
|
|
12'b010110011110,
|
3776 |
|
|
12'b010110111110,
|
3777 |
|
|
12'b1xxx01000100,
|
3778 |
|
|
12'b1xxx01xx0010,
|
3779 |
|
|
12'b1xxx10100001,
|
3780 |
|
|
12'b1xxx10101001,
|
3781 |
|
|
12'b1xxx10110001,
|
3782 |
|
|
12'b1xxx10111001: nflg_ctl = `NFLG_1;
|
3783 |
|
|
default: nflg_ctl = `NFLG_NUL;
|
3784 |
|
|
endcase
|
3785 |
|
|
end
|
3786 |
|
|
default: nflg_ctl = `NFLG_NUL;
|
3787 |
|
|
endcase
|
3788 |
|
|
end
|
3789 |
|
|
|
3790 |
|
|
/*****************************************************************************************/
|
3791 |
|
|
/* */
|
3792 |
|
|
/* c flag control */
|
3793 |
|
|
/* */
|
3794 |
|
|
/*****************************************************************************************/
|
3795 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
3796 |
|
|
casex (state_reg) //synopsys parallel_case
|
3797 |
|
|
`WR2A: begin
|
3798 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3799 |
|
|
12'b001000000xxx,
|
3800 |
|
|
12'b001000001xxx,
|
3801 |
|
|
12'b001000010xxx,
|
3802 |
|
|
12'b001000011xxx,
|
3803 |
|
|
12'b001000100xxx,
|
3804 |
|
|
12'b001000101xxx,
|
3805 |
|
|
12'b001000111xxx,
|
3806 |
|
|
12'b011x00000110,
|
3807 |
|
|
12'b011x00001110,
|
3808 |
|
|
12'b011x00010110,
|
3809 |
|
|
12'b011x00011110,
|
3810 |
|
|
12'b011x00100110,
|
3811 |
|
|
12'b011x00101110,
|
3812 |
|
|
12'b011x00111110: cflg_en = 1'b1;
|
3813 |
|
|
default: cflg_en = 1'b0;
|
3814 |
|
|
endcase
|
3815 |
|
|
end
|
3816 |
|
|
`IF1B: begin
|
3817 |
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
3818 |
|
|
12'b000010100110,
|
3819 |
|
|
12'b000010100xxx,
|
3820 |
|
|
12'b000010101110,
|
3821 |
|
|
12'b000010101xxx,
|
3822 |
|
|
12'b000010110110,
|
3823 |
|
|
12'b000010110xxx,
|
3824 |
|
|
12'b000011100110,
|
3825 |
|
|
12'b000011101110,
|
3826 |
|
|
12'b000011110110,
|
3827 |
|
|
12'b010010100110,
|
3828 |
|
|
12'b010010101110,
|
3829 |
|
|
12'b010010110110,
|
3830 |
|
|
12'b010110100110,
|
3831 |
|
|
12'b010110101110,
|
3832 |
|
|
12'b010110110110,
|
3833 |
|
|
12'b000000110111,
|
3834 |
|
|
12'b000000000111,
|
3835 |
|
|
12'b000000001111,
|
3836 |
|
|
12'b000000010111,
|
3837 |
|
|
12'b000000011111,
|
3838 |
|
|
12'b000000100111,
|
3839 |
|
|
12'b000000111111,
|
3840 |
|
|
12'b000000xx1001,
|
3841 |
|
|
12'b000010000110,
|
3842 |
|
|
12'b000010000xxx,
|
3843 |
|
|
12'b000010001110,
|
3844 |
|
|
12'b000010001xxx,
|
3845 |
|
|
12'b000010010110,
|
3846 |
|
|
12'b000010010xxx,
|
3847 |
|
|
12'b000010011110,
|
3848 |
|
|
12'b000010011xxx,
|
3849 |
|
|
12'b000010111110,
|
3850 |
|
|
12'b000010111xxx,
|
3851 |
|
|
12'b000011000110,
|
3852 |
|
|
12'b000011001110,
|
3853 |
|
|
12'b000011010110,
|
3854 |
|
|
12'b000011011110,
|
3855 |
|
|
12'b000011111110,
|
3856 |
|
|
12'b0010000000xx,12'b00100000010x,12'b001000000111,//12'b001000000rrr,
|
3857 |
|
|
12'b0010000010xx,12'b00100000110x,12'b001000001111,//12'b001000001rrr,
|
3858 |
|
|
12'b0010000100xx,12'b00100001010x,12'b001000010111,//12'b001000010rrr,
|
3859 |
|
|
12'b0010000110xx,12'b00100001110x,12'b001000011111,//12'b001000011rrr,
|
3860 |
|
|
12'b0010001000xx,12'b00100010010x,12'b001000100111,//12'b001000100rrr,
|
3861 |
|
|
12'b0010001010xx,12'b00100010110x,12'b001000101111,//12'b001000101rrr,
|
3862 |
|
|
12'b0010001110xx,12'b00100011110x,12'b001000111111,//12'b001000111rrr,
|
3863 |
|
|
12'b010000xx1001,
|
3864 |
|
|
12'b010010000110,
|
3865 |
|
|
12'b010010001110,
|
3866 |
|
|
12'b010010010110,
|
3867 |
|
|
12'b010010011110,
|
3868 |
|
|
12'b010010111110,
|
3869 |
|
|
12'b010100xx1001,
|
3870 |
|
|
12'b010110000110,
|
3871 |
|
|
12'b010110001110,
|
3872 |
|
|
12'b010110010110,
|
3873 |
|
|
12'b010110011110,
|
3874 |
|
|
12'b010110111110,
|
3875 |
|
|
12'b1xxx01000100,
|
3876 |
|
|
12'b1xxx01xx0010,
|
3877 |
|
|
12'b1xxx01xx1010: cflg_en = 1'b1;
|
3878 |
|
|
default: cflg_en = 1'b0;
|
3879 |
|
|
endcase
|
3880 |
|
|
end
|
3881 |
|
|
default: cflg_en = 1'b0;
|
3882 |
|
|
endcase
|
3883 |
|
|
end
|
3884 |
|
|
|
3885 |
|
|
/*****************************************************************************************/
|
3886 |
|
|
/* */
|
3887 |
|
|
/* temporary flag control */
|
3888 |
|
|
/* */
|
3889 |
|
|
/*****************************************************************************************/
|
3890 |
|
|
always @ (inst_reg or page_reg or state_reg) begin
|
3891 |
|
|
casex (state_reg) //synopsys parallel_case
|
3892 |
|
|
`OF1B: tflg_ctl = `TFLG_Z;
|
3893 |
|
|
`RD1A,
|
3894 |
|
|
`RD2A: begin
|
3895 |
|
|
casex ({page_reg, inst_reg})
|
3896 |
|
|
12'b1xxx10100011,
|
3897 |
|
|
12'b1xxx10101011,
|
3898 |
|
|
12'b1xxx10110011,
|
3899 |
|
|
12'b1xxx10111011: tflg_ctl = `TFLG_1;
|
3900 |
|
|
default: tflg_ctl = `TFLG_Z;
|
3901 |
|
|
endcase
|
3902 |
|
|
end
|
3903 |
|
|
`BLK1: tflg_ctl = `TFLG_B;
|
3904 |
|
|
default: tflg_ctl = `TFLG_NUL;
|
3905 |
|
|
endcase
|
3906 |
|
|
end
|
3907 |
|
|
|
3908 |
|
|
endmodule
|
3909 |
|
|
|
3910 |
|
|
|
3911 |
|
|
|
3912 |
|
|
|
3913 |
|
|
|