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[/] [y80e/] [trunk/] [rtl/] [defines.v] - Blame information for rev 2

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1 2 bsa 
/*******************************************************************************************/
2 
/**                                                                                       **/
3 
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED          **/
4 
/**                                                                                       **/
5 
/** define file to make the code more readable                       Rev  0.0  07/29/2011 **/
6 
/**                                                                                       **/
7 
/*******************************************************************************************/
8 
 
9 
  /*****************************************************************************************/
10 
  /*                                                                                       */
11 
  /* page register control - DO NOT MODIFY                                                 */
12 
  /*                                                                                       */
13 
  /*****************************************************************************************/
14 
  `define MAIN_PG     4'b0000          //no instruction prefix byte(s)
15 
  `define INTR_PG     4'b0001          //interrupt acknowledge
16 
  `define CB_PAGE     4'b0010          //CB instruction prefix
17 
  `define DMA_PG      4'b0011          //dma acknowledge
18 
  `define DD_PAGE     4'b0100          //DD instruction prefix
19 
  `define FD_PAGE     4'b0101          //FD instruction prefix
20 
  `define DDCB_PG     4'b0110          //DD-CB instruction prefix
21 
  `define FDCB_PG     4'b0111          //FD-CB instruction prefix
22 
  `define ED_PAGE     4'b1000          //ED instruction prefix
23 
  `define DEC_MAIN    4'b0x0x          //main page or DD page or FD page
24 
  `define DEC_ED      4'b1xxx          //ED page
25 
 
26 
  /*****************************************************************************************/
27 
  /*                                                                                       */
28 
  /* program counter register control: pc_sel                                              */
29 
  /*                                                                                       */
30 
  /*****************************************************************************************/
31 
  `define PCCTL_IDX   2
32 
  `define PC_NUL      3'b000           //No operation on PC
33 
  `define PC_LD       3'b001           //PC loaded unconditionally
34 
  `define PC_NILD     3'b011           //PC loaded if no interrupt, sample interrupt
35 
  `define PC_INT      3'b100           //Sample interrupt/dma only
36 
  `define PC_DMA      3'b110           //Sample dma only
37 
  `define PC_NILD2    3'b111           //PC loaded if no latched interrupt
38 
 
39 
  /*****************************************************************************************/
40 
  /*                                                                                       */
41 
  /* address bus select: add_sel                                                           */
42 
  /*                                                                                       */
43 
  /*****************************************************************************************/
44 
  `define ADCTL_IDX   3
45 
  `define ADD_RSTVAL  4'b0000          //Pipeline register reset value
46 
  `define ADD_PC      4'b0001          //Select address register from PC
47 
  `define ADD_HL      4'b0010          //Select address register from HL
48 
  `define ADD_SP      4'b0100          //Select address register from SP
49 
  `define ADD_ALU     4'b1000          //Select address register from ALU
50 
 
51 
  `define AD_PC       0                //Address from PC
52 
  `define AD_HL       1                //Address from HL
53 
  `define AD_SP       2                //Address from SP
54 
  `define AD_ALU      3                //Address from ALU
55 
 
56 
  /*****************************************************************************************/
57 
  /*                                                                                       */
58 
  /* transaction type select: tran_sel                                                     */
59 
  /*                                                                                       */
60 
  /*****************************************************************************************/
61 
  `define TTYPE_IDX   5
62 
  `define TRAN_RSTVAL 6'b000000        //Transaction type reset value
63 
  `define TRAN_IAK    6'b000001        //Intack transaction
64 
  `define TRAN_IDL    6'b000010        //Idle transaction
65 
  `define TRAN_IF     6'b000100        //Instruction fetch transaction
66 
  `define TRAN_IO     6'b001000        //I/O transaction
67 
  `define TRAN_MEM    6'b010000        //Memory (data) transaction
68 
  `define TRAN_STK    6'b100000        //Memory (stack) transaction
69 
 
70 
  `define TT_IAK      0                //Interrupt acknowledge transaction
71 
  `define TT_IDL      1                //Idle transaction
72 
  `define TT_IF       2                //Instruction fetch transaction
73 
  `define TT_IO       3                //I/O transaction
74 
  `define TT_MEM      4                //Memory (data) transaction
75 
  `define TT_STK      5                //Memory (stack) transaction
76 
 
77 
  /*****************************************************************************************/
78 
  /*                                                                                       */
79 
  /* data output control: do_ctl - DO NOT MODIFY                                           */
80 
  /*                                                                                       */
81 
  /*****************************************************************************************/
82 
  `define DO_IDX      2
83 
  `define DO_NUL      3'b000           //No load
84 
  `define DO_IO       3'b010           //Load i/o data from lsb
85 
  `define DO_LSB      3'b100           //Load mem data from lsb
86 
  `define DO_MSB      3'b101           //Load mem data from msb
87 
 
88 
  /*****************************************************************************************/
89 
  /*                                                                                       */
90 
  /* data input control: di_ctl - DO NOT MODIFY                                            */
91 
  /*                                                                                       */
92 
  /*****************************************************************************************/
93 
  `define DI_IDX      1
94 
  `define DI_NUL      2'b00            //No load
95 
  `define DI_DI0      2'b01            //Load din0
96 
  `define DI_DI1      2'b10            //Load din1
97 
  `define DI_DI10     2'b11            //Load both din0 and din1
98 
 
99 
  /*****************************************************************************************/
100 
  /*                                                                                       */
101 
  /* interrupt enable control: ief_ctl - DO NOT MODIFY                                     */
102 
  /*                                                                                       */
103 
  /*****************************************************************************************/
104 
  `define IEF_IDX     2
105 
  `define IEF_NUL     3'b000           //No load
106 
  `define IEF_0       3'b010           //Load zero
107 
  `define IEF_1       3'b011           //Load one
108 
  `define IEF_NMI     3'b100           //ief2 <= ief1, ief1 <= 0
109 
  `define IEF_RTN     3'b101           //ief1 <= ief2
110 
 
111 
  /*****************************************************************************************/
112 
  /*                                                                                       */
113 
  /* int mode control: imd_ctl - DO NOT MODIFY                                             */
114 
  /*                                                                                       */
115 
  /*****************************************************************************************/
116 
  `define IMD_IDX     1
117 
  `define IMD_NUL     2'b00            //No load
118 
  `define IMD_0       2'b01            //Set interrupt mode 0
119 
  `define IMD_1       2'b10            //Set interrupt mode 1
120 
  `define IMD_2       2'b11            //Set interrupt mode 2
121 
 
122 
  /*****************************************************************************************/
123 
  /*                                                                                       */
124 
  /* half-carry flag control: hflg_ctl - DO NOT MODIFY                                     */
125 
  /*                                                                                       */
126 
  /*****************************************************************************************/
127 
  `define HFLG_IDX    1
128 
  `define HFLG_NUL    2'b00            //No load
129 
  `define HFLG_H      2'b01            //Load half-carry result
130 
  `define HFLG_0      2'b10            //Load zero
131 
  `define HFLG_1      2'b11            //Load one
132 
 
133 
  /*****************************************************************************************/
134 
  /*                                                                                       */
135 
  /* parity/overflow flag control: pflg_ctl                                                */
136 
  /*                                                                                       */
137 
  /*****************************************************************************************/
138 
  `define PFLG_IDX    2
139 
  `define PFLG_NUL    3'b000           //No load
140 
  `define PFLG_V      3'b001           //Load overflow result
141 
  `define PFLG_0      3'b010           //Load zero
142 
  `define PFLG_1      3'b011           //Load one
143 
  `define PFLG_P      3'b100           //Load parity result
144 
  `define PFLG_B      3'b101           //Load block count zero result
145 
  `define PFLG_F      3'b111           //Load ief
146 
 
147 
  /*****************************************************************************************/
148 
  /*                                                                                       */
149 
  /* negate flag control: nflg_ctl - DO NOT MODIFY                                         */
150 
  /*                                                                                       */
151 
  /*****************************************************************************************/
152 
  `define NFLG_IDX    1
153 
  `define NFLG_NUL    2'b00            //No load
154 
  `define NFLG_S      2'b01            //Load sign result
155 
  `define NFLG_0      2'b10            //Load zero
156 
  `define NFLG_1      2'b11            //Load one
157 
 
158 
  /*****************************************************************************************/
159 
  /*                                                                                       */
160 
  /* temporary flag control: tflg_ctl                                                      */
161 
  /*                                                                                       */
162 
  /*****************************************************************************************/
163 
  `define TFLG_IDX    1
164 
  `define TFLG_NUL    2'b00            //No load
165 
  `define TFLG_Z      2'b01            //Load zero result
166 
  `define TFLG_1      2'b10            //Load one result (blk out)
167 
  `define TFLG_B      2'b11            //Load blk cp result
168 
 
169 
  /*****************************************************************************************/
170 
  /*                                                                                       */
171 
  /* write register control: wr_sel - unencoded                                            */
172 
  /*                                                                                       */
173 
  /*****************************************************************************************/
174 
  `define WREG_IDX 14
175 
  `define WREG_BB    15'b110000000000000         //Select B to write
176 
  `define WREG_BC    15'b111000000000000         //Select BC to write
177 
  `define WREG_CC    15'b101000000000000         //Select C to write
178 
  `define WREG_DD    15'b100100000000000         //Select D to write
179 
  `define WREG_DE    15'b100110000000000         //Select DE to write
180 
  `define WREG_EE    15'b100010000000000         //Select E to write
181 
  `define WREG_HH    15'b100001000000000         //Select H to write
182 
  `define WREG_HL    15'b100001100000000         //Select HL to write
183 
  `define WREG_LL    15'b100000100000000         //Select L to write
184 
  `define WREG_DEHL  15'b100111100000000         //Select DEHL to write (ex case)
185 
  `define WREG_AA    15'b100000010000000         //Select A to write
186 
  `define WREG_AF    15'b100000011000000         //Select A and F to write
187 
  `define WREG_FF    15'b100000001000000         //Select F to write
188 
  `define WREG_SP    15'b100000000100000         //Select SP to write
189 
  `define WREG_TMP   15'b100000000010000         //Select TMP register to write
190 
  `define WREG_IX    15'b100000000001000         //Select IX to write
191 
  `define WREG_IY    15'b100000000000100         //Select IY to write
192 
  `define WREG_II    15'b100000000000010         //Select I register to write
193 
  `define WREG_RR    15'b100000000000001         //Select R register to write
194 
  `define WREG_NUL   15'b000000000000000         //No register write
195 
 
196 
  `define WR_REG     14                //register write
197 
  `define WR_BB      13                //BB register index
198 
  `define WR_CC      12                //CC register index
199 
  `define WR_DD      11                //DD register index
200 
  `define WR_EE      10                //EE register index
201 
  `define WR_HH       9                //HH register index
202 
  `define WR_LL       8                //LL register index
203 
  `define WR_AA       7                //AA register index
204 
  `define WR_FF       6                //FF register index
205 
  `define WR_SP       5                //SP register index
206 
  `define WR_TMP      4                //TMP register index
207 
  `define WR_IX       3                //IX register index
208 
  `define WR_IY       2                //IY register index
209 
  `define WR_II       1                //II register index
210 
  `define WR_RR       0                //RR register index
211 
 
212 
  /*****************************************************************************************/
213 
  /*                                                                                       */
214 
  /* ALU input A control: alua_sel                                                         */
215 
  /*                                                                                       */
216 
  /*****************************************************************************************/
217 
  `define ALUA_IDX 13
218 
  `define ALUA_RSTVAL 14'h0000         //Reset value for pipeline controls
219 
  `define ALUA_ZER    14'h0000         //Select 16'h0000 (default)
220 
  `define ALUA_ONE    14'h0001         //Select 16'h0001
221 
  `define ALUA_M1     14'h0002         //Select 16'hFFFF
222 
  `define ALUA_M2     14'h0004         //Select 16'hFFFE
223 
  `define ALUA_HL     14'h0008         //Select HL register
224 
  `define ALUA_IX     14'h0010         //Select IX register
225 
  `define ALUA_IY     14'h0020         //Select IY register
226 
  `define ALUA_PC     14'h0040         //Select PC register
227 
  `define ALUA_AA     14'h0080         //Select A register
228 
  `define ALUA_BIT    14'h0100         //Select bit select constant
229 
  `define ALUA_DAA    14'h0200         //Select decimal adjust constant
230 
  `define ALUA_II     14'h0400         //Select I register
231 
  `define ALUA_RR     14'h0800         //Select R register
232 
  `define ALUA_INT    14'h1000         //Select interrupt address
233 
  `define ALUA_RST    14'h2000         //Select restart address
234 
 
235 
  `define AA_ONE       0               //alua one
236 
  `define AA_M1        1               //alua -1
237 
  `define AA_M2        2               //alua -2
238 
  `define AA_HL        3               //alua hl
239 
  `define AA_IX        4               //alua ix
240 
  `define AA_IY        5               //alua iy
241 
  `define AA_PC        6               //alua pc
242 
  `define AA_AA        7               //alua aa
243 
  `define AA_BIT       8               //alua bit
244 
  `define AA_DAA       9               //alua daa
245 
  `define AA_II       10               //alua ii
246 
  `define AA_RR       11               //alua rr
247 
  `define AA_INT      12               //alua interrupt
248 
  `define AA_RST      13               //alua restart
249 
 
250 
  /*****************************************************************************************/
251 
  /*                                                                                       */
252 
  /* ALU input B control: alub_sel                                                         */
253 
  /*                                                                                       */
254 
  /*****************************************************************************************/
255 
  `define ALUB_IDX 12
256 
  `define ALUB_RSTVAL 13'h1000         //Reset value for pipeline controls
257 
  `define ALUB_AF     13'h1002         //Select A and F registers
258 
  `define ALUB_AA     13'h1003         //Select A register
259 
  `define ALUB_BC     13'h0004         //Select BC register
260 
  `define ALUB_BB     13'h0005         //Select B register
261 
  `define ALUB_CC     13'h0004         //Select C register
262 
  `define ALUB_DE     13'h0008         //Select DE register
263 
  `define ALUB_DD     13'h0009         //Select D register
264 
  `define ALUB_EE     13'h0008         //Select E register
265 
  `define ALUB_HL     13'h0010         //Select HL register
266 
  `define ALUB_HH     13'h0011         //Select H register
267 
  `define ALUB_LL     13'h0010         //Select L register
268 
  `define ALUB_IX     13'h0020         //Select IX register
269 
  `define ALUB_IXH    13'h0021         //Select IX register high byte
270 
  `define ALUB_IXL    13'h0020         //Select IX register low byte
271 
  `define ALUB_IY     13'h0040         //Select IY register
272 
  `define ALUB_IYH    13'h0041         //Select IY register high byte
273 
  `define ALUB_IYL    13'h0040         //Select IY register low byte
274 
  `define ALUB_SP     13'h0080         //Select SP register
275 
  `define ALUB_SPH    13'h0081         //Select SP register high byte
276 
  `define ALUB_DIN    13'h0100         //Select data input register
277 
  `define ALUB_DINH   13'h0101         //Select data input register high byte
278 
  `define ALUB_IO     13'h0200         //Select i/o address
279 
  `define ALUB_TMP    13'h0400         //Select TMP register
280 
  `define ALUB_PC     13'h1800         //Select PC register
281 
  `define ALUB_PCH    13'h1801         //Select PC register high byte
282 
 
283 
  `define AB_SHR      0                //alub shift right
284 
  `define AB_AF       1                //alub af
285 
  `define AB_BC       2                //alub bc
286 
  `define AB_DE       3                //alub de
287 
  `define AB_HL       4                //alub hl
288 
  `define AB_IX       5                //alub ix
289 
  `define AB_IY       6                //alub iy
290 
  `define AB_SP       7                //alub sp
291 
  `define AB_DIN      8                //alub din
292 
  `define AB_IO       9                //alub io
293 
  `define AB_TMP      10               //alub tmp
294 
  `define AB_PC       11               //alub pc
295 
  `define AB_ADR      12               //alub address pc
296 
 
297 
  /*****************************************************************************************/
298 
  /*                                                                                       */
299 
  /* ALU operation control: aluop_sel - 2 MSBs fixed for unit sel                          */
300 
  /*                                                                                       */
301 
  /*****************************************************************************************/
302 
  `define ALUOP_IDX 7
303 
  `define ALUOP_RSTVAL 8'b00000000     //Reset Value for pipeline controls
304 
  `define ALUOP_ADD    8'b01000000     //ALU math: add
305 
  `define ALUOP_BADD   8'b01000001     //ALU math: byte add
306 
  `define ALUOP_BDEC   8'b01000011     //ALU math: byte add (decrement)
307 
  `define ALUOP_ADS    8'b01000100     //ALU math: add signed byte
308 
  `define ALUOP_DAA    8'b01000101     //ALU math: byte add (daa)
309 
  `define ALUOP_ADC    8'b01001000     //ALU math: add with carry
310 
  `define ALUOP_BADC   8'b01001001     //ALU math: byte add with carry
311 
  `define ALUOP_SUB    8'b01010000     //ALU math: subtract
312 
  `define ALUOP_BSUB   8'b01010001     //ALU math: subtract
313 
  `define ALUOP_SBC    8'b01100000     //ALU math: subtract with carry
314 
  `define ALUOP_BSBC   8'b01100001     //ALU math: byte subtract with carry
315 
 
316 
  `define ALUOP_PASS   8'b00000000     //ALU logic: pass b bus
317 
  `define ALUOP_BAND   8'b00000011     //ALU logic: byte and
318 
  `define ALUOP_BOR    8'b00000101     //ALU logic: byte or
319 
  `define ALUOP_BXOR   8'b00001001     //ALU logic: byte or
320 
  `define ALUOP_CCF    8'b00010000     //ALU logic: complement carry
321 
  `define ALUOP_SCF    8'b00010010     //ALU logic: set carry
322 
  `define ALUOP_RLD1   8'b00011000     //ALU logic: rld first step
323 
  `define ALUOP_RLD2   8'b00011010     //ALU logic: rld second step
324 
  `define ALUOP_RRD1   8'b00011100     //ALU logic: rrd first step
325 
  `define ALUOP_RRD2   8'b00011110     //ALU logic: rrd second step
326 
  `define ALUOP_APAS   8'b00100000     //ALU logic: pass a bus
327 
 
328 
  `define ALUOP_RL     8'b10000000     //ALU shft: rotate left
329 
  `define ALUOP_RLA    8'b10000001     //ALU shft: rotate left acc
330 
  `define ALUOP_RLC    8'b10000010     //ALU shft: rotate left circular
331 
  `define ALUOP_RLCA   8'b10000011     //ALU shft: rotate left circular acc
332 
  `define ALUOP_RR     8'b10000100     //ALU shft: rotate right
333 
  `define ALUOP_RRA    8'b10000101     //ALU shft: rotate right acc
334 
  `define ALUOP_RRC    8'b10001000     //ALU shft: rotate right circular
335 
  `define ALUOP_RRCA   8'b10001001     //ALU shft: rotate right circular acc
336 
  `define ALUOP_SLA    8'b10010000     //ALU shft: shift left arithmetic
337 
  `define ALUOP_SRL    8'b10100000     //ALU shft: shift right logical
338 
  `define ALUOP_SRA    8'b10101000     //ALU shft: shift right arithmetic
339 
 
340 
  /*****************************************************************************************/
341 
  /*                                                                                       */
342 
  /* ALU operation control: 6 encoded                                                      */
343 
  /*                                                                                       */
344 
  /*****************************************************************************************/
345 
  `define AOP_IDX 5
346 
  `define AOP_ADD      6'b000000       //ALU math: add
347 
  `define AOP_BADD     6'b000001       //ALU math: byte add
348 
  `define AOP_BDEC     6'b000011       //ALU math: byte add (decrement)
349 
  `define AOP_ADS      6'b000100       //ALU math: add signed byte
350 
  `define AOP_DAA      6'b000101       //ALU math: byte add (daa)
351 
  `define AOP_ADC      6'b001000       //ALU math: add with carry
352 
  `define AOP_BADC     6'b001001       //ALU math: byte add with carry
353 
  `define AOP_SUB      6'b010000       //ALU math: subtract
354 
  `define AOP_BSUB     6'b010001       //ALU math: subtract
355 
  `define AOP_SBC      6'b100000       //ALU math: subtract with carry
356 
  `define AOP_BSBC     6'b100001       //ALU math: byte subtract with carry
357 
 
358 
  `define AOP_PASS     6'b000000       //ALU logic: pass b bus
359 
  `define AOP_BAND     6'b000011       //ALU logic: byte and
360 
  `define AOP_BOR      6'b000101       //ALU logic: byte or
361 
  `define AOP_BXOR     6'b001001       //ALU logic: byte or
362 
  `define AOP_CCF      6'b010000       //ALU logic: complement carry
363 
  `define AOP_SCF      6'b010010       //ALU logic: set carry
364 
  `define AOP_RLD1     6'b011000       //ALU logic: rld first step
365 
  `define AOP_RLD2     6'b011010       //ALU logic: rld second step
366 
  `define AOP_RRD1     6'b011100       //ALU logic: rrd first step
367 
  `define AOP_RRD2     6'b011110       //ALU logic: rrd second step
368 
  `define AOP_APAS     6'b100000       //ALU logic: pass a bus
369 
 
370 
  `define AOP_RL       6'b000000       //ALU shft: rotate left
371 
  `define AOP_RLA      6'b000001       //ALU shft: rotate left acc
372 
  `define AOP_RLC      6'b000010       //ALU shft: rotate left circular
373 
  `define AOP_RLCA     6'b000011       //ALU shft: rotate left circular acc
374 
  `define AOP_RR       6'b000100       //ALU shft: rotate right
375 
  `define AOP_RRA      6'b000101       //ALU shft: rotate right acc
376 
  `define AOP_RRC      6'b001000       //ALU shft: rotate right circular
377 
  `define AOP_RRCA     6'b001001       //ALU shft: rotate right circular acc
378 
  `define AOP_SLA      6'b010000       //ALU shft: shift left arithmetic
379 
  `define AOP_SRL      6'b100000       //ALU shft: shift right logical
380 
  `define AOP_SRA      6'b101000       //ALU shft: shift right arithmetic
381 
 
382 
  /*****************************************************************************************/
383 
  /*                                                                                       */
384 
  /* machine state - pseudo-one-hot                                                        */
385 
  /*                                                                                       */
386 
  /*****************************************************************************************/
387 
  `define STATE_IDX 31
388 
  `define sRST   32'b00000000000000000000000000000000   //reset
389 
  `define sDEC1  32'b00000000000000000000000000000011   //decode 1st opcode
390 
  `define sIF2B  32'b00000000000000000000000000000101   //fetch 2nd opcode (2)
391 
  `define sDEC2  32'b00000000000000000000000000001001   //decode 2nd opcode
392 
  `define sOF1B  32'b00000000000000000000000000010001   //fetch 1st operand (2)
393 
  `define sOF2A  32'b00000000000000000000000000100001   //fetch 2nd operand (1)
394 
  `define sOF2B  32'b00000000000000000000000001000001   //fetch 2nd operand (2)
395 
  `define sIF3A  32'b00000000000000000000000010000001   //fetch 3rd opcode (1)
396 
  `define sIF3B  32'b00000000000000000000000100000001   //fetch 3rd opcode (2)
397 
  `define sADR1  32'b00000000000000000000001000000001   //address calculate (1)
398 
  `define sADR2  32'b00000000000000000000010000000001   //address calculate (2)
399 
  `define sRD1A  32'b00000000000000000000100000000001   //read 1st operand (1)
400 
  `define sRD1B  32'b00000000000000000001000000000001   //read 1st operand (2)
401 
  `define sRD2A  32'b00000000000000000010000000000001   //read 2nd operand (1)
402 
  `define sRD2B  32'b00000000000000000100000000000001   //read 2nd operand (2)
403 
  `define sWR1A  32'b00000000000000001000000000000001   //write 1st operand (1)
404 
  `define sWR1B  32'b00000000000000010000000000000001   //write 1st operand (2)
405 
  `define sWR2A  32'b00000000000000100000000000000001   //write 2nd operand (1)
406 
  `define sWR2B  32'b00000000000001000000000000000001   //write 2nd operand (2)
407 
  `define sBLK1  32'b00000000000010000000000000000001   //block instruction (1)
408 
  `define sBLK2  32'b00000000000100000000000000000001   //block instruction (2)
409 
  `define sPCA   32'b00000000001000000000000000000001   //PC adjust
410 
  `define sPCO   32'b00000000010000000000000000000001   //PC output
411 
  `define sIF1A  32'b00000000100000000000000000000001   //fetch 1st opcode (1)
412 
  `define sIF1B  32'b00000001000000000000000000000001   //fetch 1st opcode (2)
413 
  `define sINTA  32'b00000010000000000000000000000001   //interrupt acknowledge (1)
414 
  `define sINTB  32'b00000100000000000000000000000001   //interrupt acknowledge (2)
415 
  `define sHLTA  32'b00001000000000000000000000000001   //halt & sleep (1)
416 
  `define sHLTB  32'b00010000000000000000000000000001   //halt & sleep (2)
417 
  `define sDMA1  32'b00100000000000000000000000000001   //dma transfer (1)
418 
  `define sDMA2  32'b01000000000000000000000000000001   //dma transfer (2)
419 
  `define sRSTE  32'b10000000000000000000000000000001   //reset exit
420 
 
421 
  `define  RST   32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0   //reset
422 
  `define  DEC1  32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11   //decode 1st opcode
423 
  `define  IF2B  32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1x1   //fetch 2nd opcode (2)
424 
  `define  DEC2  32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx1xx1   //decode 2nd opcode
425 
  `define  OF1B  32'bxxxxxxxxxxxxxxxxxxxxxxxxxxx1xxx1   //fetch 1st operand (2)
426 
  `define  OF2A  32'bxxxxxxxxxxxxxxxxxxxxxxxxxx1xxxx1   //fetch 2nd operand (1)
427 
  `define  OF2B  32'bxxxxxxxxxxxxxxxxxxxxxxxxx1xxxxx1   //fetch 2nd operand (2)
428 
  `define  IF3A  32'bxxxxxxxxxxxxxxxxxxxxxxxx1xxxxxx1   //fetch 3rd opcode (1)
429 
  `define  IF3B  32'bxxxxxxxxxxxxxxxxxxxxxxx1xxxxxxx1   //fetch 3rd opcode (2)
430 
  `define  ADR1  32'bxxxxxxxxxxxxxxxxxxxxxx1xxxxxxxx1   //address calculate (1)
431 
  `define  ADR2  32'bxxxxxxxxxxxxxxxxxxxxx1xxxxxxxxx1   //address calculate (2)
432 
  `define  RD1A  32'bxxxxxxxxxxxxxxxxxxxx1xxxxxxxxxx1   //read 1st operand (1)
433 
  `define  RD1B  32'bxxxxxxxxxxxxxxxxxxx1xxxxxxxxxxx1   //read 1st operand (2)
434 
  `define  RD2A  32'bxxxxxxxxxxxxxxxxxx1xxxxxxxxxxxx1   //read 2nd operand (1)
435 
  `define  RD2B  32'bxxxxxxxxxxxxxxxxx1xxxxxxxxxxxxx1   //read 2nd operand (2)
436 
  `define  WR1A  32'bxxxxxxxxxxxxxxxx1xxxxxxxxxxxxxx1   //write 1st operand (1)
437 
  `define  WR1B  32'bxxxxxxxxxxxxxxx1xxxxxxxxxxxxxxx1   //write 1st operand (2)
438 
  `define  WR2A  32'bxxxxxxxxxxxxxx1xxxxxxxxxxxxxxxx1   //write 2nd operand (1)
439 
  `define  WR2B  32'bxxxxxxxxxxxxx1xxxxxxxxxxxxxxxxx1   //write 2nd operand (2)
440 
  `define  BLK1  32'bxxxxxxxxxxxx1xxxxxxxxxxxxxxxxxx1   //block instruction (1)
441 
  `define  BLK2  32'bxxxxxxxxxxx1xxxxxxxxxxxxxxxxxxx1   //block instruction (2)
442 
  `define  PCA   32'bxxxxxxxxxx1xxxxxxxxxxxxxxxxxxxx1   //PC adjust
443 
  `define  PCO   32'bxxxxxxxxx1xxxxxxxxxxxxxxxxxxxxx1   //PC output
444 
  `define  IF1A  32'bxxxxxxxx1xxxxxxxxxxxxxxxxxxxxxx1   //fetch 1st opcode (1)
445 
  `define  IF1B  32'bxxxxxxx1xxxxxxxxxxxxxxxxxxxxxxx1   //fetch 1st opcode (2)
446 
  `define  INTA  32'bxxxxxx1xxxxxxxxxxxxxxxxxxxxxxxx1   //interrupt acknowledge (1)
447 
  `define  INTB  32'bxxxxx1xxxxxxxxxxxxxxxxxxxxxxxxx1   //interrupt acknowledge (2)
448 
  `define  HLTA  32'bxxxx1xxxxxxxxxxxxxxxxxxxxxxxxxx1   //halt & sleep (1)
449 
  `define  HLTB  32'bxxx1xxxxxxxxxxxxxxxxxxxxxxxxxxx1   //halt & sleep (2)
450 
  `define  DMA1  32'bxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxx1   //dma transfer (1)
451 
  `define  DMA2  32'bx1xxxxxxxxxxxxxxxxxxxxxxxxxxxxx1   //dma transfer (2)
452 
  `define  RSTE  32'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1   //reset exit
453 
 
454 
 
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