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[/] [y80e/] [trunk/] [rtl/] [top_levl.v] - Blame information for rev 5

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/*******************************************************************************************/
/**                                                                                       **/
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED          **/
/**                                                                                       **/
/** Y80 processor test bench                                          Rev 0.0  08/20/2011 **/
/**                                                                                       **/
/*******************************************************************************************/
`timescale 1ns / 10ps                                      /* set time scale               */
`include "version.v"                                       /* select version               */
`include "hierarchy.v"                                     /* include sources              */
 
module top_levl;
 
  wire        DMA_ACK;                                     /* dma acknowledge              */
  wire        HALT_TRAN;                                   /* halt transaction             */
  wire        IACK_TRAN;                                   /* int ack transaction          */
  wire        IO_READ;                                     /* i/o read/write status        */
  wire        IO_STROBE;                                   /* i/o strobe                   */
  wire        IO_TRAN;                                     /* i/o transaction              */
  wire        IVEC_RD;                                     /* int vector read strobe       */
  wire        MEM_RD;                                      /* mem read strobe              */
  wire        MEM_TRAN;                                    /* mem transaction              */
  wire        MEM_WR;                                      /* mem write strobe             */
  wire        RETI_TRAN;                                   /* reti transaction             */
  wire        T1;                                          /* first clock of transaction   */
  wire  [7:0] IO_DATA_OUT;                                 /* i/o data output bus          */
  wire  [7:0] MEM_DATA_OUT;                                /* mem data output bus          */
  wire [15:0] IO_ADDR;                                     /* i/o address bus              */
  wire [15:0] MEM_ADDR;                                    /* mem address bus              */
 
  reg         CLEARB;                                      /* master (test) reset          */
  reg         CLKC;                                        /* clock                        */
  reg         DMA_REQ;                                     /* dma request                  */
  reg         INT_REQ;                                     /* interrupt request            */
  reg         NMI_REQ;                                     /* non-maskable interrupt req   */
  reg         RESETB;                                      /* internal (user) reset        */
  reg         WAIT_REQ;                                    /* wait request                 */
  reg   [7:0] IO_DATA_IN;                                  /* i/o data input bus           */
  reg   [7:0] IVEC_DATA_IN;                                /* vector input bus             */
  reg   [7:0] MEM_DATA_IN;                                 /* mem data input bus           */
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* testbench internal variables                                                          */
  /*                                                                                       */
  /*****************************************************************************************/
  reg         CLR_INT;                                     /* deassert interrupt           */
  reg         CLR_NMI;                                     /* deassert nmi                 */
  reg         DISABLE_BREQ;                                /* bus req generator control    */
  reg         DISABLE_INT;                                 /* interrupt generator control  */
  reg         DISABLE_WAIT;                                /* wait generator control       */
  reg         INT_TYPE;                                    /* int type during bus req      */
  reg         PAT_DONE;                                    /* pattern done flag            */
  reg         TRIG_INT;                                    /* assert interrupt             */
  reg         TRIG_NMI;                                    /* assert nmi                   */
  reg   [2:0] PAT_CNT;                                     /* counter to track patterns    */
  reg  [15:0] CMP_ERR_L;                                   /* error counter                */
 
  reg         wait_dly;                                    /* wait request state machine   */
  reg   [5:0] breq_mach;                                   /* bus request state machine    */
 
  reg         TREF0, TREF1, TREF2, TREF3, TREF4;           /* timing generator             */
  reg         TREF5, TREF6, TREF7, TREF8, TREF9;
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* read memory and write data compare memory                                             */
  /*                                                                                       */
  /*****************************************************************************************/
  reg   [7:0] rdmem [0:65535];
  reg   [7:0] wrmem [0:65535];
 
  wire  [7:0] wr_data = (MEM_TRAN) ? wrmem[MEM_ADDR] :
                        (IO_TRAN)  ? wrmem[IO_ADDR]  : 8'hxx;
 
  wire  [7:0] rd_data   = rdmem[MEM_ADDR];
  wire  [7:0] iord_data = rdmem[IO_ADDR];
 
  always @ (posedge TREF6) begin
    IO_DATA_IN   = (IO_TRAN && IO_READ && IO_STROBE && !WAIT_REQ) ? iord_data : 8'hxx;
    MEM_DATA_IN  = (MEM_TRAN && MEM_RD && !WAIT_REQ) ? rd_data : 8'hxx;
    end
 
  always @ (posedge TREF6) begin
    IVEC_DATA_IN = (IACK_TRAN && IVEC_RD && !WAIT_REQ) ? rd_data : 8'hxx;
    end
 
  always @ (posedge TREF0) begin
    IO_DATA_IN   = 8'hxx;
    MEM_DATA_IN  = 8'hxx;
    IVEC_DATA_IN = 8'hxx;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* instantiate the design                                                                */
  /*                                                                                       */
  /*****************************************************************************************/
  y80_top Y80 ( .dma_ack(DMA_ACK), .halt_tran(HALT_TRAN), .iack_tran(IACK_TRAN),
                .io_addr_out(IO_ADDR), .io_data_out(IO_DATA_OUT), .io_read(IO_READ),
                .io_strobe(IO_STROBE), .io_tran(IO_TRAN), .ivec_rd(IVEC_RD),
                .mem_addr_out(MEM_ADDR), .mem_data_out(MEM_DATA_OUT), .mem_rd(MEM_RD),
                .mem_tran(MEM_TRAN), .mem_wr(MEM_WR), .reti_tran(RETI_TRAN), .t1(T1),
                .clearb(CLEARB), .clkc(CLKC), .dma_req(DMA_REQ), .int_req(INT_REQ),
                .io_data_in(IO_DATA_IN), .ivec_data_in(IVEC_DATA_IN),
                .mem_data_in(MEM_DATA_IN), .nmi_req(NMI_REQ), .resetb(RESETB),
                .wait_req(WAIT_REQ) );
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* timing generator                                                                      */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    TREF0 = 1;
    CLKC  = 1;
    end
 
  always begin
    #10 TREF0 <= 1'b0;
        TREF1 <= 1'b1;
    #10 TREF1 <= 1'b0;
        TREF2 <= 1'b1;
    #10 TREF2 <= 1'b0;
        TREF3 <= 1'b1;
    #10 TREF3 <= 1'b0;
        TREF4 <= 1'b1;
    #10 TREF4 <= 1'b0;
        TREF5 <= 1'b1;
    #10 TREF5 <= 1'b0;
        TREF6 <= 1'b1;
    #10 TREF6 <= 1'b0;
        TREF7 <= 1'b1;
    #10 TREF7 <= 1'b0;
        TREF8 <= 1'b1;
    #10 TREF8 <= 1'b0;
        TREF9 <= 1'b1;
    #10 TREF9 <= 1'b0;
        TREF0 <= 1'b1;
    end
 
  always @ (posedge TREF3) CLKC = 0;
  always @ (posedge TREF8) CLKC = 1;
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* initialize input signals                                                              */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    CLEARB    = 1;
    DMA_REQ   = 0;
    INT_REQ   = 0;
    NMI_REQ   = 0;
    RESETB    = 1;
    WAIT_REQ  = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* initialize testbench variables                                                        */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    breq_mach    = 6'b000000;
    CMP_ERR_L    = 16'h0000;
    CLR_INT      = 0;
    CLR_NMI      = 0;
    DISABLE_BREQ = 1;
    DISABLE_INT  = 1;
    DISABLE_WAIT = 1;
    INT_TYPE     = 0;
    PAT_DONE     = 0;
    TRIG_INT     = 0;
    TRIG_NMI     = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* reset and clear task                                                                  */
  /*                                                                                       */
  /*****************************************************************************************/
  task resettask;
    begin
      wait(TREF6);
      RESETB   = 0;
      wait(TREF0);
      wait(TREF6);
      wait(TREF0);
      wait(TREF6);
      RESETB   = 1;
      CLR_INT  = 1;
      CLR_NMI  = 1;
      wait(TREF0);
      PAT_DONE = 0;
      end
    endtask
 
  task cleartask;
    begin
      wait(TREF6);
      CLEARB   = 0;
      RESETB   = 0;
      wait(TREF0);
      wait(TREF6);
      wait(TREF0);
      wait(TREF6);
      CLEARB   = 1;
      RESETB   = 1;
      CLR_INT  = 1;
      CLR_NMI  = 1;
      wait(TREF0);
      PAT_DONE = 0;
      end
    endtask
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* error log                                                                             */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge TREF4) begin
    if (MEM_WR)                CMP_ERR_L = CMP_ERR_L + (MEM_DATA_OUT != wr_data);
    if (!IO_READ && IO_STROBE) CMP_ERR_L = CMP_ERR_L + (IO_DATA_OUT  != wr_data);
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* end-of-pattern detect                                                                 */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge TREF4) begin
    PAT_DONE  = (MEM_ADDR[15:0] == 16'h00c3);
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* interrupt/nmi request generator                                                       */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge TREF4) begin
    TRIG_INT = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h0ff)) ||
                 DISABLE_INT || |breq_mach;
    TRIG_NMI = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h1ff)) ||
                 DISABLE_INT || |breq_mach;
    CLR_INT  = (MEM_ADDR[15:13] == 3'b111);
    CLR_NMI  = (MEM_ADDR[15:13] == 3'b111);
    if (T1) INT_TYPE = MEM_ADDR[8];
    end
 
  always @ (negedge TRIG_NMI) begin
    NMI_REQ = 1;
    end
 
  always @ (posedge CLR_NMI) begin
    NMI_REQ = 0;
    end
 
  always @ (negedge TRIG_INT) begin
    INT_REQ = 1;
    end
 
  always @ (posedge CLR_INT) begin
    wait(TREF0);
    wait(TREF4);
    wait(TREF0);
    wait(TREF4);
    INT_REQ = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* interrupt request generator (during Halt)                                             */
  /*                                                                                       */
  /*****************************************************************************************/
  integer j;
 
  always @ (posedge HALT_TRAN) begin
    for (j=0; j < 10; j=j+1) begin
      wait (TREF6);
      wait (TREF0);
      end
    wait (TREF6);
    INT_REQ = HALT_TRAN && !INT_TYPE;
    NMI_REQ = HALT_TRAN &&  INT_TYPE;
    wait (TREF0);
    for (j=0; j < 12; j=j+1) begin
      wait (TREF6);
      wait (TREF0);
      end
    INT_REQ = 0;
    NMI_REQ = 0;
    wait (TREF6);
    wait (TREF0);
    wait (TREF6);
    NMI_REQ = HALT_TRAN &&  INT_TYPE;
    wait (TREF0);
    wait (TREF6);
    wait (TREF0);
    NMI_REQ = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* wait request generator                                                                */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge CLKC) begin
    wait_dly <= T1;
    end
 
  always @ (posedge TREF6) WAIT_REQ = !DISABLE_WAIT && (T1 || wait_dly);
  always @ (posedge TREF9) WAIT_REQ = 1'b0;
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* bus request generator                                                                 */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge CLKC) begin
    breq_mach <= (DISABLE_BREQ) ? 6'b000000 :
                 (T1)           ? 6'b000001 : {breq_mach[4:0], wait_dly};
    end
 
  always @ (posedge TREF6) DMA_REQ = !DISABLE_BREQ &&
                                     (T1 || |breq_mach[2:0] || (HALT_TRAN && |breq_mach));
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* run the test patterns                                                                 */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    $readmemh("setup_hl.vm", rdmem);
    cleartask;
    wait (PAT_DONE);
 
    DISABLE_INT = 0;                                       /* interrupt generator on       */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h1;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("int_ops.vm",  rdmem);
    $readmemh("int_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 1;                                      /* interrupt generator off      */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h2;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("alu_ops.vm", rdmem);
    $readmemh("alu_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h3;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("dat_mov.vm", rdmem);
    $readmemh("dat_movd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h4;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("bit_ops.vm", rdmem);
    $readmemh("bit_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h5;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("jmp_ops.vm", rdmem);
    $readmemh("jmp_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h6;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("io_ops.vm", rdmem);
    $readmemh("io_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 0;                                      /* interrupt generator on       */
    DISABLE_WAIT = 0;                                      /* wait generator on            */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h1;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("int_ops.vm", rdmem);
    $readmemh("int_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 1;                                      /* interrupt generator off      */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h2;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("alu_ops.vm", rdmem);
    $readmemh("alu_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h3;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("dat_mov.vm", rdmem);
    $readmemh("dat_movd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h4;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("bit_ops.vm", rdmem);
    $readmemh("bit_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h5;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("jmp_ops.vm", rdmem);
    $readmemh("jmp_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h6;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("io_ops.vm", rdmem);
    $readmemh("io_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 0;                                      /* interrupt generator on       */
    DISABLE_BREQ = 0;                                      /* bus req generator on         */
    DISABLE_WAIT = 1;                                      /* wait generator off           */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h1;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("int_ops.vm", rdmem);
    $readmemh("int_opss.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 1;                                      /* interrupt generator off      */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h2;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("alu_ops.vm", rdmem);
    $readmemh("alu_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h3;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("dat_mov.vm", rdmem);
    $readmemh("dat_movd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h4;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("bit_ops.vm", rdmem);
    $readmemh("bit_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h5;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("jmp_ops.vm", rdmem);
    $readmemh("jmp_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 4'h6;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("io_ops.vm", rdmem);
    $readmemh("io_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    $stop;
    end
 
  endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories y80e

[/] [y80e/] [trunk/] [rtl/] [top_levl.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	bsa	`/*******************************************************************************************/`
2			`/ /`
3			`/ COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED /`
4			`/ /`
5			`/ Y80 processor test bench Rev 0.0 08/20/2011 /`
6			`/ /`
7			`/*******************************************************************************************/`
8			`timescale 1ns / 10ps /* set time scale */
9			`include "version.v" /* select version */
10			`include "hierarchy.v" /* include sources */
11
12			`module top_levl;`
13
14			`wire DMA_ACK; /* dma acknowledge */`
15			`wire HALT_TRAN; /* halt transaction */`
16			`wire IACK_TRAN; /* int ack transaction */`
17			`wire IO_READ; /* i/o read/write status */`
18			`wire IO_STROBE; /* i/o strobe */`
19			`wire IO_TRAN; /* i/o transaction */`
20			`wire IVEC_RD; /* int vector read strobe */`
21			`wire MEM_RD; /* mem read strobe */`
22			`wire MEM_TRAN; /* mem transaction */`
23			`wire MEM_WR; /* mem write strobe */`
24			`wire RETI_TRAN; /* reti transaction */`
25			`wire T1; /* first clock of transaction */`
26			`wire [7:0] IO_DATA_OUT; /* i/o data output bus */`
27			`wire [7:0] MEM_DATA_OUT; /* mem data output bus */`
28			`wire [15:0] IO_ADDR; /* i/o address bus */`
29			`wire [15:0] MEM_ADDR; /* mem address bus */`
30
31			`reg CLEARB; /* master (test) reset */`
32			`reg CLKC; /* clock */`
33			`reg DMA_REQ; /* dma request */`
34			`reg INT_REQ; /* interrupt request */`
35			`reg NMI_REQ; /* non-maskable interrupt req */`
36			`reg RESETB; /* internal (user) reset */`
37			`reg WAIT_REQ; /* wait request */`
38			`reg [7:0] IO_DATA_IN; /* i/o data input bus */`
39			`reg [7:0] IVEC_DATA_IN; /* vector input bus */`
40			`reg [7:0] MEM_DATA_IN; /* mem data input bus */`
41
42			`/*****************************************************************************************/`
43			`/* */`
44			`/* testbench internal variables */`
45			`/* */`
46			`/*****************************************************************************************/`
47			`reg CLR_INT; /* deassert interrupt */`
48			`reg CLR_NMI; /* deassert nmi */`
49			`reg DISABLE_BREQ; /* bus req generator control */`
50			`reg DISABLE_INT; /* interrupt generator control */`
51			`reg DISABLE_WAIT; /* wait generator control */`
52			`reg INT_TYPE; /* int type during bus req */`
53			`reg PAT_DONE; /* pattern done flag */`
54			`reg TRIG_INT; /* assert interrupt */`
55			`reg TRIG_NMI; /* assert nmi */`
56			`reg [2:0] PAT_CNT; /* counter to track patterns */`
57			`reg [15:0] CMP_ERR_L; /* error counter */`
58
59			`reg wait_dly; /* wait request state machine */`
60			`reg [5:0] breq_mach; /* bus request state machine */`
61
62			`reg TREF0, TREF1, TREF2, TREF3, TREF4; /* timing generator */`
63			`reg TREF5, TREF6, TREF7, TREF8, TREF9;`
64
65			`/*****************************************************************************************/`
66			`/* */`
67			`/* read memory and write data compare memory */`
68			`/* */`
69			`/*****************************************************************************************/`
70			`reg [7:0] rdmem [0:65535];`
71			`reg [7:0] wrmem [0:65535];`
72
73			`wire [7:0] wr_data = (MEM_TRAN) ? wrmem[MEM_ADDR] :`
74			`(IO_TRAN) ? wrmem[IO_ADDR] : 8'hxx;`
75
76			`wire [7:0] rd_data = rdmem[MEM_ADDR];`
77			`wire [7:0] iord_data = rdmem[IO_ADDR];`
78
79			`always @ (posedge TREF6) begin`
80			`IO_DATA_IN = (IO_TRAN && IO_READ && IO_STROBE && !WAIT_REQ) ? iord_data : 8'hxx;`
81			`MEM_DATA_IN = (MEM_TRAN && MEM_RD && !WAIT_REQ) ? rd_data : 8'hxx;`
82			`end`
83
84			`always @ (posedge TREF6) begin`
85			`IVEC_DATA_IN = (IACK_TRAN && IVEC_RD && !WAIT_REQ) ? rd_data : 8'hxx;`
86			`end`
87
88			`always @ (posedge TREF0) begin`
89			`IO_DATA_IN = 8'hxx;`
90			`MEM_DATA_IN = 8'hxx;`
91			`IVEC_DATA_IN = 8'hxx;`
92			`end`
93
94			`/*****************************************************************************************/`
95			`/* */`
96			`/* instantiate the design */`
97			`/* */`
98			`/*****************************************************************************************/`
99			`y80_top Y80 ( .dma_ack(DMA_ACK), .halt_tran(HALT_TRAN), .iack_tran(IACK_TRAN),`
100			`.io_addr_out(IO_ADDR), .io_data_out(IO_DATA_OUT), .io_read(IO_READ),`
101			`.io_strobe(IO_STROBE), .io_tran(IO_TRAN), .ivec_rd(IVEC_RD),`
102			`.mem_addr_out(MEM_ADDR), .mem_data_out(MEM_DATA_OUT), .mem_rd(MEM_RD),`
103			`.mem_tran(MEM_TRAN), .mem_wr(MEM_WR), .reti_tran(RETI_TRAN), .t1(T1),`
104			`.clearb(CLEARB), .clkc(CLKC), .dma_req(DMA_REQ), .int_req(INT_REQ),`
105			`.io_data_in(IO_DATA_IN), .ivec_data_in(IVEC_DATA_IN),`
106			`.mem_data_in(MEM_DATA_IN), .nmi_req(NMI_REQ), .resetb(RESETB),`
107			`.wait_req(WAIT_REQ) );`
108
109			`/*****************************************************************************************/`
110			`/* */`
111			`/* timing generator */`
112			`/* */`
113			`/*****************************************************************************************/`
114			`initial begin`
115			`TREF0 = 1;`
116			`CLKC = 1;`
117			`end`
118
119			`always begin`
120			`#10 TREF0 <= 1'b0;`
121			`TREF1 <= 1'b1;`
122			`#10 TREF1 <= 1'b0;`
123			`TREF2 <= 1'b1;`
124			`#10 TREF2 <= 1'b0;`
125			`TREF3 <= 1'b1;`
126			`#10 TREF3 <= 1'b0;`
127			`TREF4 <= 1'b1;`
128			`#10 TREF4 <= 1'b0;`
129			`TREF5 <= 1'b1;`
130			`#10 TREF5 <= 1'b0;`
131			`TREF6 <= 1'b1;`
132			`#10 TREF6 <= 1'b0;`
133			`TREF7 <= 1'b1;`
134			`#10 TREF7 <= 1'b0;`
135			`TREF8 <= 1'b1;`
136			`#10 TREF8 <= 1'b0;`
137			`TREF9 <= 1'b1;`
138			`#10 TREF9 <= 1'b0;`
139			`TREF0 <= 1'b1;`
140			`end`
141
142			`always @ (posedge TREF3) CLKC = 0;`
143			`always @ (posedge TREF8) CLKC = 1;`
144
145			`/*****************************************************************************************/`
146			`/* */`
147			`/* initialize input signals */`
148			`/* */`
149			`/*****************************************************************************************/`
150			`initial begin`
151			`CLEARB = 1;`
152			`DMA_REQ = 0;`
153			`INT_REQ = 0;`
154			`NMI_REQ = 0;`
155			`RESETB = 1;`
156			`WAIT_REQ = 0;`
157			`end`
158
159			`/*****************************************************************************************/`
160			`/* */`
161			`/* initialize testbench variables */`
162			`/* */`
163			`/*****************************************************************************************/`
164			`initial begin`
165			`breq_mach = 6'b000000;`
166			`CMP_ERR_L = 16'h0000;`
167			`CLR_INT = 0;`
168			`CLR_NMI = 0;`
169			`DISABLE_BREQ = 1;`
170			`DISABLE_INT = 1;`
171			`DISABLE_WAIT = 1;`
172			`INT_TYPE = 0;`
173			`PAT_DONE = 0;`
174			`TRIG_INT = 0;`
175			`TRIG_NMI = 0;`
176			`end`
177
178			`/*****************************************************************************************/`
179			`/* */`
180			`/* reset and clear task */`
181			`/* */`
182			`/*****************************************************************************************/`
183			`task resettask;`
184			`begin`
185			`wait(TREF6);`
186			`RESETB = 0;`
187			`wait(TREF0);`
188			`wait(TREF6);`
189			`wait(TREF0);`
190			`wait(TREF6);`
191			`RESETB = 1;`
192			`CLR_INT = 1;`
193			`CLR_NMI = 1;`
194			`wait(TREF0);`
195			`PAT_DONE = 0;`
196			`end`
197			`endtask`
198
199			`task cleartask;`
200			`begin`
201			`wait(TREF6);`
202			`CLEARB = 0;`
203			`RESETB = 0;`
204			`wait(TREF0);`
205			`wait(TREF6);`
206			`wait(TREF0);`
207			`wait(TREF6);`
208			`CLEARB = 1;`
209			`RESETB = 1;`
210			`CLR_INT = 1;`
211			`CLR_NMI = 1;`
212			`wait(TREF0);`
213			`PAT_DONE = 0;`
214			`end`
215			`endtask`
216
217			`/*****************************************************************************************/`
218			`/* */`
219			`/* error log */`
220			`/* */`
221			`/*****************************************************************************************/`
222			`always @ (posedge TREF4) begin`
223			`if (MEM_WR) CMP_ERR_L = CMP_ERR_L + (MEM_DATA_OUT != wr_data);`
224			`if (!IO_READ && IO_STROBE) CMP_ERR_L = CMP_ERR_L + (IO_DATA_OUT != wr_data);`
225			`end`
226
227			`/*****************************************************************************************/`
228			`/* */`
229			`/* end-of-pattern detect */`
230			`/* */`
231			`/*****************************************************************************************/`
232			`always @ (posedge TREF4) begin`
233			`PAT_DONE = (MEM_ADDR[15:0] == 16'h00c3);`
234			`end`
235
236			`/*****************************************************************************************/`
237			`/* */`
238			`/* interrupt/nmi request generator */`
239			`/* */`
240			`/*****************************************************************************************/`
241			`always @ (posedge TREF4) begin`
242			`TRIG_INT = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h0ff)) \|\|`
243			`DISABLE_INT \|\| \|breq_mach;`
244			`TRIG_NMI = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h1ff)) \|\|`
245			`DISABLE_INT \|\| \|breq_mach;`
246			`CLR_INT = (MEM_ADDR[15:13] == 3'b111);`
247			`CLR_NMI = (MEM_ADDR[15:13] == 3'b111);`
248			`if (T1) INT_TYPE = MEM_ADDR[8];`
249			`end`
250
251			`always @ (negedge TRIG_NMI) begin`
252			`NMI_REQ = 1;`
253			`end`
254
255			`always @ (posedge CLR_NMI) begin`
256			`NMI_REQ = 0;`
257			`end`
258
259			`always @ (negedge TRIG_INT) begin`
260			`INT_REQ = 1;`
261			`end`
262
263			`always @ (posedge CLR_INT) begin`
264			`wait(TREF0);`
265			`wait(TREF4);`
266			`wait(TREF0);`
267			`wait(TREF4);`
268			`INT_REQ = 0;`
269			`end`
270
271			`/*****************************************************************************************/`
272			`/* */`
273			`/* interrupt request generator (during Halt) */`
274			`/* */`
275			`/*****************************************************************************************/`
276			`integer j;`
277
278			`always @ (posedge HALT_TRAN) begin`
279			`for (j=0; j < 10; j=j+1) begin`
280			`wait (TREF6);`
281			`wait (TREF0);`
282			`end`
283			`wait (TREF6);`
284			`INT_REQ = HALT_TRAN && !INT_TYPE;`
285			`NMI_REQ = HALT_TRAN && INT_TYPE;`
286			`wait (TREF0);`
287			`for (j=0; j < 12; j=j+1) begin`
288			`wait (TREF6);`
289			`wait (TREF0);`
290			`end`
291			`INT_REQ = 0;`
292			`NMI_REQ = 0;`
293			`wait (TREF6);`
294			`wait (TREF0);`
295			`wait (TREF6);`
296			`NMI_REQ = HALT_TRAN && INT_TYPE;`
297			`wait (TREF0);`
298			`wait (TREF6);`
299			`wait (TREF0);`
300			`NMI_REQ = 0;`
301			`end`
302
303			`/*****************************************************************************************/`
304			`/* */`
305			`/* wait request generator */`
306			`/* */`
307			`/*****************************************************************************************/`
308			`always @ (posedge CLKC) begin`
309			`wait_dly <= T1;`
310			`end`
311
312			`always @ (posedge TREF6) WAIT_REQ = !DISABLE_WAIT && (T1 \|\| wait_dly);`
313			`always @ (posedge TREF9) WAIT_REQ = 1'b0;`
314
315			`/*****************************************************************************************/`
316			`/* */`
317			`/* bus request generator */`
318			`/* */`
319			`/*****************************************************************************************/`
320			`always @ (posedge CLKC) begin`
321			`breq_mach <= (DISABLE_BREQ) ? 6'b000000 :`
322			`(T1) ? 6'b000001 : {breq_mach[4:0], wait_dly};`
323			`end`
324
325			`always @ (posedge TREF6) DMA_REQ = !DISABLE_BREQ &&`
326			`(T1 \|\| \|breq_mach[2:0] \|\| (HALT_TRAN && \|breq_mach));`
327
328			`/*****************************************************************************************/`
329			`/* */`
330			`/* run the test patterns */`
331			`/* */`
332			`/*****************************************************************************************/`
333			`initial begin`
334			`$readmemh("setup_hl.vm", rdmem);`
335			`cleartask;`
336			`wait (PAT_DONE);`
337
338			`DISABLE_INT = 0; /* interrupt generator on */`
339
340			`resettask;`
341			`CMP_ERR_L = 16'h0000;`
342			`PAT_CNT = 4'h1;`
343			`$readmemh("blank_xx.vm", rdmem);`
344			`$readmemh("blank_xx.vm", wrmem);`
345			`$readmemh("int_ops.vm", rdmem);`
346			`$readmemh("int_opsd.vm", wrmem);`
347			`wait (PAT_DONE);`
348
349			`DISABLE_INT = 1; /* interrupt generator off */`
350
351			`resettask;`
352			`CMP_ERR_L = 16'h0000;`
353			`PAT_CNT = 4'h2;`
354			`$readmemh("blank_xx.vm", rdmem);`
355			`$readmemh("blank_xx.vm", wrmem);`
356			`$readmemh("alu_ops.vm", rdmem);`
357			`$readmemh("alu_opsd.vm", wrmem);`
358			`wait (PAT_DONE);`
359
360			`resettask;`
361			`CMP_ERR_L = 16'h0000;`
362			`PAT_CNT = 4'h3;`
363			`$readmemh("blank_xx.vm", rdmem);`
364			`$readmemh("blank_xx.vm", wrmem);`
365			`$readmemh("dat_mov.vm", rdmem);`
366			`$readmemh("dat_movd.vm", wrmem);`
367			`wait (PAT_DONE);`
368
369			`resettask;`
370			`CMP_ERR_L = 16'h0000;`
371			`PAT_CNT = 4'h4;`
372			`$readmemh("blank_xx.vm", rdmem);`
373			`$readmemh("blank_xx.vm", wrmem);`
374			`$readmemh("bit_ops.vm", rdmem);`
375			`$readmemh("bit_opsd.vm", wrmem);`
376			`wait (PAT_DONE);`
377
378			`resettask;`
379			`CMP_ERR_L = 16'h0000;`
380			`PAT_CNT = 4'h5;`
381			`$readmemh("blank_xx.vm", rdmem);`
382			`$readmemh("blank_xx.vm", wrmem);`
383			`$readmemh("jmp_ops.vm", rdmem);`
384			`$readmemh("jmp_opsd.vm", wrmem);`
385			`wait (PAT_DONE);`
386
387			`resettask;`
388			`CMP_ERR_L = 16'h0000;`
389			`PAT_CNT = 4'h6;`
390			`$readmemh("blank_xx.vm", rdmem);`
391			`$readmemh("blank_xx.vm", wrmem);`
392			`$readmemh("io_ops.vm", rdmem);`
393			`$readmemh("io_opsd.vm", wrmem);`
394			`wait (PAT_DONE);`
395
396			`DISABLE_INT = 0; /* interrupt generator on */`
397			`DISABLE_WAIT = 0; /* wait generator on */`
398
399			`resettask;`
400			`CMP_ERR_L = 16'h0000;`
401			`PAT_CNT = 4'h1;`
402			`$readmemh("blank_xx.vm", rdmem);`
403			`$readmemh("blank_xx.vm", wrmem);`
404			`$readmemh("int_ops.vm", rdmem);`
405			`$readmemh("int_opsd.vm", wrmem);`
406			`wait (PAT_DONE);`
407
408			`DISABLE_INT = 1; /* interrupt generator off */`
409
410			`resettask;`
411			`CMP_ERR_L = 16'h0000;`
412			`PAT_CNT = 4'h2;`
413			`$readmemh("blank_xx.vm", rdmem);`
414			`$readmemh("blank_xx.vm", wrmem);`
415			`$readmemh("alu_ops.vm", rdmem);`
416			`$readmemh("alu_opsd.vm", wrmem);`
417			`wait (PAT_DONE);`
418
419			`resettask;`
420			`CMP_ERR_L = 16'h0000;`
421			`PAT_CNT = 4'h3;`
422			`$readmemh("blank_xx.vm", rdmem);`
423			`$readmemh("blank_xx.vm", wrmem);`
424			`$readmemh("dat_mov.vm", rdmem);`
425			`$readmemh("dat_movd.vm", wrmem);`
426			`wait (PAT_DONE);`
427
428			`resettask;`
429			`CMP_ERR_L = 16'h0000;`
430			`PAT_CNT = 4'h4;`
431			`$readmemh("blank_xx.vm", rdmem);`
432			`$readmemh("blank_xx.vm", wrmem);`
433			`$readmemh("bit_ops.vm", rdmem);`
434			`$readmemh("bit_opsd.vm", wrmem);`
435			`wait (PAT_DONE);`
436
437			`resettask;`
438			`CMP_ERR_L = 16'h0000;`
439			`PAT_CNT = 4'h5;`
440			`$readmemh("blank_xx.vm", rdmem);`
441			`$readmemh("blank_xx.vm", wrmem);`
442			`$readmemh("jmp_ops.vm", rdmem);`
443			`$readmemh("jmp_opsd.vm", wrmem);`
444			`wait (PAT_DONE);`
445
446			`resettask;`
447			`CMP_ERR_L = 16'h0000;`
448			`PAT_CNT = 4'h6;`
449			`$readmemh("blank_xx.vm", rdmem);`
450			`$readmemh("blank_xx.vm", wrmem);`
451			`$readmemh("io_ops.vm", rdmem);`
452			`$readmemh("io_opsd.vm", wrmem);`
453			`wait (PAT_DONE);`
454
455			`DISABLE_INT = 0; /* interrupt generator on */`
456			`DISABLE_BREQ = 0; /* bus req generator on */`
457			`DISABLE_WAIT = 1; /* wait generator off */`
458
459			`resettask;`
460			`CMP_ERR_L = 16'h0000;`
461			`PAT_CNT = 4'h1;`
462			`$readmemh("blank_xx.vm", rdmem);`
463			`$readmemh("blank_xx.vm", wrmem);`
464			`$readmemh("int_ops.vm", rdmem);`
465			`$readmemh("int_opss.vm", wrmem);`
466			`wait (PAT_DONE);`
467
468			`DISABLE_INT = 1; /* interrupt generator off */`
469
470			`resettask;`
471			`CMP_ERR_L = 16'h0000;`
472			`PAT_CNT = 4'h2;`
473			`$readmemh("blank_xx.vm", rdmem);`
474			`$readmemh("blank_xx.vm", wrmem);`
475			`$readmemh("alu_ops.vm", rdmem);`
476			`$readmemh("alu_opsd.vm", wrmem);`
477			`wait (PAT_DONE);`
478
479			`resettask;`
480			`CMP_ERR_L = 16'h0000;`
481			`PAT_CNT = 4'h3;`
482			`$readmemh("blank_xx.vm", rdmem);`
483			`$readmemh("blank_xx.vm", wrmem);`
484			`$readmemh("dat_mov.vm", rdmem);`
485			`$readmemh("dat_movd.vm", wrmem);`
486			`wait (PAT_DONE);`
487
488			`resettask;`
489			`CMP_ERR_L = 16'h0000;`
490			`PAT_CNT = 4'h4;`
491			`$readmemh("blank_xx.vm", rdmem);`
492			`$readmemh("blank_xx.vm", wrmem);`
493			`$readmemh("bit_ops.vm", rdmem);`
494			`$readmemh("bit_opsd.vm", wrmem);`
495			`wait (PAT_DONE);`
496
497			`resettask;`
498			`CMP_ERR_L = 16'h0000;`
499			`PAT_CNT = 4'h5;`
500			`$readmemh("blank_xx.vm", rdmem);`
501			`$readmemh("blank_xx.vm", wrmem);`
502			`$readmemh("jmp_ops.vm", rdmem);`
503			`$readmemh("jmp_opsd.vm", wrmem);`
504			`wait (PAT_DONE);`
505
506			`resettask;`
507			`CMP_ERR_L = 16'h0000;`
508			`PAT_CNT = 4'h6;`
509			`$readmemh("blank_xx.vm", rdmem);`
510			`$readmemh("blank_xx.vm", wrmem);`
511			`$readmemh("io_ops.vm", rdmem);`
512			`$readmemh("io_opsd.vm", wrmem);`
513			`wait (PAT_DONE);`
514
515			`$stop;`
516			`end`
517
518			`endmodule`
519
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