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----------------------------------------------------------------------------
----                                                                    ----
----                  Copyright Notice                                  ----
----                                                                    ----
---- This file is part of YAC - Yet Another CORDIC Core                 ----
---- Copyright (c) 2014, Author(s), All rights reserved.                ----
----                                                                    ----
---- YAC is free software; you can redistribute it and/or               ----
---- modify it under the terms of the GNU Lesser General Public         ----
---- License as published by the Free Software Foundation; either       ----
---- version 3.0 of the License, or (at your option) any later version. ----
----                                                                    ----
---- YAC is distributed in the hope that it will be useful,             ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of     ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU  ----
---- Lesser General Public License for more details.                    ----
----                                                                    ----
---- You should have received a copy of the GNU Lesser General Public   ----
---- License along with this library. If not, download it from          ----
---- http://www.gnu.org/licenses/lgpl                                   ----
----                                                                    ----
----------------------------------------------------------------------------
 
 
 
<<<<<<< HEAD
<<<<<<< HEAD
=======
>>>>>>> Updated C and RTL model as well as the documentation
         Author(s):  Christian Haettich
         Email       feddischson@opencores.org
 
 
 
 
 
 
Description
------------------
 
CORDIC is the acronym for COordinate Rotation DIgital Computer and
allows a hardware efficient calculation of various functions
like - atan, sin, cos - atanh, sinh, cosh, - division, multiplication.
Hardware efficient means, that only shifting, additions and
subtractions in combination with table-lookup is required. This makes
it suitable for a realization in digital hardware. Good
introductions can be found in [1][2][3][5].
 
 
 
The following six CORDIC modes are supported:
- trigonometric rotation
- trigonometric vectoring
- linear rotation
- linear vectoring
- hyperbolic rotation
- hyperbolic vectoring
 
 
Furthermore, the CORDIC algorithm is implemented for iterative
processing which means, that the IP-core is started
with a set of input data and after a specific amount of
clock cycles, the result is
available. No parallel data can be processed.
 
In addition to an IP-core written in VHDL, a bit-accurate C-model
is provided. This C-model can be compiled as mex for a usage with Octave or
Matlab. Therefore, this C-model allows a bit-accurate analysis
of the CORDIC performance on a higher level.
 
 
For a more detailed documentation, see ./doc/documentation.pdf
 
 
 
 
 
Status
----------------------
- C-model implementation is done
- RTL model implementation is done
- RTL model is verified against C-model
- Wishbone-bus wrapper is added
- Included into a small SoC, tested on a spartan-3 FPGA
- Testing within an SOC is done (see ./test_sys)
 
 
 
 
Next-Steps
-----------------------
- Circuit optimizations
- Numerical optimizations
 
 
 
<<<<<<< HEAD
=======
>>>>>>> initial commit
=======
>>>>>>> Updated C and RTL model as well as the documentation
 
Files and folders:
------------------
 
 ./c_octave :  contains a bit-accurate C-implementation of the YAC.
               This C-implementation is used for analyzing the performance
               and to generate RTL testbench stimulus
               (cordic_iterative_test.m).
               The file cordic_iterative_code.m is used to create some
               VHDL/C-code automatically.
 
 ./rtl/vhdl :  Contains the VHDL implementation files
 
 ./doc      :  Will contain a detailed documentation in future.
 
 ./test_sys :  Contains a test system to test the YAC on a spartan-3an board
 
 
<<<<<<< HEAD
<<<<<<< HEAD
=======
>>>>>>> Updated C and RTL model as well as the documentation
 
 
[1] Andraka, Ray; A survey of CORDIC algorithms for FPGA based computers, 1989
[2] Hu, Yu Hen; CORDIC-Based VLSI Architectures for Digital Signal Processing, 1992
[3] CORDIC on wikibook: http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC
[4] CORDIC on wikipedia:http://en.wikipedia.org/wiki/CORDIC
[5] David, Herbert; Meyr, Heinricht; CORDIC Algorithms and Architectures
    http://www.eecs.berkeley.edu/newton/Classes/EE290sp99/lectures/ee290aSp996_1/cordic_chap24.pdf
 
 
<<<<<<< HEAD
=======
>>>>>>> initial commit
=======
>>>>>>> Updated C and RTL model as well as the documentation

Line No.	Rev	Author	Line
1	2	feddischso	`----------------------------------------------------------------------------`
2			`---- ----`
3			`---- Copyright Notice ----`
4			`---- ----`
5			`---- This file is part of YAC - Yet Another CORDIC Core ----`
6			`---- Copyright (c) 2014, Author(s), All rights reserved. ----`
7			`---- ----`
8			`---- YAC is free software; you can redistribute it and/or ----`
9			`---- modify it under the terms of the GNU Lesser General Public ----`
10			`---- License as published by the Free Software Foundation; either ----`
11			`---- version 3.0 of the License, or (at your option) any later version. ----`
12			`---- ----`
13			`---- YAC is distributed in the hope that it will be useful, ----`
14			`---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----`
15			`---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----`
16			`---- Lesser General Public License for more details. ----`
17			`---- ----`
18			`---- You should have received a copy of the GNU Lesser General Public ----`
19			`---- License along with this library. If not, download it from ----`
20			`---- http://www.gnu.org/licenses/lgpl ----`
21			`---- ----`
22			`----------------------------------------------------------------------------`
23
24
25
26	3	feddischso	`<<<<<<< HEAD`
27	4	feddischso	`<<<<<<< HEAD`
28			`=======`
29			`>>>>>>> Updated C and RTL model as well as the documentation`
30	2	feddischso	`Author(s): Christian Haettich`
31			`Email feddischson@opencores.org`
32
33
34
35
36
37
38			`Description`
39			`------------------`
40
41			`CORDIC is the acronym for COordinate Rotation DIgital Computer and`
42			`allows a hardware efficient calculation of various functions`
43			`like - atan, sin, cos - atanh, sinh, cosh, - division, multiplication.`
44			`Hardware efficient means, that only shifting, additions and`
45			`subtractions in combination with table-lookup is required. This makes`
46			`it suitable for a realization in digital hardware. Good`
47			`introductions can be found in [1][2][3][5].`
48
49
50	6	feddischso
51	2	feddischso	`The following six CORDIC modes are supported:`
52			`- trigonometric rotation`
53			`- trigonometric vectoring`
54			`- linear rotation`
55			`- linear vectoring`
56			`- hyperbolic rotation`
57			`- hyperbolic vectoring`
58
59
60			`Furthermore, the CORDIC algorithm is implemented for iterative`
61			`processing which means, that the IP-core is started`
62			`with a set of input data and after a specific amount of`
63			`clock cycles, the result is`
64			`available. No parallel data can be processed.`
65
66			`In addition to an IP-core written in VHDL, a bit-accurate C-model`
67			`is provided. This C-model can be compiled as mex for a usage with Octave or`
68			`Matlab. Therefore, this C-model allows a bit-accurate analysis`
69			`of the CORDIC performance on a higher level.`
70
71
72			`For a more detailed documentation, see ./doc/documentation.pdf`
73
74
75
76
77
78			`Status`
79			`----------------------`
80			`- C-model implementation is done`
81			`- RTL model implementation is done`
82			`- RTL model is verified against C-model`
83	6	feddischso	`- Wishbone-bus wrapper is added`
84	12	feddischso	`- Included into a small SoC, tested on a spartan-3 FPGA`
85			`- Testing within an SOC is done (see ./test_sys)`
86	2	feddischso
87
88
89
90			`Next-Steps`
91			`-----------------------`
92			`- Circuit optimizations`
93			`- Numerical optimizations`
94
95
96
97	4	feddischso	`<<<<<<< HEAD`
98	3	feddischso	`=======`
99			`>>>>>>> initial commit`
100	4	feddischso	`=======`
101			`>>>>>>> Updated C and RTL model as well as the documentation`
102	2	feddischso
103			`Files and folders:`
104			`------------------`
105
106			`./c_octave : contains a bit-accurate C-implementation of the YAC.`
107			`This C-implementation is used for analyzing the performance`
108			`and to generate RTL testbench stimulus`
109			`(cordic_iterative_test.m).`
110			`The file cordic_iterative_code.m is used to create some`
111			`VHDL/C-code automatically.`
112
113			`./rtl/vhdl : Contains the VHDL implementation files`
114
115			`./doc : Will contain a detailed documentation in future.`
116
117	12	feddischso	`./test_sys : Contains a test system to test the YAC on a spartan-3an board`
118	2	feddischso
119
120	3	feddischso	`<<<<<<< HEAD`
121	4	feddischso	`<<<<<<< HEAD`
122			`=======`
123			`>>>>>>> Updated C and RTL model as well as the documentation`
124	2	feddischso
125
126			`[1] Andraka, Ray; A survey of CORDIC algorithms for FPGA based computers, 1989`
127			`[2] Hu, Yu Hen; CORDIC-Based VLSI Architectures for Digital Signal Processing, 1992`
128			`[3] CORDIC on wikibook: http://en.wikibooks.org/wiki/Digital_Circuits/CORDIC`
129			`[4] CORDIC on wikipedia:http://en.wikipedia.org/wiki/CORDIC`
130			`[5] David, Herbert; Meyr, Heinricht; CORDIC Algorithms and Architectures`
131			`http://www.eecs.berkeley.edu/newton/Classes/EE290sp99/lectures/ee290aSp996_1/cordic_chap24.pdf`
132
133
134	4	feddischso	`<<<<<<< HEAD`
135	3	feddischso	`=======`
136			`>>>>>>> initial commit`
137	4	feddischso	`=======`
138			`>>>>>>> Updated C and RTL model as well as the documentation`

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[/] [yac/] [trunk/] [README.txt] - Blame information for rev 12