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feddischso |
----------------------------------------------------------------------------
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---- ----
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---- File : cordic_iterative_tb.vhd ----
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---- Project : YAC (Yet Another CORDIC Core) ----
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---- Creation : Feb. 2014 ----
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---- Limitations : ----
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---- Synthesizer : ----
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---- Target : ----
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---- ----
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---- Author(s): : Christian Haettich ----
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---- Email : feddischson@opencores.org ----
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---- ----
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---- ----
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----- -----
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---- ----
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---- Description ----
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---- VHDL Testbench ----
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---- ----
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---- ----
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---- ----
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----- -----
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---- ----
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---- TODO ----
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---- Some documentation ----
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---- ----
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---- ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- Copyright Notice ----
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---- ----
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---- This file is part of YAC - Yet Another CORDIC Core ----
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---- Copyright (c) 2014, Author(s), All rights reserved. ----
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---- ----
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---- YAC is free software; you can redistribute it and/or ----
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---- modify it under the terms of the GNU Lesser General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 3.0 of the License, or (at your option) any later version. ----
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---- ----
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---- YAC is distributed in the hope that it will be useful, ----
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---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
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---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----
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---- Lesser General Public License for more details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General Public ----
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---- License along with this library. If not, download it from ----
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---- http://www.gnu.org/licenses/lgpl ----
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---- ----
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----------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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library std;
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use std.textio.all; -- for reading/writing from/to files
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use std.env.all; -- for finish()
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library work;
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entity cordic_iterative_tb is
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end entity cordic_iterative_tb;
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architecture IMP of cordic_iterative_tb is
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constant FRQ_MULT_VALUE : integer :=18;
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constant stim_file : string := "../../c_octave/tb_data.txt";
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constant err_file : string := "./error_out.txt";
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constant clk_T : time := 5 ns;
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signal clk : std_logic;
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signal rst : std_logic;
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signal nrst : std_logic;
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constant XY_WIDTH : natural := 25;
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constant A_WIDTH : natural := 25;
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constant GUARD_BITS : natural := 2;
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constant RM_GAIN : natural := 5;
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component cordic_iterative_int is
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generic(
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XY_WIDTH : natural := 12;
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A_WIDTH : natural := 12;
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GUARD_BITS : natural := 2;
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RM_GAIN : natural := 4
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);
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port(
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clk, rst : in std_logic;
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en : in std_logic;
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start : in std_logic;
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done : out std_logic;
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mode_i : in std_logic_vector( 4-1 downto 0 );
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x_i : in std_logic_vector( XY_WIDTH-1 downto 0 );
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y_i : in std_logic_vector( XY_WIDTH-1 downto 0 );
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a_i : in std_logic_vector( A_WIDTH+2-1 downto 0 );
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x_o : out std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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y_o : out std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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a_o : out std_logic_vector( A_WIDTH+2-1 downto 0 )
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);
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end component cordic_iterative_int;
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signal en : std_logic;
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signal start : std_logic;
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signal done : std_logic;
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signal mode_i : std_logic_vector( 4-1 downto 0 );
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signal x_i : std_logic_vector( XY_WIDTH-1 downto 0 );
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signal y_i : std_logic_vector( XY_WIDTH-1 downto 0 );
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signal a_i : std_logic_vector( A_WIDTH+2-1 downto 0 );
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signal x_o : std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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signal y_o : std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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signal a_o : std_logic_vector( A_WIDTH+2-1 downto 0 );
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begin
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-- --
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-- clock and reset
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--
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nrst <= not rst;
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clk_gen : process
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begin
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clk <= '1';
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wait for clk_T/2;
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clk <= '0';
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wait for clk_T/2;
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end process;
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rst_gen : process
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begin
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rst <= '1';
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wait for clk_T * 10;
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rst <= '0';
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wait;
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end process;
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dut : cordic_iterative_int
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generic map (
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XY_WIDTH => XY_WIDTH ,
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A_WIDTH => A_WIDTH ,
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GUARD_BITS => GUARD_BITS,
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RM_GAIN => RM_GAIN
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)
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port map(
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clk => clk ,
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rst => rst ,
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en => en ,
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start => start ,
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done => done ,
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mode_i => mode_i ,
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x_i => x_i ,
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y_i => y_i ,
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a_i => a_i ,
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x_o => x_o ,
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y_o => y_o ,
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a_o => a_o
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);
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--
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--
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--
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stims_p : process
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file test_pattern_file : text;
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file error_pattern_file : text;
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variable file_status : file_open_status;
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variable input_line : line;
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variable input_line_bak : line;
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variable good : boolean;
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type values_t is array ( 0 to 7 ) of integer;
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variable tmp_value : values_t;
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variable x_ex : std_logic_vector( x_o'range );
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variable y_ex : std_logic_vector( y_o'range );
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variable a_ex : std_logic_vector( a_o'range );
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variable err_cnt : integer := 0;
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variable stim_cnt : integer := 0;
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begin
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err_cnt := 0;
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--
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-- open file
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--
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file_open( file_status, test_pattern_file, stim_file, READ_MODE );
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if file_status /= open_ok then
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report "unable to open input stimulation file, please use cordic_iterative_test.m to create stimulation file" severity error;
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stop( -1 );
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end if;
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file_open( file_status, error_pattern_file, err_file, WRITE_MODE );
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if file_status /= open_ok then
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report "unable to open output error file" severity error;
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stop( -1 );
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end if;
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-- wait some cycles
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x_i <= ( others => '0' );
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y_i <= ( others => '0' );
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a_i <= ( others => '0' );
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mode_i <= ( others => '0' );
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start <= '0';
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wait for clk_T * 20;
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wait until clk'event and clk='1';
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while ( not endfile( test_pattern_file ) )loop
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wait until en='1';
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wait for clk_T;
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-- read line and extract values
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readline( test_pattern_file, input_line );
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input_line_bak := new string'( input_line.ALL );
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for i in 0 to 6 loop
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read( input_line, tmp_value(i), good );
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--report "rd: "& integer'image( i ) & " : " & integer'image( tmp_value( i ) );
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end loop;
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-- assign values to DUT
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x_i <= std_logic_vector( to_signed ( tmp_value(0), x_i'length ) );
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y_i <= std_logic_vector( to_signed ( tmp_value(1), y_i'length ) );
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a_i <= std_logic_vector( to_signed ( tmp_value(2), a_i'length ) );
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x_ex := std_logic_vector( to_signed ( tmp_value(3), x_ex'length ) );
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y_ex := std_logic_vector( to_signed ( tmp_value(4), y_ex'length ) );
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a_ex := std_logic_vector( to_signed ( tmp_value(5), a_ex'length ) );
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mode_i <= std_logic_vector( to_unsigned( tmp_value(6), mode_i'length ) );
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-- start the DUT and wait, until the DUT is done
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start <= '1';
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wait for clk_T;
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start <= '0';
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wait until done = '1';
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wait until clk'event and clk='1';
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stim_cnt := stim_cnt+1;
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if x_ex /= x_o or
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y_ex /= y_o or
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a_ex /= a_o then
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assert x_ex = x_o report
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3 |
feddischso |
<<<<<<< HEAD
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2 |
feddischso |
integer'image( stim_cnt ) & ": Serial Cordic Failed: expected x result:"
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& integer'image( tmp_value(5) ) & ", but got:"
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& integer'image( to_integer( signed( x_ex ) ) );
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assert y_ex = y_o report
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integer'image( stim_cnt ) & ": Serial Cordic Failed: expected y result:"
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& integer'image( tmp_value(6) ) & ", but got:"
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& integer'image( to_integer( signed( y_ex ) ) );
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assert a_ex = a_o report
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integer'image( stim_cnt ) & ": Serial Cordic Failed: expected a result:"
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3 |
feddischso |
=======
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" Serial Cordic Failed: expected x result:"
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& integer'image( tmp_value(5) ) & ", but got:"
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& integer'image( to_integer( signed( x_ex ) ) );
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assert y_ex = y_o report
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" Serial Cordic Failed: expected y result:"
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& integer'image( tmp_value(6) ) & ", but got:"
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& integer'image( to_integer( signed( y_ex ) ) );
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assert a_ex = a_o report
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" Serial Cordic Failed: expected a result:"
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>>>>>>> initial commit
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2 |
feddischso |
& integer'image( tmp_value(7) ) & ", but got:"
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& integer'image( to_integer( signed( a_ex ) ) );
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err_cnt := err_cnt + 1;
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writeline( error_pattern_file, input_line_bak );
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end if;
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wait for CLK_T * 5;
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end loop;
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report "====>>>> Serial Cordic Verification Result:" & integer'image( err_cnt ) & " of " & integer'image( stim_cnt ) & " tests failed";
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stop( 0 );
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end process stims_p;
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en_test : process
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begin
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en <= '0';
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wait for clk_T * 10;
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en <= '1';
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wait for clk_T * 1000;
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end process;
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end architecture IMP;
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