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feddischso |
----------------------------------------------------------------------------
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---- ----
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---- File : cordic_iterative_wb.vhd ----
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---- Project : YAC (Yet Another CORDIC Core) ----
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---- Creation : Feb. 2014 ----
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---- Limitations : ----
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---- Synthesizer : ----
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---- Target : ----
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---- ----
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---- Author(s): : Christian Haettich ----
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---- Email : feddischson@opencores.org ----
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---- ----
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---- ----
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----- -----
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---- ----
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---- Description ----
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---- wb bus interface for the YAC ----
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---- ----
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---- ----
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---- ----
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----- -----
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---- ----
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---- Memory organization: ----
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---- ----------------------------------------------------------- ----
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---- | word | description | ----
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---- | index | | ----
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---- ----------------------------------------------------------- ----
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---- | 0 | x_0 \ | ----
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---- | 1 | y_0 \ 1'st entry | ----
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---- | 2 | a_0 / | ----
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---- | 3 | mode_0 / | ----
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---- | 4 | x_1 \ | ----
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---- | 5 | y_1 \ 2'nd entry | ----
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---- | 6 | a_1 / | ----
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---- | 7 | mode_1 / | ----
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---- | 8 | . | ----
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---- | | ... | ----
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---- | N_ENTRIES*4-4 | x_n \ | ----
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---- | N_ENTRIES*4-3 | y_n \ n'th entry | ----
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---- | N_ENTRIES*4-2 | a_n / | ----
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---- | N_ENTRIES*4-1 | mode_n / | ----
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---- | N_ENTRIES*4 | status-register | ----
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---- ----------------------------------------------------------- ----
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---- ----
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---- ----
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---- Status register bit fields: ----
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---- ----
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---- bit 0: ==>> start/idle flag: ----
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---- ------------------------------ ----
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---- write 1: start ----
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---- read 1: busy ----
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---- read 0: idle ----
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---- the flag is set by SW and cleared automatically ----
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---- after processing. ----
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---- ----
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---- bit 1: ==>> IRQ flag: ----
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---- ------------------------------ ----
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---- write 1: sets the IRQ ----
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---- write 0: clears the IRQ ----
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---- the flag is set automatically by HW and is mapped ----
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---- to irq_o. The software can clear the flag/irq by ----
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---- writing a 0 to this bit. ----
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---- ----
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---- ----
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---- ----
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---- bit 16...ceil(log2(N_ENTRIES)): ==>> item-count ----
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---- ----------------------------------------------- ----
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---- defines, how much items are processed, ----
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---- the processing works from the higher part to the lower ----
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---- part of the memory. ---
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---- ----
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---- ----
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---- ----
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---- ----
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--------- ------------
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---- TODO: ----
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---- - further testing ----
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---- - err_o: error output generation ----
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---- ----
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---- ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- Copyright Notice ----
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---- ----
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---- This file is part of YAC - Yet Another CORDIC Core ----
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---- Copyright (c) 2014, Author(s), All rights reserved. ----
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---- ----
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---- YAC is free software; you can redistribute it and/or ----
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---- modify it under the terms of the GNU Lesser General Public ----
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---- License as published by the Free Software Foundation; either ----
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---- version 3.0 of the License, or (at your option) any later version. ----
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---- ----
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---- YAC is distributed in the hope that it will be useful, ----
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---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
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---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----
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---- Lesser General Public License for more details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General Public ----
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---- License along with this library. If not, download it from ----
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---- http://www.gnu.org/licenses/lgpl ----
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---- ----
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----------------------------------------------------------------------------
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library ieee;
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library std;
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use std.textio.all;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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use ieee.std_logic_textio.all; -- I/O for logic types
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use work.cordic_pkg.ALL;
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entity cordic_iterative_wb is
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generic(
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WB_ADR_WIDTH : natural := 32; -- wishbone address bus width
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N_ENTRIES : natural := 16; -- number of calculation entries,
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-- which can be stored
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A_WIDTH : natural := 12; -- \
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XY_WIDTH : natural := 12; -- | Cordic setup
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GUARD_BITS : natural := 2; -- |
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RM_GAIN : natural := 3 -- /
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);
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port(
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clk_i : in std_logic;
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rst_i : in std_logic;
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dat_i : in std_logic_vector( 32-1 downto 0 );
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dat_o : out std_logic_vector( 32-1 downto 0 );
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adr_i : in std_logic_vector( WB_ADR_WIDTH-1 downto 0 );
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we_i : in std_logic;
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sel_i : in std_logic_vector( 4-1 downto 0 );
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cyc_i : in std_logic;
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stb_i : in std_logic;
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ack_o : out std_logic;
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cti_i : in std_logic_vector( 3-1 downto 0 );
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bte_i : in std_logic_vector( 2-1 downto 0 );
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irq_o : out std_logic
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);
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end entity;
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architecture IMP of cordic_iterative_wb is
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constant STATUS_REG_I : natural := N_ENTRIES*4;
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function ceil_log2(N: natural) return positive is
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begin
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if N <= 2 then
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return 1;
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else
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if N mod 2 = 0 then
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return 1 + ceil_log2( N/2 );
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else
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return 1 + ceil_log2( (N+1) / 2 );
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end if;
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end if;
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end;
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constant MEM_SIZE : natural := 32;
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--
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-- memory blocks:
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-- N_ENTRIES * ( x, y, a, mode) + status-register
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--
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type mem_t is array ( 0 to 4*N_ENTRIES+1-1 ) of std_logic_vector( MEM_SIZE-1 downto 0 );
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signal MEM : mem_t;
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-- address size (in words)
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constant ADR_WIDTH : natural := ceil_log2( 4*N_ENTRIES+1 );
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type B3_TRANS_T is ( WB_BURST, WB_NO_BURST );
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signal b3_trans : B3_TRANS_T;
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signal addr : std_logic_vector( ADR_WIDTH-1 downto 0 );
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signal addr_burst : std_logic_vector( ADR_WIDTH-1 downto 0 );
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signal cti_r : std_logic_vector( cti_i'range );
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signal bte_r : std_logic_vector( bte_i'range );
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signal dat_o_tmp : std_logic_vector( dat_o'range );
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signal wr_data : std_logic_vector( dat_i'range );
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signal ack_r : std_logic;
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signal ack : std_logic;
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signal burst_start : std_logic;
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signal burst_end : std_logic;
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component cordic_iterative_int is
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generic(
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XY_WIDTH : natural := 12;
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A_WIDTH : natural := 12;
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GUARD_BITS : natural := 2;
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RM_GAIN : natural := 4
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);
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port(
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clk, rst : in std_logic;
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en : in std_logic;
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start : in std_logic;
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done : out std_logic;
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mode_i : in std_logic_vector( 4-1 downto 0 );
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x_i : in std_logic_vector( XY_WIDTH-1 downto 0 );
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y_i : in std_logic_vector( XY_WIDTH-1 downto 0 );
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a_i : in std_logic_vector( A_WIDTH+2-1 downto 0 );
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x_o : out std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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y_o : out std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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a_o : out std_logic_vector( A_WIDTH+2-1 downto 0 )
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);
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end component cordic_iterative_int;
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signal cordic_en : std_logic;
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signal cordic_start : std_logic;
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signal cordic_done : std_logic;
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signal cordic_mode_i : std_logic_vector( 4-1 downto 0 );
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signal cordic_x_i : std_logic_vector( XY_WIDTH-1 downto 0 );
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signal cordic_y_i : std_logic_vector( XY_WIDTH-1 downto 0 );
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signal cordic_a_i : std_logic_vector( A_WIDTH+2-1 downto 0 );
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signal cordic_x_o : std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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signal cordic_y_o : std_logic_vector( XY_WIDTH+GUARD_BITS-1 downto 0 );
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signal cordic_a_o : std_logic_vector( A_WIDTH+2-1 downto 0 );
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type state_T_st is (ST_IDLE, ST_START, ST_WAIT);
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type state_T is
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record
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st : state_T_st;
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cnt : unsigned( ceil_log2( N_ENTRIES ) -1 downto 0 );
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end record;
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signal state : state_T;
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begin
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-- start of burst signal
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burst_start <= '1' when ( cti_i = "001" or cti_i = "010" )
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and stb_i = '1'
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and b3_trans /= WB_BURST
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else '0';
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-- end of burst signal
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burst_end <= '1' when cti_i = "111"
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and stb_i = '1'
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and b3_trans = WB_BURST
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and ack = '1'
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else '0';
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------
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-- Burst address generation: this depends on the number of entries
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-- and the internal address bus width
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--
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BURST_GEN_ALL : if ADR_WIDTH > 4 generate
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addr_burst <= std_logic_vector( unsigned( addr ) + 1 ) when bte_r = "00" else
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addr( addr'high downto 2 ) & std_logic_vector( unsigned( addr( 1 downto 0 ) ) + 1 ) when bte_r = "01" else
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addr( addr'high downto 3 ) & std_logic_vector( unsigned( addr( 2 downto 0 ) ) + 1 ) when bte_r = "10" else
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addr( addr'high downto 4 ) & std_logic_vector( unsigned( addr( 3 downto 0 ) ) + 1 ) when bte_r = "11";
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end generate;
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BURST_GEN_4 : if ADR_WIDTH = 4 generate
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addr_burst <= std_logic_vector( unsigned( addr ) + 1 ) when bte_r = "00" else
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addr( addr'high downto 2 ) & std_logic_vector( unsigned( addr( 1 downto 0 ) ) + 1 ) when bte_r = "01" else
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addr( addr'high downto 3 ) & std_logic_vector( unsigned( addr( 2 downto 0 ) ) + 1 ) when bte_r = "10" else
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std_logic_vector( unsigned( addr( 3 downto 0 ) ) + 1 ) when bte_r = "11";
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end generate;
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BURST_GEN_3 : if ADR_WIDTH = 3 generate
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addr_burst <= std_logic_vector( unsigned( addr ) + 1 ) when bte_r = "00" else
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addr( addr'high downto 2 ) & std_logic_vector( unsigned( addr( 1 downto 0 ) ) + 1 ) when bte_r = "01" else
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std_logic_vector( unsigned( addr( 2 downto 0 ) ) + 1 ) when bte_r = "10";
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end generate;
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BURST_GEN_2 : if ADR_WIDTH = 2 generate
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addr_burst <= std_logic_vector( unsigned( addr ) + 1 ) when bte_r = "00" else
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std_logic_vector( unsigned( addr( 1 downto 0 ) ) + 1 ) when bte_r = "01";
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end generate;
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------
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--
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-- wishbone bus transaction handling
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-- - ack generation
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-- - burst handling
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-- - address handling
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--
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p : process( clk_i, rst_i )
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begin
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if clk_i'event and clk_i='1' then
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if rst_i = '1' then
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addr <= ( others => '0' );
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b3_trans <= WB_NO_BURST;
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ack_r <= '0';
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else
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cti_r <= cti_i;
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bte_r <= bte_i;
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if burst_start = '1' then
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addr <= adr_i( ADR_WIDTH+2-1 downto 2 );
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elsif cti_r = "010" and ack = '1' and b3_trans = WB_BURST then
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addr <= addr_burst;
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else
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addr <= adr_i( ADR_WIDTH+2-1 downto 2 );
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end if;
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if burst_start = '1' then
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-- start of burst
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b3_trans <= WB_BURST;
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elsif burst_end = '1' then
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-- end of burst
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b3_trans <= WB_NO_BURST;
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elsif b3_trans = WB_BURST then
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-- during burst
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end if;
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-- ack generation
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if cyc_i = '1' then
|
| 337 |
|
|
|
| 338 |
|
|
if cti_i = "000" then
|
| 339 |
|
|
|
| 340 |
|
|
if stb_i = '1' then
|
| 341 |
|
|
ack_r <= not ack_r;
|
| 342 |
|
|
end if;
|
| 343 |
|
|
|
| 344 |
|
|
elsif cti_i = "010" or cti_i = "001" then
|
| 345 |
|
|
ack_r <= stb_i;
|
| 346 |
|
|
|
| 347 |
|
|
elsif cti_i = "111" then
|
| 348 |
|
|
if ack_r = '0' then
|
| 349 |
|
|
ack_r <= '1';
|
| 350 |
|
|
else
|
| 351 |
|
|
ack_r <= '0';
|
| 352 |
|
|
end if;
|
| 353 |
|
|
|
| 354 |
|
|
end if;
|
| 355 |
|
|
else
|
| 356 |
|
|
ack_r <= '0';
|
| 357 |
|
|
end if;
|
| 358 |
|
|
|
| 359 |
|
|
end if;
|
| 360 |
|
|
end if;
|
| 361 |
|
|
|
| 362 |
|
|
end process;
|
| 363 |
|
|
|
| 364 |
|
|
|
| 365 |
|
|
ack <= ack_r and stb_i;
|
| 366 |
|
|
ack_o <= ack;
|
| 367 |
|
|
|
| 368 |
|
|
wr_data( 31 downto 24 ) <= dat_i( 31 downto 24 ) when sel_i(3) = '1' else dat_o_tmp( 31 downto 24 );
|
| 369 |
|
|
wr_data( 23 downto 16 ) <= dat_i( 23 downto 16 ) when sel_i(2) = '1' else dat_o_tmp( 23 downto 16 );
|
| 370 |
|
|
wr_data( 15 downto 8 ) <= dat_i( 15 downto 8 ) when sel_i(1) = '1' else dat_o_tmp( 15 downto 8 );
|
| 371 |
|
|
wr_data( 7 downto 0 ) <= dat_i( 7 downto 0 ) when sel_i(0) = '1' else dat_o_tmp( 7 downto 0 );
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
--dat_o_tmp( dat_o_tmp'high downto MEM_SIZE ) <= ( others => '0' );
|
| 375 |
|
|
dat_o_tmp( MEM_SIZE-1 downto 0 ) <= MEM( to_integer( unsigned( addr ) ) );
|
| 376 |
|
|
dat_o <= dat_o_tmp;
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
--
|
| 383 |
|
|
-- this includes a small state machine, the IRQ generation
|
| 384 |
|
|
-- and the memory handling
|
| 385 |
|
|
--
|
| 386 |
|
|
wr_p : process( clk_i, rst_i )
|
| 387 |
|
|
variable MEM_START : integer;
|
| 388 |
|
|
begin
|
| 389 |
|
|
|
| 390 |
|
|
if clk_i'event and clk_i='1' then
|
| 391 |
|
|
if rst_i = '1' then
|
| 392 |
|
|
MEM <= ( others => ( others => '0' ) );
|
| 393 |
|
|
state <= ( st => ST_IDLE,
|
| 394 |
|
|
cnt => ( others => '0' ) );
|
| 395 |
|
|
|
| 396 |
|
|
cordic_start <= '0';
|
| 397 |
|
|
cordic_x_i <= ( others => '0' );
|
| 398 |
|
|
cordic_y_i <= ( others => '0' );
|
| 399 |
|
|
cordic_a_i <= ( others => '0' );
|
| 400 |
|
|
cordic_mode_i <= ( others => '0' );
|
| 401 |
|
|
|
| 402 |
|
|
else
|
| 403 |
|
|
|
| 404 |
|
|
-- default values (get changed below)
|
| 405 |
|
|
cordic_start <= '0';
|
| 406 |
|
|
cordic_x_i <= ( others => '0' );
|
| 407 |
|
|
cordic_y_i <= ( others => '0' );
|
| 408 |
|
|
cordic_a_i <= ( others => '0' );
|
| 409 |
|
|
cordic_mode_i <= ( others => '0' );
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
-- writing to memory
|
| 414 |
|
|
if we_i = '1' and ack = '1' then
|
| 415 |
|
|
MEM( to_integer( unsigned( addr ) ) ) <= wr_data( MEM_SIZE-1 downto 0 );
|
| 416 |
|
|
end if;
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
-- start of all calculations
|
| 422 |
|
|
if MEM( STATUS_REG_I )(0) = '1' and state.st = ST_IDLE then
|
| 423 |
|
|
state.st <= ST_START;
|
| 424 |
|
|
state.cnt <= unsigned( MEM( STATUS_REG_I )( 16+state.cnt'length-1 downto 16 ) )-1;
|
| 425 |
|
|
end if;
|
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
-- start of a single cordic calculation
|
| 429 |
|
|
if state.st = ST_START then
|
| 430 |
|
|
MEM_START := to_integer( state.cnt & "00" ); -- state.cnt * 4
|
| 431 |
|
|
cordic_x_i <= MEM( MEM_START+0 )( cordic_x_i'range );
|
| 432 |
|
|
cordic_y_i <= MEM( MEM_START+1 )( cordic_y_i'range );
|
| 433 |
|
|
cordic_a_i <= MEM( MEM_START+2 )( cordic_a_i'range );
|
| 434 |
|
|
cordic_mode_i <= MEM( MEM_START+3 )( cordic_mode_i'range );
|
| 435 |
|
|
cordic_start <= '1';
|
| 436 |
|
|
|
| 437 |
|
|
state.st <= ST_WAIT;
|
| 438 |
|
|
end if;
|
| 439 |
|
|
|
| 440 |
|
|
|
| 441 |
|
|
-- single cordic calculation is done:
|
| 442 |
|
|
-- save the result and start the next one or
|
| 443 |
|
|
-- go back to idle
|
| 444 |
|
|
if state.st = ST_WAIT and cordic_done = '1' then
|
| 445 |
|
|
MEM_START := to_integer( state.cnt & "00" ); -- state.cnt * 4
|
| 446 |
|
|
MEM( MEM_START+0 ) <= ( others => '0' );
|
| 447 |
|
|
MEM( MEM_START+1 ) <= ( others => '0' );
|
| 448 |
|
|
MEM( MEM_START+2 ) <= ( others => '0' );
|
| 449 |
|
|
MEM( MEM_START+0 )( cordic_x_o'range ) <= cordic_x_o;
|
| 450 |
|
|
MEM( MEM_START+1 )( cordic_y_o'range ) <= cordic_y_o;
|
| 451 |
|
|
MEM( MEM_START+2 )( cordic_a_o'range ) <= cordic_a_o;
|
| 452 |
|
|
|
| 453 |
|
|
|
| 454 |
|
|
if state.cnt = 0 then
|
| 455 |
|
|
|
| 456 |
|
|
-- go back to IDLE
|
| 457 |
|
|
state.st <= ST_IDLE;
|
| 458 |
|
|
|
| 459 |
|
|
-- clear busy flag
|
| 460 |
|
|
MEM( STATUS_REG_I )( 0 ) <= '0';
|
| 461 |
|
|
|
| 462 |
|
|
-- set IRQ flag
|
| 463 |
|
|
MEM( STATUS_REG_I )( 1 ) <= '1';
|
| 464 |
|
|
else
|
| 465 |
|
|
state.st <= ST_START;
|
| 466 |
|
|
state.cnt <= state.cnt-1;
|
| 467 |
|
|
end if;
|
| 468 |
|
|
|
| 469 |
|
|
end if;
|
| 470 |
|
|
|
| 471 |
|
|
end if;
|
| 472 |
|
|
end if;
|
| 473 |
|
|
end process;
|
| 474 |
|
|
|
| 475 |
|
|
-- disable the cordic when there is nothing to do
|
| 476 |
|
|
cordic_en <= '0' when state.st = ST_IDLE else '1';
|
| 477 |
|
|
|
| 478 |
|
|
irq_o <= MEM( STATUS_REG_I )( 1 );
|
| 479 |
|
|
|
| 480 |
|
|
|
| 481 |
|
|
|
| 482 |
|
|
-- the cordic instance
|
| 483 |
|
|
cordic_inst : cordic_iterative_int
|
| 484 |
|
|
generic map (
|
| 485 |
|
|
XY_WIDTH => XY_WIDTH ,
|
| 486 |
|
|
A_WIDTH => A_WIDTH ,
|
| 487 |
|
|
GUARD_BITS => GUARD_BITS,
|
| 488 |
|
|
RM_GAIN => RM_GAIN
|
| 489 |
|
|
)
|
| 490 |
|
|
port map(
|
| 491 |
|
|
clk => clk_i ,
|
| 492 |
|
|
rst => rst_i ,
|
| 493 |
|
|
en => cordic_en ,
|
| 494 |
|
|
start => cordic_start ,
|
| 495 |
|
|
done => cordic_done ,
|
| 496 |
|
|
mode_i => cordic_mode_i ,
|
| 497 |
|
|
x_i => cordic_x_i ,
|
| 498 |
|
|
y_i => cordic_y_i ,
|
| 499 |
|
|
a_i => cordic_a_i ,
|
| 500 |
|
|
x_o => cordic_x_o ,
|
| 501 |
|
|
y_o => cordic_y_o ,
|
| 502 |
|
|
a_o => cordic_a_o
|
| 503 |
|
|
);
|
| 504 |
|
|
|
| 505 |
|
|
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
|
| 510 |
|
|
end architecture IMP;
|
