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[/] [yac/] [trunk/] [test_sys/] [test_sys.yaml] - Blame information for rev 10

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SOCM_SOC
v_socm: 0.1.1
name: YAC Test SOC
description: 'A test system to test the YAC core'
date: 'June 2015'
license: 'LGPL v3'
licensefile: ''
author: 'Christian Haettich'
authormail: 'feddischson@opencores.org'
vccmd: ''
toplevel: yac_test_soc
interfaces:
  :clk_ifc: SOCM_IFC
    name: clk
    dir: 1
    ports:
      :clk_i: SOCM_PORT
        spc_ref: clk
        len: 1
    id: clk,1
  :rst_ifc: SOCM_IFC
    name: rst
    dir: 1
    ports:
      :rst_i: SOCM_PORT
        spc_ref: rst
        len: 1
    id: rst,1
  :jtag_ifc: SOCM_IFC
    name: jtag_tap
    dir: 1
    ports:
      :tck_i: SOCM_PORT
        spc_ref: tck
        len: 1
      :tdi_i: SOCM_PORT
        spc_ref: tdi
        len: 1
      :tdo_o: SOCM_PORT
        spc_ref: tdo
        len: 1
      :debug_rst_i: SOCM_PORT
        spc_ref: rst
        len: 1
      :shift_dr_i: SOCM_PORT
        spc_ref: shift
        len: 1
      :pause_dr_i: SOCM_PORT
        spc_ref: pause
        len: 1
      :update_dr_i: SOCM_PORT
        spc_ref: update
        len: 1
      :capture_dr_i: SOCM_PORT
        spc_ref: capture
        len: 1
      :debug_select_i: SOCM_PORT
        spc_ref: select
        len: 1
    id: jtag_tap,1
  :uart_ifc: SOCM_IFC
    name: uart
    dir: 1
    ports:
      :stx_pad_o: SOCM_PORT
        spc_ref: stx_pad
        len: 1
      :srx_pad_i: SOCM_PORT
        spc_ref: srx_pad
        len: 1
      :rts_pad_o: SOCM_PORT
        spc_ref: rts_pad
        len: 1
      :cts_pad_i: SOCM_PORT
        spc_ref: cts_pad
        len: 1
      :dtr_pad_o: SOCM_PORT
        spc_ref: dtr_pad
        len: 1
      :dsr_pad_i: SOCM_PORT
        spc_ref: dsr_pad
        len: 1
      :ri_pad_i: SOCM_PORT
        spc_ref: ri_pad
        len: 1
      :dcd_pad_i: SOCM_PORT
        spc_ref: dcd_pad
        len: 1
    id: uart,1
functions: {}
inst_parameters: {}
static_parameters: {}
hdlfiles: {}
id: yac_test_soc,v1
cores:
  :cpu: SOCM_INST
    params: {}
    type: or1200,rel2
  :wb_bus: SOCM_INST
    type: wb_connect,1
    params:
      :t0_addr_w: 8
      :t0_addr: 0
      :t1_addr_w: 8
      :t1_addr: 4
      :t28c_addr_w: 4
      :t28_addr: 9
      :t28i_addr_w: 8
      :t2_addr: 151
      :t3_addr: 146
      :t4_addr: 157
      :t5_addr: 144
      :t6_addr: 148
      :t7_addr: 158
      :t8_addr: 159
  :dbg: SOCM_INST
    type: adv_debug_sys,ads_3
    params: {}
  :ram1: SOCM_INST
    type: ram_wb,b3
    params:
      :mem_size_bytes: 10240
      :mem_adr_width: 14
  :ram2: SOCM_INST
    params:
      :mem_size_bytes: 10240
      :mem_adr_width: 15
    type: ram_wb,b3
  :uart: SOCM_INST
    type: uart16550,rel4
    params:
      :uart_data_width: 32
      :uart_addr_width: 32
  :yac: SOCM_INST
    type: yac,v0
    params:
      :WB_ADR_WIDTH: 32
      :N_ENTRIES: 4
      :A_WIDTH: 8
      :XY_WIDTH: 8
      :GUARD_BITS: 2
      :RM_GAIN: 3
cons:
  :con_main_clk:
    :mapping:
    - :yac_test_soc: :clk_ifc
    - :cpu: :clk
      :wb_bus: :clk
      :dbg: :cpu0_dbg_clk
  :con_main_rst:
    :mapping:
    - :yac_test_soc: :rst_ifc
    - :cpu: :rst
      :wb_bus: :rst
  :con_jtag_top:
    :mapping:
    - :yac_test_soc: :jtag_ifc
    - :dbg: :jtag
  :con_uart_top:
    :mapping:
    - :yac_test_soc: :uart_ifc
    - :uart: :uart_ifc
  :con_wb_debug:
    :mapping:
    - :wb_bus: :i3
    - :dbg: :wb_ifc
  :con_data:
    :mapping:
    - :wb_bus: :i4
    - :cpu: :wb_data
  :con_instruction:
    :mapping:
    - :wb_bus: :i5
    - :cpu: :wb_instruction
  :con_ram1:
    :mapping:
    - :wb_bus: :t0
    - :ram1: :wb_ifc
  :con_ram2:
    :mapping:
    - :wb_bus: :t1
    - :ram2: :wb_ifc
  :con_uart:
    :mapping:
    - :wb_bus: :t5
    - :uart: :wb_ifc
  :con_debug:
    :mapping:
    - :dbg: :cpu0_dbg
    - :cpu: :ext_debug
  :con_yac:
    :mapping:
    - :wb_bus: :t8
    - :yac: :wb_ifc
static:
  :or1200,rel2:
    :VCD_DUMP: false
    :VERBOSE: false
    :ASIC: false
    :ASIC_MEM_CHOICE: 0
    :ASIC_NO_DC: true
    :ASIC_NO_IC: true
    :ASIC_NO_DMMU: true
    :ASIC_NO_IMMU: true
    :ASIC_MUL_CHOICE: 0
    :ASIC_IC_CHOICE: 0
    :ASIC_DC_CHOICE: 0
    :FPGA_MEM_CHOICE: 2
    :FPGA_NO_DC: true
    :FPGA_NO_IC: true
    :FPGA_NO_DMMU: true
    :FPGA_NO_IMMU: true
    :FPGA_MUL_CHOICE: 1
    :FPGA_IC_CHOICE: 0
    :FPGA_DC_CHOICE: 0

Line No.	Rev	Author	Line
1	10	feddischso	`SOCM_SOC`
2			`v_socm: 0.1.1`
3			`name: YAC Test SOC`
4			`description: 'A test system to test the YAC core'`
5			`date: 'June 2015'`
6			`license: 'LGPL v3'`
7			`licensefile: ''`
8			`author: 'Christian Haettich'`
9			`authormail: 'feddischson@opencores.org'`
10			`vccmd: ''`
11			`toplevel: yac_test_soc`
12			`interfaces:`
13			`:clk_ifc: SOCM_IFC`
14			`name: clk`
15			`dir: 1`
16			`ports:`
17			`:clk_i: SOCM_PORT`
18			`spc_ref: clk`
19			`len: 1`
20			`id: clk,1`
21			`:rst_ifc: SOCM_IFC`
22			`name: rst`
23			`dir: 1`
24			`ports:`
25			`:rst_i: SOCM_PORT`
26			`spc_ref: rst`
27			`len: 1`
28			`id: rst,1`
29			`:jtag_ifc: SOCM_IFC`
30			`name: jtag_tap`
31			`dir: 1`
32			`ports:`
33			`:tck_i: SOCM_PORT`
34			`spc_ref: tck`
35			`len: 1`
36			`:tdi_i: SOCM_PORT`
37			`spc_ref: tdi`
38			`len: 1`
39			`:tdo_o: SOCM_PORT`
40			`spc_ref: tdo`
41			`len: 1`
42			`:debug_rst_i: SOCM_PORT`
43			`spc_ref: rst`
44			`len: 1`
45			`:shift_dr_i: SOCM_PORT`
46			`spc_ref: shift`
47			`len: 1`
48			`:pause_dr_i: SOCM_PORT`
49			`spc_ref: pause`
50			`len: 1`
51			`:update_dr_i: SOCM_PORT`
52			`spc_ref: update`
53			`len: 1`
54			`:capture_dr_i: SOCM_PORT`
55			`spc_ref: capture`
56			`len: 1`
57			`:debug_select_i: SOCM_PORT`
58			`spc_ref: select`
59			`len: 1`
60			`id: jtag_tap,1`
61			`:uart_ifc: SOCM_IFC`
62			`name: uart`
63			`dir: 1`
64			`ports:`
65			`:stx_pad_o: SOCM_PORT`
66			`spc_ref: stx_pad`
67			`len: 1`
68			`:srx_pad_i: SOCM_PORT`
69			`spc_ref: srx_pad`
70			`len: 1`
71			`:rts_pad_o: SOCM_PORT`
72			`spc_ref: rts_pad`
73			`len: 1`
74			`:cts_pad_i: SOCM_PORT`
75			`spc_ref: cts_pad`
76			`len: 1`
77			`:dtr_pad_o: SOCM_PORT`
78			`spc_ref: dtr_pad`
79			`len: 1`
80			`:dsr_pad_i: SOCM_PORT`
81			`spc_ref: dsr_pad`
82			`len: 1`
83			`:ri_pad_i: SOCM_PORT`
84			`spc_ref: ri_pad`
85			`len: 1`
86			`:dcd_pad_i: SOCM_PORT`
87			`spc_ref: dcd_pad`
88			`len: 1`
89			`id: uart,1`
90			`functions: {}`
91			`inst_parameters: {}`
92			`static_parameters: {}`
93			`hdlfiles: {}`
94			`id: yac_test_soc,v1`
95			`cores:`
96			`:cpu: SOCM_INST`
97			`params: {}`
98			`type: or1200,rel2`
99			`:wb_bus: SOCM_INST`
100			`type: wb_connect,1`
101			`params:`
102			`:t0_addr_w: 8`
103			`:t0_addr: 0`
104			`:t1_addr_w: 8`
105			`:t1_addr: 4`
106			`:t28c_addr_w: 4`
107			`:t28_addr: 9`
108			`:t28i_addr_w: 8`
109			`:t2_addr: 151`
110			`:t3_addr: 146`
111			`:t4_addr: 157`
112			`:t5_addr: 144`
113			`:t6_addr: 148`
114			`:t7_addr: 158`
115			`:t8_addr: 159`
116			`:dbg: SOCM_INST`
117			`type: adv_debug_sys,ads_3`
118			`params: {}`
119			`:ram1: SOCM_INST`
120			`type: ram_wb,b3`
121			`params:`
122			`:mem_size_bytes: 10240`
123			`:mem_adr_width: 14`
124			`:ram2: SOCM_INST`
125			`params:`
126			`:mem_size_bytes: 10240`
127			`:mem_adr_width: 15`
128			`type: ram_wb,b3`
129			`:uart: SOCM_INST`
130			`type: uart16550,rel4`
131			`params:`
132			`:uart_data_width: 32`
133			`:uart_addr_width: 32`
134			`:yac: SOCM_INST`
135			`type: yac,v0`
136			`params:`
137			`:WB_ADR_WIDTH: 32`
138			`:N_ENTRIES: 4`
139			`:A_WIDTH: 8`
140			`:XY_WIDTH: 8`
141			`:GUARD_BITS: 2`
142			`:RM_GAIN: 3`
143			`cons:`
144			`:con_main_clk:`
145			`:mapping:`
146			`- :yac_test_soc: :clk_ifc`
147			`- :cpu: :clk`
148			`:wb_bus: :clk`
149			`:dbg: :cpu0_dbg_clk`
150			`:con_main_rst:`
151			`:mapping:`
152			`- :yac_test_soc: :rst_ifc`
153			`- :cpu: :rst`
154			`:wb_bus: :rst`
155			`:con_jtag_top:`
156			`:mapping:`
157			`- :yac_test_soc: :jtag_ifc`
158			`- :dbg: :jtag`
159			`:con_uart_top:`
160			`:mapping:`
161			`- :yac_test_soc: :uart_ifc`
162			`- :uart: :uart_ifc`
163			`:con_wb_debug:`
164			`:mapping:`
165			`- :wb_bus: :i3`
166			`- :dbg: :wb_ifc`
167			`:con_data:`
168			`:mapping:`
169			`- :wb_bus: :i4`
170			`- :cpu: :wb_data`
171			`:con_instruction:`
172			`:mapping:`
173			`- :wb_bus: :i5`
174			`- :cpu: :wb_instruction`
175			`:con_ram1:`
176			`:mapping:`
177			`- :wb_bus: :t0`
178			`- :ram1: :wb_ifc`
179			`:con_ram2:`
180			`:mapping:`
181			`- :wb_bus: :t1`
182			`- :ram2: :wb_ifc`
183			`:con_uart:`
184			`:mapping:`
185			`- :wb_bus: :t5`
186			`- :uart: :wb_ifc`
187			`:con_debug:`
188			`:mapping:`
189			`- :dbg: :cpu0_dbg`
190			`- :cpu: :ext_debug`
191			`:con_yac:`
192			`:mapping:`
193			`- :wb_bus: :t8`
194			`- :yac: :wb_ifc`
195			`static:`
196			`:or1200,rel2:`
197			`:VCD_DUMP: false`
198			`:VERBOSE: false`
199			`:ASIC: false`
200			`:ASIC_MEM_CHOICE: 0`
201			`:ASIC_NO_DC: true`
202			`:ASIC_NO_IC: true`
203			`:ASIC_NO_DMMU: true`
204			`:ASIC_NO_IMMU: true`
205			`:ASIC_MUL_CHOICE: 0`
206			`:ASIC_IC_CHOICE: 0`
207			`:ASIC_DC_CHOICE: 0`
208			`:FPGA_MEM_CHOICE: 2`
209			`:FPGA_NO_DC: true`
210			`:FPGA_NO_IC: true`
211			`:FPGA_NO_DMMU: true`
212			`:FPGA_NO_IMMU: true`
213			`:FPGA_MUL_CHOICE: 1`
214			`:FPGA_IC_CHOICE: 0`
215			`:FPGA_DC_CHOICE: 0`

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[/] [yac/] [trunk/] [test_sys/] [test_sys.yaml] - Blame information for rev 10