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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<HTML>
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<HEAD>
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<META http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
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<META name="GENERATOR" content="IBM WebSphere Studio Homepage Builder Version 9.0.2.0 for Windows">
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<META http-equiv="Content-Style-Type" content="text/css">
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<TITLE></TITLE>
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</HEAD>
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<BODY>
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<P><B>2.2 Component Design</B><BR>
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<B>2.2.1 ALU</B><BR>
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</P>
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<P>No sequential logic. Very simple. </P>
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<TABLE border="1">
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<TBODY>
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<TR>
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<TH width="28" height="14" align="left">
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<PRE>`include "define.h"
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//Apr.14.2005 Stratix 2 workaround Quartus 4.1/4.2
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//Feb.25.2005 Verilog2001 Style
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//Jan.20.2005 implict event list
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//Jun.14.2004 Initial Version
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//Jul.4.2004 sensibity list bug fix
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//Jul.5.2004 less area version
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module substruct (input [31:0] a,b,
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output [31:0] c);
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assign c=a+~b+1;//NG Quartus 4.1/4.2 a-b Why ? I do not know.
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endmodule
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module alu (input [31:0] a,b,
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output reg [31:0] alu_out,
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input [3:0] alu_func);
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wire [31:0] c;
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parameter [3:0] alu_nop =4'b0000,
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alu_add =4'b0001,
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alu_sub =4'b0010,
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alu_less_than_unsigned =4'b0101, //Jul.5.2004
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alu_less_than_signed =4'b0100, //Jul.5.2004
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alu_OR =4'b0011,
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alu_AND =4'b0110,
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alu_XOR =4'b0111,
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alu_NOR =4'b1000;
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reg [32:0] sum;
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always @* begin //
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case (alu_func)
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alu_nop : alu_out=32'h0000;
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alu_add : alu_out=a+b;
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alu_sub : alu_out=c;//Apr.14.2005 NG a-b Quartus 4.1/4.2
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alu_OR : alu_out=a | b;
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alu_AND : alu_out=a & b;
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alu_XOR : alu_out=a ^ b;
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alu_NOR : alu_out=~(a | b);
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alu_less_than_unsigned : alu_out=a < b;//Jun.29.2004
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alu_less_than_signed: begin
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sum={a[31],a}+~{b[31],b}+33'h0_0000_0001;//Apr.14.2005 1'b1;//Important 33'h0_0000_000 :a-b $signed(a) > $signed(b);
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alu_out={31'h0000_0000,sum[32]};//{31'h0000_0000,sum[32]};
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end
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default : alu_out=32'h0000_0000;
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endcase
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end
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substruct sub(a,b,c);
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endmodule
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</PRE>
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</TH>
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</TR>
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</TBODY>
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</TABLE>
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<P><B>2.2.2 Shifter</B><BR>
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</P>
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<P>No sequential logic. Very simple.</P>
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<TABLE border="1">
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<TBODY>
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<TR>
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<TH width="28" height="14" align="left">
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<PRE>//Jul.5.2004 redushift_oute shift_outritishift_outal path shift_outell
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//Apr.5.2005 always @(*)
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//Apr.8.2005 rewritten using verilog2001 shift_outoding style
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`include "define.h"
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module
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shifter(input [31:0] a,
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output reg [31:0] shift_out,
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input [1:0] shift_func,
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input [4:0] shift_amount);
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localparam [1:0] shift_left=`SHIFT_LEFT,
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shift_right_unsigned=`SHIFT_RIGHT_UNSIGNED,
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shift_right_signed=`SHIFT_RIGHT_SIGNED;
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always @ (*) begin //
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if (!shift_func[1] ) begin
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case (shift_amount[4:0] )
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5'b00000: shift_out=a;
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5'b00001: shift_out={a[30:0],1'b0};
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5'b00010: shift_out={a[29:0],2'b00};
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5'b00011: shift_out={a[28:0],3'b000};
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5'b00100: shift_out={a[27:0],4'b0000};
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5'b00101: shift_out={a[26:0],5'b0_0000};
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5'b00110: shift_out={a[25:0],6'b00_0000};
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5'b00111: shift_out={a[24:0],7'b000_0000};
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5'b01000: shift_out={a[23:0],8'b0000_0000};
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5'b01001: shift_out={a[22:0],9'b0_0000_0000};
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5'b01010: shift_out={a[21:0],10'b00_0000_0000};
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5'b01011: shift_out={a[20:0],11'b000_0000_0000};
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5'b01100: shift_out={a[19:0],12'b0000_0000_0000};
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5'b01101: shift_out={a[18:0],13'b0_0000_0000_0000};
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5'b01110: shift_out={a[17:0],14'b00_0000_0000_0000};
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5'b01111: shift_out={a[16:0],15'b000_0000_0000_0000};
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5'b10000: shift_out={a[15:0],16'b0000_0000_0000_0000};
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5'b10001: shift_out={a[14:0],16'b0000_0000_0000_0000,1'b0};
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5'b10010: shift_out={a[13:0],16'b0000_0000_0000_0000,2'b00};
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5'b10011: shift_out={a[12:0],16'b0000_0000_0000_0000,3'b000};
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5'b10100: shift_out={a[11:0],16'b0000_0000_0000_0000,4'b0000};
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5'b10101: shift_out={a[10:0],16'b0000_0000_0000_0000,5'b0_0000};
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5'b10110: shift_out={a[9:0],16'b0000_0000_0000_0000,6'b00_0000};
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5'b10111: shift_out={a[8:0],16'b0000_0000_0000_0000,7'b000_0000};
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5'b11000: shift_out={a[7:0],16'b0000_0000_0000_0000,8'b0000_0000};
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5'b11001: shift_out={a[6:0],16'b0000_0000_0000_0000,9'b0_0000_0000};
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5'b11010: shift_out={a[5:0],16'b0000_0000_0000_0000,10'b00_0000_0000};
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5'b11011: shift_out={a[4:0],16'b0000_0000_0000_0000,11'b000_0000_0000};
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5'b11100: shift_out={a[3:0],16'b0000_0000_0000_0000,12'b0000_0000_0000};
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5'b11101: shift_out={a[2:0],16'b0000_0000_0000_0000,13'b0_0000_0000_0000};
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5'b11110: shift_out={a[1:0],16'b0000_0000_0000_0000,14'b00_0000_0000_0000};
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5'b11111: shift_out={a[0],16'b0000_0000_0000_0000,15'b000_0000_0000_0000};
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endcase
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end else if (shift_func==`SHIFT_RIGHT_UNSIGNED) begin
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case (shift_amount)
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5'b00000: shift_out=a;
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5'b00001: shift_out={1'b0,a[31:1]};
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5'b00010: shift_out={2'b00,a[31:2]};
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5'b00011: shift_out={3'b000,a[31:3]};
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5'b00100: shift_out={4'b0000,a[31:4]};
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5'b00101: shift_out={5'b0_0000,a[31:5]};
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5'b00110: shift_out={6'b00_0000,a[31:6]};
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5'b00111: shift_out={7'b000_0000,a[31:7]};
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5'b01000: shift_out={8'b0000_0000,a[31:8]};
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5'b01001: shift_out={9'b0_0000_0000,a[31:9]};
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5'b01010: shift_out={10'b00_0000_0000,a[31:10]};
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5'b01011: shift_out={11'b000_0000_0000,a[31:11]};
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5'b01100: shift_out={12'b0000_0000_0000,a[31:12]};
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5'b01101: shift_out={13'b0_0000_0000_0000,a[31:13]};
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5'b01110: shift_out={14'b00_0000_0000_0000,a[31:14]};
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5'b01111: shift_out={15'b000_0000_0000_0000,a[31:15]};
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5'b10000: shift_out={16'b0000_0000_0000_0000,a[31:16]};
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5'b10001: shift_out={16'b0000_0000_0000_0000,1'b0,a[31:17]};
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5'b10010: shift_out={16'b0000_0000_0000_0000,2'b00,a[31:18]};
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5'b10011: shift_out={16'b0000_0000_0000_0000,3'b000,a[31:19]};
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5'b10100: shift_out={16'b0000_0000_0000_0000,4'b0000,a[31:20]};
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5'b10101: shift_out={16'b0000_0000_0000_0000,5'b0_0000,a[31:21]};
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5'b10110: shift_out={16'b0000_0000_0000_0000,6'b00_0000,a[31:22]};
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5'b10111: shift_out={16'b0000_0000_0000_0000,7'b000_0000,a[31:23]};
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5'b11000: shift_out={16'b0000_0000_0000_0000,8'b0000_0000,a[31:24]};
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5'b11001: shift_out={16'b0000_0000_0000_0000,9'b0_0000_0000,a[31:25]};
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5'b11010: shift_out={16'b0000_0000_0000_0000,10'b00_0000_0000,a[31:26]};
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5'b11011: shift_out={16'b0000_0000_0000_0000,11'b000_0000_0000,a[31:27]};
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5'b11100: shift_out={16'b0000_0000_0000_0000,12'b0000_0000_0000,a[31:28]};
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5'b11101: shift_out={16'b0000_0000_0000_0000,13'b0_0000_0000_0000,a[31:29]};
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5'b11110: shift_out={16'b0000_0000_0000_0000,14'b00_0000_0000_0000,a[31:30]};
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5'b11111: shift_out={16'b0000_0000_0000_0000,15'b000_0000_0000_0000,a[31:31]};
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endcase
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end else begin// SHIFT_RIGHT_SIGNED
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case (shift_amount)
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5'b00000: shift_out=a;
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5'b00001: shift_out={a[31],a[31:1]};
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5'b00010: shift_out={{2{a[31]}},a[31:2]};
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5'b00011: shift_out={{3{a[31]}},a[31:3]};
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5'b00100: shift_out={{4{a[31]}},a[31:4]};
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5'b00101: shift_out={{5{a[31]}},a[31:5]};
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5'b00110: shift_out={{6{a[31]}},a[31:6]};
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5'b00111: shift_out={{7{a[31]}},a[31:7]};
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5'b01000: shift_out={{8{a[31]}},a[31:8]};
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5'b01001: shift_out={{9{a[31]}},a[31:9]};
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5'b01010: shift_out={{10{a[31]}},a[31:10]};
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5'b01011: shift_out={{11{a[31]}},a[31:11]};
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5'b01100: shift_out={{12{a[31]}},a[31:12]};
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5'b01101: shift_out={{13{a[31]}},a[31:13]};
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5'b01110: shift_out={{14{a[31]}},a[31:14]};
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5'b01111: shift_out={{15{a[31]}},a[31:15]};
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5'b10000: shift_out={{16{a[31]}},a[31:16]};
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5'b10001: shift_out={{17{a[31]}},a[31:17]};
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5'b10010: shift_out={{18{a[31]}},a[31:18]};
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5'b10011: shift_out={{19{a[31]}},a[31:19]};
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5'b10100: shift_out={{20{a[31]}},a[31:20]};
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5'b10101: shift_out={{21{a[31]}},a[31:21]};
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5'b10110: shift_out={{22{a[31]}},a[31:22]};
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5'b10111: shift_out={{23{a[31]}},a[31:23]};
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5'b11000: shift_out={{24{a[31]}},a[31:24]};
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5'b11001: shift_out={{25{a[31]}},a[31:25]};
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5'b11010: shift_out={{26{a[31]}},a[31:26]};
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5'b11011: shift_out={{27{a[31]}},a[31:27]};
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5'b11100: shift_out={{28{a[31]}},a[31:28]};
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5'b11101: shift_out={{29{a[31]}},a[31:29]};
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5'b11110: shift_out={{30{a[31]}},a[31:30]};
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5'b11111: shift_out={{31{a[31]}},a[31:31]};
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endcase
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end
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end
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endmodule</PRE>
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</TH>
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</TR>
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</TBODY>
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</TABLE>
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<P><B>2.2.3 mul_div_module</B></P>
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<P> Multiplier:</P>
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<UL>
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<LI>singed/unsigned 32bits input
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<LI>singed/unsigned 64 bits output
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<LI>scalable 2-32clocks processing time
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</UL>
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<P>Divider</P>
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<UL>
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<LI>signed/unsigned 32bits input
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<LI>signed/unsigned 32bits quotient and remainder
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<LI>fixed 32 clocks processing time
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</UL>
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<P>Starts calculation by "mul_div_enable" signal, "stop_state"
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signal becomes high during calculation.<BR>
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</P>
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<TABLE border="1">
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<TBODY>
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<TR>
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<TH width="28" height="14" align="left">
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<PRE>//Jun.2.2004
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//Jun.27.2004
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//Jun.28.2004
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//Jun.30.2004 mulfunc output bug fix
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// still 16x16 sign extension
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//Jul.2.2004 mul 32x32=>64bit w/ w/o sign
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//Jul.2.2004 address MUL_WIDTH==1
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//Jul.4.2004 input critical path : => add carry_ff;
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//Jul.5.2004 :=> less fanout
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//Jul.13.2004 signed mul bug fix
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//Jul.15.2004 32/32 div
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//Jul.16.2004 diet
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//Jul.17.2004 add `ifdef less path delay for interface port
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//Apr.7.2005 ADDRESS to XILINX Specific problem
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//Apr.14.2005 Add Stratix2
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// mul/div module
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// a[31:0] /b[31:0] =>
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// mul_div_out[15:0] <=a/b
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// mul_div_out[31:16] <=a%b
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// No detection of overflow
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// Algorithm
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// answer_reg = (answer_reg << 1);
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// multout_reg<={sum,a_reg[31]};
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// if (multout_reg >= b_reg) {
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// answer_reg += 1;
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// multout_reg -= b_reg;
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// }
|
271 |
|
|
// a_reg <= a_reg << 1;
|
272 |
|
|
`include "define.h"
|
273 |
|
|
module mul_div(clock,sync_reset,a,b,mul_div_out,mul_div_sign,mul_div_word,mul_div_mode,state,stop_state,mul_div_enable,lohi);
|
274 |
|
|
`ifdef RAM4K
|
275 |
|
|
|
276 |
|
|
`ifdef XILINX
|
277 |
|
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
278 |
|
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
279 |
|
|
// XILINX fails using ISE7.1 if MUL_WIDTH==1,2
|
280 |
|
|
// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
|
281 |
|
|
// if MULWIDTH==2 synthesis fails;
|
282 |
|
|
// MUL_WIDTH==16 shows good.
|
283 |
|
|
|
284 |
|
|
`else
|
285 |
|
|
parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
286 |
|
|
parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
|
287 |
|
|
`endif
|
288 |
|
|
`else
|
289 |
|
|
`ifdef XILINX
|
290 |
|
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
291 |
|
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
292 |
|
|
// XILINX fails using ISE7.1 if MUL_WIDTH==1,2
|
293 |
|
|
// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
|
294 |
|
|
// if MULWIDTH==2 synthesis fails;
|
295 |
|
|
// MUL_WIDTH==16 shows good.
|
296 |
|
|
|
297 |
|
|
`else
|
298 |
|
|
`ifdef Stratix2
|
299 |
|
|
parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
300 |
|
|
parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
|
301 |
|
|
`else
|
302 |
|
|
parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
|
303 |
|
|
parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
|
304 |
|
|
`endif
|
305 |
|
|
`endif
|
306 |
|
|
`endif
|
307 |
|
|
input clock,sync_reset;
|
308 |
|
|
input [31:0] a,b;
|
309 |
|
|
input [7:0] state;
|
310 |
|
|
input lohi;
|
311 |
|
|
input mul_div_enable,mul_div_sign,mul_div_word,mul_div_mode;
|
312 |
|
|
output stop_state;
|
313 |
|
|
output [31:0] mul_div_out;
|
314 |
|
|
|
315 |
|
|
reg [31:0] a_reg;
|
316 |
|
|
reg [31:0] b_reg;
|
317 |
|
|
reg [31:0] answer_reg;
|
318 |
|
|
|
319 |
|
|
reg stop_state_reg;// For state control
|
320 |
|
|
reg [5:0] counter;
|
321 |
|
|
reg mul_div_sign_ff,mul_div_mode_ff;
|
322 |
|
|
reg a31_latch,b31_latch;
|
323 |
|
|
reg breg31;
|
324 |
|
|
//mult64
|
325 |
|
|
wire [63:0] ab62={1'b0,a_reg[31]*breg31,62'h0};//Jul.5.2004
|
326 |
|
|
wire [63:0] shift_a31=mul_div_sign_ff ? ~{2'b0,a_reg[30:0],31'h0}+1'b1: {2'b0,a_reg[30:0],31'h0} ;//Jul.13.2004 Jul.2.2004
|
327 |
|
|
wire [63:0] shift_b31=mul_div_sign_ff ? ~{2'b0,b_reg[30:0],31'h0}+1'b1: {2'b0,b_reg[30:0],31'h0};//Jul.13.2004 Jul.2.2004
|
328 |
|
|
|
329 |
|
|
wire [30:0] init_lower =breg31*shift_a31[30:0] +a_reg[31]*shift_b31[30:0]+ab62[30:0];//Jul.5.2004
|
330 |
|
|
wire [63:31] init_upper=breg31*shift_a31[63:31]+a_reg[31]*shift_b31[63:31]+ab62[63:31];//+carry;Jul.5.2004
|
331 |
|
|
wire [63:0] init_val={init_upper,init_lower};
|
332 |
|
|
wire [MUL_WIDTH+30 :0] mult32x4out_temp=a_reg[30:0]*b_reg[MUL_WIDTH-1:0];//Jul.5.2004
|
333 |
|
|
wire [MUL_WIDTH+31 :0] mult32x4out={1'b0,mult32x4out_temp};
|
334 |
|
|
reg [63:0] mult64_reg;
|
335 |
|
|
reg [31:0] multout_reg;
|
336 |
|
|
wire [63:0] mult64_out;
|
337 |
|
|
wire [63:0] mult64=a_reg* b_reg;
|
338 |
|
|
reg [MUL_WIDTH+31-1+1 :0] mult32x4out_reg;
|
339 |
|
|
|
340 |
|
|
|
341 |
|
|
wire finish_operation;
|
342 |
|
|
wire pre_stop;
|
343 |
|
|
wire [32:0] sum;
|
344 |
|
|
wire [31:0] answer_inc;
|
345 |
|
|
wire [31:0] aminus=-a;
|
346 |
|
|
wire [31:0] div_out,div_out_tmp;
|
347 |
|
|
|
348 |
|
|
|
349 |
|
|
wire mul_div_mode_w;
|
350 |
|
|
reg mul_state_reg;
|
351 |
|
|
reg div_msb_ff;
|
352 |
|
|
|
353 |
|
|
assign mul_div_mode_w=pre_stop ? mul_div_mode: mul_div_mode_ff;
|
354 |
|
|
|
355 |
|
|
`ifdef RAM4K
|
356 |
|
|
//less area
|
357 |
|
|
|
358 |
|
|
assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : div_out :
|
359 |
|
|
!mul_div_mode_ff ? mult64_out[63:32] : div_out;//Jul.16.2004
|
360 |
|
|
|
361 |
|
|
assign div_out_tmp=!lohi ? answer_reg: {div_msb_ff,multout_reg[31:1]};
|
362 |
|
|
assign div_out= (!lohi && (a31_latch ^ b31_latch) && mul_div_sign_ff) ||
|
363 |
|
|
(lohi && mul_div_sign_ff && a31_latch) ? ~div_out_tmp+1'b1 : div_out_tmp;
|
364 |
|
|
|
365 |
|
|
`else
|
366 |
|
|
|
367 |
|
|
// faster
|
368 |
|
|
reg [31:0] div_out_multout_latch,answer_reg_latch;//
|
369 |
|
|
|
370 |
|
|
assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : answer_reg_latch :
|
371 |
|
|
!mul_div_mode_ff ? mult64_out[63:32] : div_out_multout_latch;//Jul.16.2004
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
|
375 |
|
|
always @(posedge clock) begin
|
376 |
|
|
if ( (a31_latch ^ b31_latch) && mul_div_sign_ff)
|
377 |
|
|
answer_reg_latch<=~answer_reg+1'b1;
|
378 |
|
|
else answer_reg_latch<= answer_reg;
|
379 |
|
|
|
380 |
|
|
if ( mul_div_sign_ff && a31_latch)
|
381 |
|
|
div_out_multout_latch<=~{div_msb_ff,multout_reg[31:1]}+1'b1;
|
382 |
|
|
else div_out_multout_latch<={div_msb_ff,multout_reg[31:1]};
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
end
|
386 |
|
|
|
387 |
|
|
|
388 |
|
|
`endif
|
389 |
|
|
|
390 |
|
|
//mul64
|
391 |
|
|
//mul_state
|
392 |
|
|
always @(posedge clock) begin
|
393 |
|
|
breg31<=b[31];
|
394 |
|
|
end
|
395 |
|
|
always @(posedge clock) begin
|
396 |
|
|
mult32x4out_reg<=mult32x4out;
|
397 |
|
|
end
|
398 |
|
|
|
399 |
|
|
//Jul.16.2004
|
400 |
|
|
always @(posedge clock) begin
|
401 |
|
|
if (sync_reset) mul_state_reg<=0;
|
402 |
|
|
else if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) mul_state_reg<=1;
|
403 |
|
|
else if (finish_operation) mul_state_reg<=0;
|
404 |
|
|
end
|
405 |
|
|
|
406 |
|
|
//mult64_reg multout_reg
|
407 |
|
|
always @(posedge clock) begin
|
408 |
|
|
if (mul_state_reg && counter==0 )begin
|
409 |
|
|
mult64_reg<=init_val;//Jul.13.2004 Jul.5.2004 Jul.4.2004
|
410 |
|
|
end
|
411 |
|
|
else
|
412 |
|
|
if (mul_state_reg) begin
|
413 |
|
|
{mult64_reg,multout_reg[31:31-MUL_WIDTH+1]}<={{MUL_WIDTH {1'b0}},mult64_reg+mult32x4out_reg};
|
414 |
|
|
multout_reg[31-MUL_WIDTH:0] <=multout_reg[31:MUL_WIDTH];
|
415 |
|
|
|
416 |
|
|
//Division
|
417 |
|
|
end else if (pre_stop && counter==0 ) multout_reg<=0; //First
|
418 |
|
|
else if (mul_div_mode_ff && stop_state_reg ) begin
|
419 |
|
|
if (sum[32]==1'b0) begin //if (a_reg >=b_reg)
|
420 |
|
|
if (finish_operation) div_msb_ff<=sum[31];
|
421 |
|
|
multout_reg<={sum,a_reg[31]};
|
422 |
|
|
end else begin
|
423 |
|
|
if (finish_operation) div_msb_ff<=multout_reg[31];
|
424 |
|
|
multout_reg[0]<=a_reg[31];
|
425 |
|
|
multout_reg[31:1] <=multout_reg[30:0];
|
426 |
|
|
end
|
427 |
|
|
end
|
428 |
|
|
end
|
429 |
|
|
|
430 |
|
|
assign mult64_out={mult64_reg[31:0],multout_reg[31:0]};
|
431 |
|
|
//input FFs
|
432 |
|
|
|
433 |
|
|
always @(posedge clock) begin
|
434 |
|
|
if (sync_reset) begin
|
435 |
|
|
mul_div_sign_ff<=0;
|
436 |
|
|
mul_div_mode_ff<=0;
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
end else if (pre_stop) begin
|
440 |
|
|
mul_div_sign_ff<=mul_div_sign;
|
441 |
|
|
a31_latch<=a[31];
|
442 |
|
|
b31_latch<=b[31];
|
443 |
|
|
mul_div_mode_ff<=mul_div_mode;
|
444 |
|
|
end
|
445 |
|
|
end
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
//state_machine
|
450 |
|
|
assign pre_stop=mul_div_enable ;
|
451 |
|
|
assign finish_operation=(mul_div_mode_ff && counter==32) || (mul_state_reg && counter==MUL_STATE_MSB) ;//Jul.2.2004
|
452 |
|
|
|
453 |
|
|
|
454 |
|
|
always @(posedge clock) begin
|
455 |
|
|
if (sync_reset) stop_state_reg <=0;
|
456 |
|
|
else if (pre_stop && !stop_state_reg ) stop_state_reg<=1;
|
457 |
|
|
else if (stop_state_reg && finish_operation) stop_state_reg<=0;
|
458 |
|
|
end
|
459 |
|
|
|
460 |
|
|
assign stop_state=stop_state_reg;
|
461 |
|
|
|
462 |
|
|
always @(posedge clock) begin
|
463 |
|
|
if (sync_reset) counter <=0;
|
464 |
|
|
else if (!stop_state_reg) counter <=0;
|
465 |
|
|
else if (stop_state_reg ) counter <=counter+1;
|
466 |
|
|
end
|
467 |
|
|
|
468 |
|
|
//a_reg
|
469 |
|
|
always @(posedge clock) begin
|
470 |
|
|
if(mul_div_mode_w==`MUL_DIV_MUL_SEL && pre_stop) a_reg <=a;//
|
471 |
|
|
else if(mul_div_mode_w !=`MUL_DIV_MUL_SEL )begin//
|
472 |
|
|
if (!stop_state_reg && !pre_stop) a_reg <=a_reg;//
|
473 |
|
|
else if (pre_stop && counter==0 ) begin //
|
474 |
|
|
if (mul_div_sign) begin//
|
475 |
|
|
if (a[31]) a_reg <=aminus;//
|
476 |
|
|
else a_reg <=a;
|
477 |
|
|
end else a_reg <=a;//
|
478 |
|
|
end else begin//div
|
479 |
|
|
a_reg <={a_reg[30:0],1'b0};// a_reg <<=1;
|
480 |
|
|
end
|
481 |
|
|
|
482 |
|
|
end
|
483 |
|
|
end
|
484 |
|
|
|
485 |
|
|
//b_reg
|
486 |
|
|
always @(posedge clock) begin
|
487 |
|
|
if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) b_reg<={1'b0,b[30:0]};
|
488 |
|
|
else if ( mul_state_reg) b_reg<=b_reg[31:MUL_WIDTH];
|
489 |
|
|
else if( mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
|
490 |
|
|
if (!stop_state_reg && !pre_stop ) b_reg <=b_reg;//
|
491 |
|
|
else if (pre_stop && counter==0 ) begin //
|
492 |
|
|
if (mul_div_sign) begin//
|
493 |
|
|
if ( b[31]) b_reg <=-b[31:0];//
|
494 |
|
|
else b_reg <=b[31:0];//
|
495 |
|
|
end else begin
|
496 |
|
|
b_reg <=b[31:0];//
|
497 |
|
|
end
|
498 |
|
|
end else begin//div
|
499 |
|
|
b_reg <=b_reg;//;
|
500 |
|
|
end
|
501 |
|
|
end
|
502 |
|
|
end
|
503 |
|
|
|
504 |
|
|
//answer_reg
|
505 |
|
|
always @(posedge clock) begin
|
506 |
|
|
|
507 |
|
|
if (mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
|
508 |
|
|
if (!stop_state_reg && !pre_stop) answer_reg <=answer_reg;//
|
509 |
|
|
else if (pre_stop && counter==0 ) answer_reg<=0; //
|
510 |
|
|
else begin//div
|
511 |
|
|
if ( !sum[32] ) begin//
|
512 |
|
|
if (finish_operation) answer_reg <=answer_inc;
|
513 |
|
|
else answer_reg <={answer_inc[30:0],1'b0}; //Jun.7.2004 a_reg -= b_reg
|
514 |
|
|
end else begin
|
515 |
|
|
if (finish_operation ) begin
|
516 |
|
|
answer_reg <=answer_reg;
|
517 |
|
|
end else answer_reg <={answer_reg[30:0],1'b0}; // answer_reg <<=1;
|
518 |
|
|
end
|
519 |
|
|
end
|
520 |
|
|
end
|
521 |
|
|
end
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
assign sum={1'b0,multout_reg}+~{1'b0,b_reg}+1'b1;//
|
525 |
|
|
assign answer_inc=answer_reg+1'b1;//Jun.7.2004
|
526 |
|
|
|
527 |
|
|
endmodule
|
528 |
|
|
</PRE>
|
529 |
|
|
</TH>
|
530 |
|
|
</TR>
|
531 |
|
|
</TBODY>
|
532 |
|
|
</TABLE>
|
533 |
|
|
<P><B>2.2.4 RAM_Module</B></P>
|
534 |
|
|
<P>In this module,8bitsx4 dual port RAM is necessary for both Altera and Xilinx.<BR>
|
535 |
|
|
Dual Port makes it possible to access independently for program and data.</P>
|
536 |
|
|
<TABLE border="1">
|
537 |
|
|
<TBODY>
|
538 |
|
|
<TR>
|
539 |
|
|
<TH width="28" height="14" align="left">
|
540 |
|
|
<PRE>//Jun.29.2004 w0,w1,w2,w3 bug fix
|
541 |
|
|
//Jun.30.2004 endian bug fix
|
542 |
|
|
//Jul.1.2004 endian bug fix
|
543 |
|
|
//Apr.2.2005 Change Port Address
|
544 |
|
|
`include "define.h"
|
545 |
|
|
`define COMB_MOUT
|
546 |
|
|
`define COMB_MOUT_IR
|
547 |
|
|
|
548 |
|
|
|
549 |
|
|
`define NO_SIGNED_MOUT
|
550 |
|
|
module ram_module_altera(clock,sync_reset,IR,MOUT,Paddr,Daddr,wren,datain,access_mode,M_signed,
|
551 |
|
|
uread_port,write_busy);
|
552 |
|
|
input clock,sync_reset;
|
553 |
|
|
input wren;
|
554 |
|
|
input [31:0] datain;
|
555 |
|
|
input M_signed;
|
556 |
|
|
input [7:0] uread_port;
|
557 |
|
|
input write_busy;//Apr.2.2005
|
558 |
|
|
`ifdef RAM32K
|
559 |
|
|
|
560 |
|
|
input [14:0] Paddr,Daddr;//4KB address
|
561 |
|
|
reg [14:0] DaddrD;
|
562 |
|
|
|
563 |
|
|
|
564 |
|
|
`endif
|
565 |
|
|
|
566 |
|
|
`ifdef RAM16K
|
567 |
|
|
|
568 |
|
|
input [13:0] Paddr,Daddr;//4KB address
|
569 |
|
|
reg [13:0] DaddrD;
|
570 |
|
|
|
571 |
|
|
|
572 |
|
|
`endif
|
573 |
|
|
|
574 |
|
|
`ifdef RAM4K
|
575 |
|
|
input [11:0] Paddr,Daddr;//4KB address
|
576 |
|
|
reg [11:0] DaddrD;
|
577 |
|
|
|
578 |
|
|
`endif
|
579 |
|
|
|
580 |
|
|
output [31:0] IR;//Instrcuntion Register
|
581 |
|
|
output [31:0] MOUT;//data out
|
582 |
|
|
input [1:0] access_mode;
|
583 |
|
|
|
584 |
|
|
reg [31:0] IR;
|
585 |
|
|
reg [31:0] MOUT;
|
586 |
|
|
reg [1:0] access_modeD;
|
587 |
|
|
|
588 |
|
|
wire [7:0] a0,a1,a2,a3;
|
589 |
|
|
wire [7:0] b0,b1,b2,b3;
|
590 |
|
|
wire [7:0] dport0,dport1,dport2,dport3;
|
591 |
|
|
wire w0,w1,w2,w3;
|
592 |
|
|
wire uread_port_access=`UART_PORT_ADDRESS==Daddr;
|
593 |
|
|
|
594 |
|
|
reg uread_access_reg;
|
595 |
|
|
|
596 |
|
|
assign dport0=datain[7:0] ;
|
597 |
|
|
assign dport1=access_mode !=`BYTE_ACCESS ? datain[15:8] : datain[7:0];
|
598 |
|
|
assign dport2=access_mode==`LONG_ACCESS ? datain[23:16] : datain[7:0];
|
599 |
|
|
assign dport3=access_mode==`LONG_ACCESS ? datain[31:24] :
|
600 |
|
|
access_mode==`WORD_ACCESS ? datain[15:8] : datain[7:0];
|
601 |
|
|
|
602 |
|
|
|
603 |
|
|
`ifdef RAM32K
|
604 |
|
|
ram8192x8_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
|
605 |
|
|
.data_b(dport0),.address_b(Daddr[14:2]),.wren_b(w0),.clock(clock),
|
606 |
|
|
.q_a(a0),.q_b(b0));
|
607 |
|
|
|
608 |
|
|
ram8192x8_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
|
609 |
|
|
.data_b(dport1),.address_b(Daddr[14:2]),.wren_b(w1),.clock(clock),
|
610 |
|
|
.q_a(a1),.q_b(b1));
|
611 |
|
|
|
612 |
|
|
ram8192x8_1 ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
|
613 |
|
|
.data_b(dport2),.address_b(Daddr[14:2]),.wren_b(w2),.clock(clock),
|
614 |
|
|
.q_a(a2),.q_b(b2));
|
615 |
|
|
|
616 |
|
|
ram8192x8_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
|
617 |
|
|
.data_b(dport3),.address_b(Daddr[14:2]),.wren_b(w3),.clock(clock),
|
618 |
|
|
.q_a(a3),.q_b(b3));
|
619 |
|
|
|
620 |
|
|
`endif
|
621 |
|
|
`ifdef RAM16K
|
622 |
|
|
`ifdef ALTERA
|
623 |
|
|
ram4096x8_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
|
624 |
|
|
.data_b(dport0),.address_b(Daddr[13:2]),.wren_b(w0),.clock(clock),
|
625 |
|
|
.q_a(a0),.q_b(b0));
|
626 |
|
|
|
627 |
|
|
ram4096x8_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
|
628 |
|
|
.data_b(dport1),.address_b(Daddr[13:2]),.wren_b(w1),.clock(clock),
|
629 |
|
|
.q_a(a1),.q_b(b1));
|
630 |
|
|
|
631 |
|
|
ram4092x8_1 ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
|
632 |
|
|
.data_b(dport2),.address_b(Daddr[13:2]),.wren_b(w2),.clock(clock),
|
633 |
|
|
.q_a(a2),.q_b(b2));
|
634 |
|
|
|
635 |
|
|
ram4092x8_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
|
636 |
|
|
.data_b(dport3),.address_b(Daddr[13:2]),.wren_b(w3),.clock(clock),
|
637 |
|
|
.q_a(a3),.q_b(b3));
|
638 |
|
|
`else
|
639 |
|
|
ram1k3 ram0(.addra(Paddr[13:2]),
|
640 |
|
|
.dinb(dport0),.addrb(Daddr[13:2]),.web(w0),.clka(clock),.clkb(clock),
|
641 |
|
|
.douta(a0),.doutb(b0));
|
642 |
|
|
ram1k2 ram1(.addra(Paddr[13:2]),
|
643 |
|
|
.dinb(dport1),.addrb(Daddr[13:2]),.web(w1),.clka(clock),.clkb(clock),
|
644 |
|
|
.douta(a1),.doutb(b1));
|
645 |
|
|
ram1k1 ram2(.addra(Paddr[13:2]),
|
646 |
|
|
.dinb(dport2),.addrb(Daddr[13:2]),.web(w2),.clka(clock),.clkb(clock),
|
647 |
|
|
.douta(a2),.doutb(b2));
|
648 |
|
|
ram1k0 ram3(.addra(Paddr[13:2]),
|
649 |
|
|
.dinb(dport3),.addrb(Daddr[13:2]),.web(w3),.clka(clock),.clkb(clock),
|
650 |
|
|
.douta(a3),.doutb(b3));
|
651 |
|
|
`endif
|
652 |
|
|
`endif
|
653 |
|
|
|
654 |
|
|
`ifdef RAM4K
|
655 |
|
|
ram_1k_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
|
656 |
|
|
.data_b(dport0),.address_b(Daddr[11:2]),.wren_b(w0),.clock(clock),
|
657 |
|
|
.q_a(a0),.q_b(b0));
|
658 |
|
|
|
659 |
|
|
ram_1k_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
|
660 |
|
|
.data_b(dport1),.address_b(Daddr[11:2]),.wren_b(w1),.clock(clock),
|
661 |
|
|
.q_a(a1),.q_b(b1));
|
662 |
|
|
|
663 |
|
|
ram_1k_1 ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
|
664 |
|
|
.data_b(dport2),.address_b(Daddr[11:2]),.wren_b(w2),.clock(clock),
|
665 |
|
|
.q_a(a2),.q_b(b2));
|
666 |
|
|
|
667 |
|
|
ram_1k_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
|
668 |
|
|
.data_b(dport3),.address_b(Daddr[11:2]),.wren_b(w3),.clock(clock),
|
669 |
|
|
.q_a(a3),.q_b(b3));
|
670 |
|
|
|
671 |
|
|
`endif
|
672 |
|
|
|
673 |
|
|
wire temp=( access_mode==`BYTE_ACCESS && Daddr[1:0]==2'b00);
|
674 |
|
|
|
675 |
|
|
|
676 |
|
|
assign w3= wren &&
|
677 |
|
|
( access_mode==`LONG_ACCESS ||
|
678 |
|
|
( access_mode==`WORD_ACCESS && !Daddr[1] ) ||
|
679 |
|
|
( access_mode==`BYTE_ACCESS && Daddr[1:0]==2'b00));
|
680 |
|
|
assign w2= wren &&
|
681 |
|
|
( access_mode==`LONG_ACCESS ||
|
682 |
|
|
( access_mode==`WORD_ACCESS && !Daddr[1]) ||
|
683 |
|
|
( Daddr[1:0]==2'b01));
|
684 |
|
|
assign w1= wren &&
|
685 |
|
|
( access_mode==`LONG_ACCESS ||
|
686 |
|
|
( access_mode==`WORD_ACCESS && Daddr[1]) ||
|
687 |
|
|
( Daddr[1:0]==2'b10));
|
688 |
|
|
assign w0= wren &&
|
689 |
|
|
( access_mode==`LONG_ACCESS ||
|
690 |
|
|
( access_mode==`WORD_ACCESS && Daddr[1]) ||
|
691 |
|
|
( Daddr[1:0]==2'b11));
|
692 |
|
|
|
693 |
|
|
|
694 |
|
|
//IR
|
695 |
|
|
|
696 |
|
|
`ifdef COMB_MOUT_IR
|
697 |
|
|
|
698 |
|
|
always @(*) IR={a3,a2,a1,a0};
|
699 |
|
|
|
700 |
|
|
|
701 |
|
|
`else
|
702 |
|
|
always @(posedge clock) begin
|
703 |
|
|
if (sync_reset) IR <=0;
|
704 |
|
|
else IR <={a3,a2,a1,a0};
|
705 |
|
|
|
706 |
|
|
end
|
707 |
|
|
`endif
|
708 |
|
|
|
709 |
|
|
always @(posedge clock) begin
|
710 |
|
|
if (access_modeD==`LONG_ACCESS) begin
|
711 |
|
|
if(uread_access_reg) begin
|
712 |
|
|
MOUT <={23'h00_0000,write_busy,uread_port};
|
713 |
|
|
end else
|
714 |
|
|
MOUT <={b3,b2,b1,b0};
|
715 |
|
|
|
716 |
|
|
end else if (access_modeD==`WORD_ACCESS) begin
|
717 |
|
|
case (DaddrD[1])
|
718 |
|
|
1'b0: if(M_signed) MOUT <={{16{b3[7]}},b3,b2};//Jul.1.2004
|
719 |
|
|
else MOUT <={16'h0000,b3,b2};
|
720 |
|
|
1'b1: if(M_signed) MOUT <={{16{b1[7]}},b1,b0};//Jul.1.2004
|
721 |
|
|
else MOUT <={16'h0000,b1,b0};
|
722 |
|
|
endcase
|
723 |
|
|
end else begin//BYTE ACCESSS
|
724 |
|
|
case (DaddrD[1:0])
|
725 |
|
|
2'b00:if(M_signed) MOUT <={{24{b3[7]}},b3};
|
726 |
|
|
else MOUT <={16'h0000,8'h00,b3};
|
727 |
|
|
2'b01:if(M_signed) MOUT <={{24{b2[7]}},b2};
|
728 |
|
|
else MOUT <={16'h0000,8'h00,b2};
|
729 |
|
|
2'b10:if(M_signed) MOUT <={{24{b1[7]}},b1};
|
730 |
|
|
else MOUT <={16'h0000,8'h00,b1};
|
731 |
|
|
2'b11:if(M_signed) MOUT <={{24{b0[7]}},b0};
|
732 |
|
|
else MOUT <={16'h0000,8'h00,b0};
|
733 |
|
|
endcase
|
734 |
|
|
end
|
735 |
|
|
end
|
736 |
|
|
|
737 |
|
|
always @(posedge clock) begin
|
738 |
|
|
access_modeD<=access_mode;
|
739 |
|
|
DaddrD<=Daddr;
|
740 |
|
|
uread_access_reg<=uread_port_access;//Jul.7.2004
|
741 |
|
|
end
|
742 |
|
|
endmodule
|
743 |
|
|
|
744 |
|
|
</PRE>
|
745 |
|
|
</TH>
|
746 |
|
|
</TR>
|
747 |
|
|
</TBODY>
|
748 |
|
|
</TABLE>
|
749 |
|
|
<P><B>2.2.5 Decode</B>r</P>
|
750 |
|
|
<P>Includes disassembler for debug use.<BR>
|
751 |
|
|
$sprintf is the same as $sformat in Verilog-2001.</P>
|
752 |
|
|
<TABLE border="1">
|
753 |
|
|
<TBODY>
|
754 |
|
|
<TR>
|
755 |
|
|
<TH width="28" height="14" align="left">
|
756 |
|
|
<PRE>//Jun.28.2004
|
757 |
|
|
//Jun.30.2004 jump bug fix
|
758 |
|
|
//Jul.11.2004 target special zero
|
759 |
|
|
//Jan.20.2005 apply @*
|
760 |
|
|
`include "define.h"
|
761 |
|
|
//`define ALTERA
|
762 |
|
|
module decoder(clock,sync_reset,MWriteD1,RegWriteD2,A_Right_SELD1,RF_inputD2,
|
763 |
|
|
RF_input_addr,M_signD1,M_signD2,M_access_modeD1,M_access_modeD2,
|
764 |
|
|
ALU_FuncD2,Shift_FuncD2,source_addrD1,target_addrD1,IMMD2,
|
765 |
|
|
source_addrD2,target_addrD2,Shift_amountD2,PC_commandD1,IMMD1,IRD1,takenD3,takenD2,beqQ,bneQ,blezQ,bgtzQ,
|
766 |
|
|
DAddress,PC,memory_indata,MOUT,IMM,branchQQ,jumpQ,int_req,clear_int,int_address,
|
767 |
|
|
A_Left_SELD1,RRegSelD1,MWriteD2,NOP_Signal,mul_alu_selD2,mul_div_funcD2,
|
768 |
|
|
pause_out,control_state,Shift_Amount_selD2,uread_port,int_stateD1,bgezQ,bltzQ,write_busy);
|
769 |
|
|
|
770 |
|
|
input clock,sync_reset;
|
771 |
|
|
input takenD3,takenD2;
|
772 |
|
|
output MWriteD1,RegWriteD2;
|
773 |
|
|
output [1:0] A_Right_SELD1;
|
774 |
|
|
output [1:0] RF_inputD2;
|
775 |
|
|
output M_signD1,M_signD2;
|
776 |
|
|
output [1:0] M_access_modeD1,M_access_modeD2;
|
777 |
|
|
output [3:0] ALU_FuncD2;
|
778 |
|
|
output [1:0] Shift_FuncD2;
|
779 |
|
|
output [25:0] IMMD2,IMMD1;
|
780 |
|
|
output [4:0] source_addrD2,target_addrD2;
|
781 |
|
|
output [4:0] source_addrD1,target_addrD1,Shift_amountD2;
|
782 |
|
|
output [4:0] RF_input_addr;
|
783 |
|
|
output [2:0] PC_commandD1;
|
784 |
|
|
output [31:0] IRD1;
|
785 |
|
|
output beqQ,bneQ,blezQ,bgtzQ;
|
786 |
|
|
output bgezQ,bltzQ;
|
787 |
|
|
input [7:0] uread_port;
|
788 |
|
|
output int_stateD1;
|
789 |
|
|
input write_busy;//Apr.2.2005
|
790 |
|
|
|
791 |
|
|
`ifdef RAM4K
|
792 |
|
|
input [11:0] DAddress,PC;
|
793 |
|
|
input [11:0] int_address;
|
794 |
|
|
`else
|
795 |
|
|
input [25:0] DAddress,PC;
|
796 |
|
|
input [25:0] int_address;
|
797 |
|
|
`endif
|
798 |
|
|
|
799 |
|
|
|
800 |
|
|
input [31:0] memory_indata;
|
801 |
|
|
output [31:0] MOUT;
|
802 |
|
|
output [25:0] IMM;
|
803 |
|
|
output branchQQ,jumpQ;
|
804 |
|
|
input int_req;
|
805 |
|
|
output clear_int;
|
806 |
|
|
|
807 |
|
|
output A_Left_SELD1;
|
808 |
|
|
output [1:0] RRegSelD1;
|
809 |
|
|
output MWriteD2;
|
810 |
|
|
output NOP_Signal;
|
811 |
|
|
output [1:0] mul_alu_selD2;
|
812 |
|
|
output [3:0] mul_div_funcD2;
|
813 |
|
|
input pause_out;
|
814 |
|
|
output [7:0] control_state;
|
815 |
|
|
output Shift_Amount_selD2;
|
816 |
|
|
//For Debug Use
|
817 |
|
|
localparam [4:0] zero_=0,
|
818 |
|
|
at_=1,
|
819 |
|
|
v0_=2,
|
820 |
|
|
v1_=3,
|
821 |
|
|
a0_=4,
|
822 |
|
|
a1_=5,
|
823 |
|
|
a2_=6,
|
824 |
|
|
a3_=7,
|
825 |
|
|
t0_=8, t1_=9,t2_=10,t3_=11,t4_=12,t5_=13,t6_=14,t7_=15,
|
826 |
|
|
s0_=16,s1_=17,s2_=18,s3_=19,s4_=20,s5_=21,s6_=22,s7_=23,t8_=24,t9_=25,
|
827 |
|
|
k0_=26,k1_=27,gp_=28,sp_=29,s8_=30,ra_=31;
|
828 |
|
|
|
829 |
|
|
|
830 |
|
|
//regsiters
|
831 |
|
|
reg [31:0] IRD1;
|
832 |
|
|
reg [31:0] IRD2;
|
833 |
|
|
reg [1:0] RF_input_addr_selD1;
|
834 |
|
|
reg [4:0] RF_input_addr;
|
835 |
|
|
reg [1:0] Shift_FuncD1,Shift_FuncD2;
|
836 |
|
|
reg [3:0] ALU_FuncD2;
|
837 |
|
|
reg [1:0] A_Right_SELD1;
|
838 |
|
|
reg [1:0] RF_inputD2,RF_inputD1;
|
839 |
|
|
reg [1:0] M_access_modeD1,M_access_modeD2;
|
840 |
|
|
reg M_signD1,M_signD2;
|
841 |
|
|
|
842 |
|
|
reg MWriteD1,RegWriteD2,RegWriteD1,MWriteD2;
|
843 |
|
|
reg [2:0] PC_commandD1;
|
844 |
|
|
reg beqQ,bneQ,blezQ,bgtzQ;
|
845 |
|
|
reg bltzQ,bgezQ;//Jul.11.2004
|
846 |
|
|
reg branchQ,branchQQ,jumpQ;
|
847 |
|
|
reg [7:0] control_state;
|
848 |
|
|
reg sync_resetD1;
|
849 |
|
|
reg [31:0] memory_indataD2;
|
850 |
|
|
reg A_Left_SELD1;
|
851 |
|
|
reg [1:0] RRegSelD1;
|
852 |
|
|
reg takenD4,takenD5;
|
853 |
|
|
reg nop_bit;
|
854 |
|
|
reg [1:0] mul_alu_selD2;
|
855 |
|
|
reg mul_div_funcD1;
|
856 |
|
|
reg div_mode_ff;
|
857 |
|
|
reg [3:0] mul_div_funcD2;
|
858 |
|
|
reg excuting_flag;
|
859 |
|
|
reg excuting_flagD,excuting_flagDD;
|
860 |
|
|
reg Shift_Amount_selD2;
|
861 |
|
|
reg int_seqD1;
|
862 |
|
|
//wires
|
863 |
|
|
wire [31:0] IR;
|
864 |
|
|
|
865 |
|
|
wire [5:0] opecode=IR[31:26];
|
866 |
|
|
wire [5:0] opecodeD1=IRD1[31:26];
|
867 |
|
|
wire [5:0] opefuncD1=IRD1[5:0];
|
868 |
|
|
wire [5:0] opefunc=IR[5:0];
|
869 |
|
|
wire [4:0] destination_addrD1;//Apr.8.2005
|
870 |
|
|
|
871 |
|
|
wire NOP_Signal;
|
872 |
|
|
wire finish_operation;
|
873 |
|
|
|
874 |
|
|
|
875 |
|
|
|
876 |
|
|
assign int_stateD1=control_state==5;
|
877 |
|
|
|
878 |
|
|
assign IMMD2=IRD2[25:0];
|
879 |
|
|
assign IMMD1=IRD1[25:0];
|
880 |
|
|
assign source_addrD2=IRD2[25:21];
|
881 |
|
|
assign target_addrD2=IRD2[20:16];
|
882 |
|
|
assign source_addrD1=IRD1[25:21];
|
883 |
|
|
assign target_addrD1=IRD1[20:16];
|
884 |
|
|
assign destination_addrD1=IRD1[15:11];
|
885 |
|
|
assign Shift_amountD2=IRD2[10:6];
|
886 |
|
|
assign IMM=IR[25:0];
|
887 |
|
|
|
888 |
|
|
`ifdef Veritak //Disassenblar
|
889 |
|
|
reg [30*8:1] inst;
|
890 |
|
|
wire [5:0] op=IR[31:26];
|
891 |
|
|
wire [25:0] bra=PC+{{10{IR[15]}},IR[15:0]}*4;//+4;
|
892 |
|
|
wire [4:0] rs=IR[25:21];
|
893 |
|
|
wire [4:0] rt=IR[20:16];
|
894 |
|
|
wire [4:0] rd=IR[15:11];
|
895 |
|
|
wire [4:0] sh=IR[10:6];
|
896 |
|
|
reg [5*8:1] reg_name="abcd";
|
897 |
|
|
|
898 |
|
|
reg [30*8:1] instD1,instD2;
|
899 |
|
|
|
900 |
|
|
function [4*8:1] get_reg_name;
|
901 |
|
|
input [4:0] field;
|
902 |
|
|
begin
|
903 |
|
|
case (field)
|
904 |
|
|
0: get_reg_name="$z0";
|
905 |
|
|
1: get_reg_name="$at";
|
906 |
|
|
2: get_reg_name="$v0";
|
907 |
|
|
3: get_reg_name="$v1";
|
908 |
|
|
4: get_reg_name="$a0";
|
909 |
|
|
5: get_reg_name="$a1";
|
910 |
|
|
6: get_reg_name="$a2";
|
911 |
|
|
7: get_reg_name="$a3";
|
912 |
|
|
8,9,10,11,12,13,14,15:
|
913 |
|
|
$sprintf(get_reg_name,"$t%1d",field-8);
|
914 |
|
|
16,17,18,19,20,21,22,23,24,25: $sprintf(get_reg_name,"$s%1d",field-16);
|
915 |
|
|
26:get_reg_name="$k0";
|
916 |
|
|
27:get_reg_name="$k1";
|
917 |
|
|
28:get_reg_name="$gp";
|
918 |
|
|
29:get_reg_name="$sp";
|
919 |
|
|
30:get_reg_name="$s8";
|
920 |
|
|
31:get_reg_name="$ra";
|
921 |
|
|
endcase
|
922 |
|
|
end
|
923 |
|
|
endfunction
|
924 |
|
|
|
925 |
|
|
always @(posedge clock) begin
|
926 |
|
|
instD1<=inst;
|
927 |
|
|
instD2<=instD1;
|
928 |
|
|
end
|
929 |
|
|
|
930 |
|
|
always @*begin:sprintf //Jan.20.2005 @ (IR,op,bra,rs,rt,rd,sh) begin :sprintf
|
931 |
|
|
reg [4*8:1] rdn;//Mar.15.2005 =get_reg_name(rd);//
|
932 |
|
|
reg [4*8:1] rsn;//Mar.15.2005=get_reg_name(rs);
|
933 |
|
|
reg [4*8:1] rtn;//Mar.15.2005 =get_reg_name(rt);
|
934 |
|
|
rdn=get_reg_name(rd);
|
935 |
|
|
rsn=get_reg_name(rs);
|
936 |
|
|
rtn=get_reg_name(rt);
|
937 |
|
|
case (op)
|
938 |
|
|
0:
|
939 |
|
|
case (IR[5:0])
|
940 |
|
|
0: if (rd==0 && rt==0 && rs==0 ) $sprintf(inst,"nop");
|
941 |
|
|
else $sprintf(inst,"sll %s,%s,%2d\n",rdn,rtn,sh);
|
942 |
|
|
2:
|
943 |
|
|
$sprintf(inst," srl %s,%s,%2d\n",rdn,rtn,sh);
|
944 |
|
|
|
945 |
|
|
3:
|
946 |
|
|
$sprintf(inst," sra %s,%s,%2d\n",rdn,rtn,sh);
|
947 |
|
|
|
948 |
|
|
4:
|
949 |
|
|
$sprintf(inst," sllv %s,%s,%s\n",rdn,rtn,rsn);
|
950 |
|
|
|
951 |
|
|
6:
|
952 |
|
|
$sprintf(inst," srlv %s,%s,%s\n",rdn,rtn,rsn);
|
953 |
|
|
|
954 |
|
|
7:
|
955 |
|
|
$sprintf(inst," srav %s,%s,%s\n",rdn,rtn,rsn);
|
956 |
|
|
|
957 |
|
|
8:
|
958 |
|
|
$sprintf(inst," jr %s\n",rsn);
|
959 |
|
|
|
960 |
|
|
9:
|
961 |
|
|
$sprintf(inst," jalr %s\n",rsn);
|
962 |
|
|
|
963 |
|
|
12:
|
964 |
|
|
$sprintf(inst," syscall\n");
|
965 |
|
|
|
966 |
|
|
13:
|
967 |
|
|
$sprintf(inst," break");
|
968 |
|
|
|
969 |
|
|
16:
|
970 |
|
|
$sprintf(inst," mfhi %s\n",rdn);
|
971 |
|
|
|
972 |
|
|
17:
|
973 |
|
|
$sprintf(inst," mthi %s\n",rsn);
|
974 |
|
|
|
975 |
|
|
18:
|
976 |
|
|
$sprintf(inst," mflo %s\n",rdn);
|
977 |
|
|
|
978 |
|
|
19:
|
979 |
|
|
$sprintf(inst," mtlo %s\n",rsn);
|
980 |
|
|
|
981 |
|
|
24:
|
982 |
|
|
$sprintf(inst," mult %s,%s\n",rsn,rtn);
|
983 |
|
|
|
984 |
|
|
25:
|
985 |
|
|
$sprintf(inst," multu %s,%s\n",rsn,rtn);
|
986 |
|
|
|
987 |
|
|
26:
|
988 |
|
|
$sprintf(inst," div %s,%s\n",rsn,rtn);
|
989 |
|
|
|
990 |
|
|
27:
|
991 |
|
|
$sprintf(inst," divu %s,%s\n",rsn,rtn);
|
992 |
|
|
|
993 |
|
|
32:
|
994 |
|
|
|
995 |
|
|
$sprintf(inst," add %s,%s,%s",rdn,rsn,rtn);
|
996 |
|
|
|
997 |
|
|
33:
|
998 |
|
|
if(rt==0)
|
999 |
|
|
$sprintf(inst," move %s,%s\n",rdn,rsn);
|
1000 |
|
|
else
|
1001 |
|
|
$sprintf(inst," addu %s,%s,%s\n",rdn,rsn,rtn);
|
1002 |
|
|
|
1003 |
|
|
34:
|
1004 |
|
|
$sprintf(inst," sub %s,%s,%s\n",rdn,rsn,rtn);
|
1005 |
|
|
|
1006 |
|
|
35:
|
1007 |
|
|
$sprintf(inst," subu %s,%s,%s\n",rdn,rsn,rtn);
|
1008 |
|
|
|
1009 |
|
|
36:
|
1010 |
|
|
$sprintf(inst," and %s,%s,%s\n",rdn,rsn,rtn);
|
1011 |
|
|
|
1012 |
|
|
37:
|
1013 |
|
|
if(rt==0)
|
1014 |
|
|
$sprintf(inst," move %s,%s\n",rdn,rsn);
|
1015 |
|
|
else
|
1016 |
|
|
$sprintf(inst," or %s,%s,%s\n",rdn,rsn,rtn);
|
1017 |
|
|
|
1018 |
|
|
38:
|
1019 |
|
|
$sprintf(inst," xor %s,%s,%s\n",rdn,rsn,rtn);
|
1020 |
|
|
|
1021 |
|
|
39:
|
1022 |
|
|
$sprintf(inst," nor %s,%s,%s\n",rdn,rsn,rtn);
|
1023 |
|
|
|
1024 |
|
|
42:
|
1025 |
|
|
$sprintf(inst," slt %s,%s,%s\n",rdn,rsn,rtn);
|
1026 |
|
|
|
1027 |
|
|
43:
|
1028 |
|
|
$sprintf(inst," sltu %s,%s,%s\n",rdn,rsn,rtn);
|
1029 |
|
|
|
1030 |
|
|
default:
|
1031 |
|
|
$sprintf(inst,"Unknown Func. %08h\n",IR);
|
1032 |
|
|
|
1033 |
|
|
|
1034 |
|
|
|
1035 |
|
|
|
1036 |
|
|
endcase
|
1037 |
|
|
1:
|
1038 |
|
|
case (IR[20:16])
|
1039 |
|
|
0:
|
1040 |
|
|
$sprintf(inst," bltz %s,$%08h\n",rsn,bra);
|
1041 |
|
|
|
1042 |
|
|
1:
|
1043 |
|
|
$sprintf(inst," bgez %s,$%08h\n",rsn,bra);
|
1044 |
|
|
|
1045 |
|
|
16:
|
1046 |
|
|
$sprintf(inst," bltzal %s,$%08h\n",rsn,bra);
|
1047 |
|
|
|
1048 |
|
|
17:
|
1049 |
|
|
$sprintf(inst," bgezal %s,$%08h\n",rsn,bra);
|
1050 |
|
|
|
1051 |
|
|
default:
|
1052 |
|
|
$sprintf(inst,"Unknown1 %08h\n",IR);
|
1053 |
|
|
|
1054 |
|
|
endcase
|
1055 |
|
|
|
1056 |
|
|
2:
|
1057 |
|
|
$sprintf(inst," j $%08h\n",((IR*4)&32'h0ffffffc)+(PC&32'hf0000000));
|
1058 |
|
|
|
1059 |
|
|
3:
|
1060 |
|
|
$sprintf(inst," jal $%08h\n",((IR*4)&32'h0ffffffc)+(PC&32'hf0000000));
|
1061 |
|
|
|
1062 |
|
|
4:
|
1063 |
|
|
if(rs==0 && rt==0)
|
1064 |
|
|
$sprintf(inst," bra $%08h\n",bra);
|
1065 |
|
|
else
|
1066 |
|
|
$sprintf(inst," beq %s,%s,$%08h\n",rsn,rtn,bra);
|
1067 |
|
|
|
1068 |
|
|
5:
|
1069 |
|
|
$sprintf(inst," bne %s,%s,$%08h\n",rsn,rtn,bra);
|
1070 |
|
|
|
1071 |
|
|
6:
|
1072 |
|
|
$sprintf(inst," blez %s,$%08h\n",rsn,bra);
|
1073 |
|
|
|
1074 |
|
|
7:
|
1075 |
|
|
$sprintf(inst," bgtz %s,$%08h\n",rsn,bra);
|
1076 |
|
|
|
1077 |
|
|
8:
|
1078 |
|
|
$sprintf(inst," addi %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
|
1079 |
|
|
|
1080 |
|
|
9:
|
1081 |
|
|
if(rs==0)
|
1082 |
|
|
$sprintf(inst," li %s,#$%08h\n",rtn,IR[15:0]);
|
1083 |
|
|
else
|
1084 |
|
|
$sprintf(inst," addiu %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
|
1085 |
|
|
|
1086 |
|
|
10:
|
1087 |
|
|
$sprintf(inst," slti %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
|
1088 |
|
|
|
1089 |
|
|
11:
|
1090 |
|
|
$sprintf(inst," sltiu %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
|
1091 |
|
|
|
1092 |
|
|
12:
|
1093 |
|
|
$sprintf(inst," andi %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
|
1094 |
|
|
|
1095 |
|
|
13:
|
1096 |
|
|
if(rs==0)
|
1097 |
|
|
$sprintf(inst," li %s,#$%08h\n",rtn,IR[15:0]);
|
1098 |
|
|
else
|
1099 |
|
|
$sprintf(inst," ori %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
|
1100 |
|
|
|
1101 |
|
|
14:
|
1102 |
|
|
$sprintf(inst," xori %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
|
1103 |
|
|
|
1104 |
|
|
15://load upper immediate
|
1105 |
|
|
|
1106 |
|
|
$sprintf(inst," lui %s,#$%04h",rtn,IR[15:0]);
|
1107 |
|
|
|
1108 |
|
|
16, 17, 18, 19: begin
|
1109 |
|
|
if(rs>=16)
|
1110 |
|
|
$sprintf(inst," cop%d $%08h\n",op&3,IR[25:0]);
|
1111 |
|
|
else
|
1112 |
|
|
case(rsn)
|
1113 |
|
|
0:
|
1114 |
|
|
$sprintf(inst," mfc%d %s,%s\n",op&3,rtn,rdn);
|
1115 |
|
|
|
1116 |
|
|
2:
|
1117 |
|
|
$sprintf(inst," cfc%d %s,%s\n",op&3,rtn,rdn);
|
1118 |
|
|
|
1119 |
|
|
4:
|
1120 |
|
|
$sprintf(inst," mtc%d %s,%s\n",op&3,rtn,rdn);
|
1121 |
|
|
|
1122 |
|
|
6:
|
1123 |
|
|
$sprintf(inst," ctc%d %s,%s\n",op&3,rtn,rdn);
|
1124 |
|
|
|
1125 |
|
|
8, 12:
|
1126 |
|
|
if(rt&1)
|
1127 |
|
|
$sprintf(inst," bc%dt %d,%08h\n",op&3,rs*32+rt,bra);
|
1128 |
|
|
else
|
1129 |
|
|
$sprintf(inst," bc%df %d,%08h\n",op&3,rs*32+rt,bra);
|
1130 |
|
|
|
1131 |
|
|
|
1132 |
|
|
default:
|
1133 |
|
|
$sprintf(inst,"Unknown16 %08h\n",IR);
|
1134 |
|
|
endcase
|
1135 |
|
|
end
|
1136 |
|
|
32:
|
1137 |
|
|
$sprintf(inst," lb %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1138 |
|
|
|
1139 |
|
|
33:
|
1140 |
|
|
$sprintf(inst," lh %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1141 |
|
|
|
1142 |
|
|
34:
|
1143 |
|
|
$sprintf(inst," lwl %s,$%04h(%s)\n",IR[15:0],rsn);
|
1144 |
|
|
|
1145 |
|
|
35:
|
1146 |
|
|
$sprintf(inst," lw %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1147 |
|
|
|
1148 |
|
|
36:
|
1149 |
|
|
$sprintf(inst," lbu %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1150 |
|
|
|
1151 |
|
|
37:
|
1152 |
|
|
$sprintf(inst," lhu %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1153 |
|
|
|
1154 |
|
|
38:
|
1155 |
|
|
$sprintf(inst," lwr %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1156 |
|
|
|
1157 |
|
|
40:
|
1158 |
|
|
$sprintf(inst," sb %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1159 |
|
|
|
1160 |
|
|
41:
|
1161 |
|
|
$sprintf(inst," sh %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1162 |
|
|
|
1163 |
|
|
42:
|
1164 |
|
|
$sprintf(inst," swl %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1165 |
|
|
|
1166 |
|
|
43:
|
1167 |
|
|
$sprintf(inst," sw %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1168 |
|
|
|
1169 |
|
|
46:
|
1170 |
|
|
$sprintf(inst," swr %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
|
1171 |
|
|
|
1172 |
|
|
48, 49, 50, 51:
|
1173 |
|
|
$sprintf(inst," lwc%d %s,$%04h(%s)\n",op&3,rtn,IR[15:0],rsn);
|
1174 |
|
|
|
1175 |
|
|
56, 57, 58, 59:
|
1176 |
|
|
$sprintf(inst," swc%d %s,$%04h(%s)\n",op&3,rtn,IR[15:0],rsn);
|
1177 |
|
|
|
1178 |
|
|
default:
|
1179 |
|
|
$sprintf(inst,"UnknownOp %08h\n",IR);
|
1180 |
|
|
|
1181 |
|
|
|
1182 |
|
|
|
1183 |
|
|
|
1184 |
|
|
endcase
|
1185 |
|
|
end
|
1186 |
|
|
|
1187 |
|
|
|
1188 |
|
|
`endif
|
1189 |
|
|
//
|
1190 |
|
|
always @ (posedge clock) sync_resetD1 <=sync_reset;
|
1191 |
|
|
|
1192 |
|
|
|
1193 |
|
|
//IRD1
|
1194 |
|
|
always @ (posedge clock) begin
|
1195 |
|
|
if (sync_resetD1) IRD1 <=32'h00;
|
1196 |
|
|
else if ((control_state[5:0]==6'b00_0000 && int_req) ) IRD1<=int_address>>2;
|
1197 |
|
|
else if (opecode==6'b000_001) IRD1<={IR[31:21],5'b00000,IR[15:0]};//Jul.11.2004 target ‚ªSpecial zero
|
1198 |
|
|
else IRD1 <=IR;
|
1199 |
|
|
end
|
1200 |
|
|
|
1201 |
|
|
//IRD2
|
1202 |
|
|
always @ (posedge clock) begin
|
1203 |
|
|
IRD2 <=IRD1;
|
1204 |
|
|
end
|
1205 |
|
|
|
1206 |
|
|
//RF_input_addr [4:0]
|
1207 |
|
|
always @ (posedge clock) begin
|
1208 |
|
|
case (RF_input_addr_selD1)
|
1209 |
|
|
`RF_Ert_sel: RF_input_addr <=target_addrD1;
|
1210 |
|
|
`RF_Erd_sel: RF_input_addr <=destination_addrD1;
|
1211 |
|
|
`RF_R15_SEL: RF_input_addr <=`Last_Reg;
|
1212 |
|
|
`RF_INTR_SEL:RF_input_addr <=`Intr_Reg;
|
1213 |
|
|
default : RF_input_addr <=target_addrD1;
|
1214 |
|
|
endcase
|
1215 |
|
|
end
|
1216 |
|
|
|
1217 |
|
|
//int_seqD1
|
1218 |
|
|
always @(posedge clock) begin
|
1219 |
|
|
if (sync_reset) int_seqD1<=0;
|
1220 |
|
|
else int_seqD1<=control_state[5:0]==6'b00_0000 && int_req;
|
1221 |
|
|
|
1222 |
|
|
end
|
1223 |
|
|
|
1224 |
|
|
|
1225 |
|
|
// [1:0] Shift_FuncD1,Shift_FuncD2;
|
1226 |
|
|
always @ (posedge clock) begin
|
1227 |
|
|
Shift_FuncD2<=Shift_FuncD1;
|
1228 |
|
|
end
|
1229 |
|
|
|
1230 |
|
|
// [3:0] ALU_FuncD1,ALU_FuncD2;
|
1231 |
|
|
|
1232 |
|
|
|
1233 |
|
|
|
1234 |
|
|
always @ (posedge clock) begin
|
1235 |
|
|
M_access_modeD2<=M_access_modeD1;
|
1236 |
|
|
end
|
1237 |
|
|
|
1238 |
|
|
//M_signD1,M_signD2;
|
1239 |
|
|
always @ (posedge clock) begin
|
1240 |
|
|
M_signD2<=M_signD1;
|
1241 |
|
|
end
|
1242 |
|
|
|
1243 |
|
|
//takenD4
|
1244 |
|
|
always @ (posedge clock) begin
|
1245 |
|
|
if (sync_resetD1) takenD4<=1'b0;
|
1246 |
|
|
else if (NOP_Signal) takenD4<=1'b0;//TRY
|
1247 |
|
|
else takenD4<=takenD3;
|
1248 |
|
|
end
|
1249 |
|
|
//takenD5
|
1250 |
|
|
always @ (posedge clock) begin
|
1251 |
|
|
if (sync_resetD1) takenD5<=1'b0;
|
1252 |
|
|
else takenD5<=takenD4;
|
1253 |
|
|
end
|
1254 |
|
|
//RegWriteD2,RegWriteD1;
|
1255 |
|
|
always @ (posedge clock) begin
|
1256 |
|
|
if (sync_resetD1) begin
|
1257 |
|
|
RegWriteD2<=1'b0;
|
1258 |
|
|
end else if (takenD4 ||takenD5 || NOP_Signal ) RegWriteD2<=1'b0;//NOP
|
1259 |
|
|
else RegWriteD2<=RegWriteD1;
|
1260 |
|
|
|
1261 |
|
|
end
|
1262 |
|
|
|
1263 |
|
|
|
1264 |
|
|
|
1265 |
|
|
|
1266 |
|
|
//Combination logics
|
1267 |
|
|
//RegWrite;
|
1268 |
|
|
always @ (posedge clock) begin
|
1269 |
|
|
if (sync_resetD1) RegWriteD1<=1'b0;
|
1270 |
|
|
else if (control_state[5:0]==6'b00_0000 && int_req) RegWriteD1<=1'b1;
|
1271 |
|
|
else case (opecode)
|
1272 |
|
|
`loadbyte_signed : RegWriteD1<=1'b1;
|
1273 |
|
|
`loadbyte_unsigned : RegWriteD1<=1'b1;
|
1274 |
|
|
`loadword_signed : RegWriteD1<=1'b1;
|
1275 |
|
|
`loadword_unsigned : RegWriteD1<=1'b1;
|
1276 |
|
|
`loadlong : RegWriteD1<=1'b1;
|
1277 |
|
|
`jump_and_link_im: RegWriteD1<=1'b1;
|
1278 |
|
|
`andi : RegWriteD1<=1'b1;
|
1279 |
|
|
`addi : RegWriteD1<=1'b1 ;
|
1280 |
|
|
`addiu : RegWriteD1<=1'b1;
|
1281 |
|
|
`ori : RegWriteD1<=1'b1;
|
1282 |
|
|
`xori : RegWriteD1<=1'b1;
|
1283 |
|
|
`lui : RegWriteD1<=1'b1;
|
1284 |
|
|
`comp_im_signed : RegWriteD1<=1'b1;
|
1285 |
|
|
`comp_im_unsigned : RegWriteD1<=1'b1;
|
1286 |
|
|
6'b00_0000:
|
1287 |
|
|
case (opefunc)
|
1288 |
|
|
`divs: RegWriteD1<=1'b0;
|
1289 |
|
|
`divu: RegWriteD1<=1'b0;
|
1290 |
|
|
`muls: RegWriteD1<=1'b0;
|
1291 |
|
|
`mulu: RegWriteD1<=1'b0;
|
1292 |
|
|
default: RegWriteD1<=1'b1;
|
1293 |
|
|
endcase
|
1294 |
|
|
default: RegWriteD1<=1'b0;
|
1295 |
|
|
endcase
|
1296 |
|
|
end
|
1297 |
|
|
//
|
1298 |
|
|
always @ (posedge clock) begin
|
1299 |
|
|
if (sync_resetD1) mul_div_funcD1<=1'b0;
|
1300 |
|
|
else if (control_state[5:0]==6'b00_0000 && int_req) mul_div_funcD1<=1'b0;
|
1301 |
|
|
else case (opecode)
|
1302 |
|
|
|
1303 |
|
|
6'b00_0000:
|
1304 |
|
|
case (opefunc)
|
1305 |
|
|
`divs: begin
|
1306 |
|
|
mul_div_funcD1<=1'b1;
|
1307 |
|
|
div_mode_ff<=1'b1;
|
1308 |
|
|
end
|
1309 |
|
|
`divu: begin
|
1310 |
|
|
mul_div_funcD1<=1'b1;
|
1311 |
|
|
div_mode_ff<=1'b1;
|
1312 |
|
|
end
|
1313 |
|
|
`muls: begin
|
1314 |
|
|
mul_div_funcD1<=1'b1;
|
1315 |
|
|
div_mode_ff<=1'b0;
|
1316 |
|
|
end
|
1317 |
|
|
`mulu: begin
|
1318 |
|
|
mul_div_funcD1<=1'b1;
|
1319 |
|
|
div_mode_ff<=1'b0;
|
1320 |
|
|
end
|
1321 |
|
|
default: mul_div_funcD1<=1'b0;
|
1322 |
|
|
endcase
|
1323 |
|
|
default: mul_div_funcD1<=1'b0;
|
1324 |
|
|
endcase
|
1325 |
|
|
end
|
1326 |
|
|
|
1327 |
|
|
//mu_div_func
|
1328 |
|
|
//mul_alu_selD2/excuting_flag
|
1329 |
|
|
always @ (posedge clock) begin
|
1330 |
|
|
if (sync_resetD1) begin
|
1331 |
|
|
mul_div_funcD2 <=`mult_nothing;
|
1332 |
|
|
mul_alu_selD2<=2'b00;
|
1333 |
|
|
end else if ( mul_div_funcD2 [3] ) mul_div_funcD2[3]<=1'b0;////
|
1334 |
|
|
|
1335 |
|
|
else if( !NOP_Signal) //
|
1336 |
|
|
case (opecodeD1)
|
1337 |
|
|
6'b00_0000:
|
1338 |
|
|
case (opefuncD1)
|
1339 |
|
|
`divs: begin
|
1340 |
|
|
mul_div_funcD2<=`mult_signed_divide;
|
1341 |
|
|
|
1342 |
|
|
end
|
1343 |
|
|
`divu: begin
|
1344 |
|
|
mul_div_funcD2<=`mult_divide;
|
1345 |
|
|
end
|
1346 |
|
|
`muls: begin
|
1347 |
|
|
mul_div_funcD2<=`mult_signed_mult;
|
1348 |
|
|
end
|
1349 |
|
|
`mulu: begin
|
1350 |
|
|
mul_div_funcD2<=`mult_mult;
|
1351 |
|
|
end
|
1352 |
|
|
|
1353 |
|
|
`mfhi : begin
|
1354 |
|
|
if (!pause_out)mul_div_funcD2<=`mult_read_hi;
|
1355 |
|
|
mul_alu_selD2<=`MUL_hi_SEL;
|
1356 |
|
|
end
|
1357 |
|
|
`mflo : begin
|
1358 |
|
|
if(!pause_out) mul_div_funcD2<=`mult_read_lo;
|
1359 |
|
|
mul_alu_selD2<=`MUL_lo_SEL;
|
1360 |
|
|
end
|
1361 |
|
|
default: begin
|
1362 |
|
|
mul_div_funcD2 <=`mult_read_lo;
|
1363 |
|
|
mul_alu_selD2<=2'b00;
|
1364 |
|
|
end
|
1365 |
|
|
endcase
|
1366 |
|
|
default: mul_alu_selD2<=2'b00;
|
1367 |
|
|
endcase
|
1368 |
|
|
|
1369 |
|
|
end
|
1370 |
|
|
|
1371 |
|
|
always @ (posedge clock) begin
|
1372 |
|
|
if (sync_resetD1) excuting_flagD<=1'b0;
|
1373 |
|
|
else excuting_flagD<=excuting_flag;
|
1374 |
|
|
end
|
1375 |
|
|
|
1376 |
|
|
always @ (posedge clock) begin
|
1377 |
|
|
if (sync_resetD1) excuting_flagDD<=1'b0;
|
1378 |
|
|
else excuting_flagDD<=excuting_flagD;
|
1379 |
|
|
end
|
1380 |
|
|
assign finish_operation=excuting_flag && !pause_out;
|
1381 |
|
|
|
1382 |
|
|
|
1383 |
|
|
//MWrite
|
1384 |
|
|
always @ (posedge clock) begin
|
1385 |
|
|
if (sync_resetD1) MWriteD1<=1'b0;
|
1386 |
|
|
|
1387 |
|
|
else case (opecode)
|
1388 |
|
|
`storebyte: MWriteD1<=1'b1;
|
1389 |
|
|
`storeword: MWriteD1<=1'b1;
|
1390 |
|
|
`storelong: MWriteD1<=1'b1;
|
1391 |
|
|
default: MWriteD1<=1'b0;
|
1392 |
|
|
endcase
|
1393 |
|
|
end
|
1394 |
|
|
|
1395 |
|
|
always @ (posedge clock) begin
|
1396 |
|
|
if (sync_resetD1) MWriteD2<=1'b0;
|
1397 |
|
|
else if ( NOP_Signal ) MWriteD2<=1'b0;
|
1398 |
|
|
else MWriteD2<=MWriteD1;//taken NOP
|
1399 |
|
|
end
|
1400 |
|
|
|
1401 |
|
|
|
1402 |
|
|
//M_sign
|
1403 |
|
|
always @ (posedge clock) begin
|
1404 |
|
|
if (sync_resetD1) M_signD1<=`M_unsigned;
|
1405 |
|
|
else case (opecode)
|
1406 |
|
|
`loadbyte_signed : M_signD1<=`M_signed;
|
1407 |
|
|
`loadbyte_unsigned : M_signD1<=`M_unsigned;
|
1408 |
|
|
`loadword_signed : M_signD1<=`M_signed;
|
1409 |
|
|
`loadword_unsigned : M_signD1<=`M_unsigned;
|
1410 |
|
|
`loadlong : M_signD1<=`M_unsigned;
|
1411 |
|
|
`storebyte: M_signD1<=`M_unsigned;
|
1412 |
|
|
`storeword: M_signD1<=`M_unsigned;
|
1413 |
|
|
`storelong: M_signD1<=`M_unsigned;
|
1414 |
|
|
default: M_signD1<=`M_unsigned;
|
1415 |
|
|
endcase
|
1416 |
|
|
end
|
1417 |
|
|
|
1418 |
|
|
|
1419 |
|
|
|
1420 |
|
|
|
1421 |
|
|
// [1:0] M_access_mode
|
1422 |
|
|
always @ (posedge clock) begin
|
1423 |
|
|
if (sync_resetD1) M_access_modeD1<=`LONG_ACCESS;
|
1424 |
|
|
else case (opecode)
|
1425 |
|
|
`loadbyte_signed : M_access_modeD1<=`BYTE_ACCESS;
|
1426 |
|
|
`loadbyte_unsigned : M_access_modeD1<=`BYTE_ACCESS;
|
1427 |
|
|
`loadword_signed : M_access_modeD1<=`WORD_ACCESS;
|
1428 |
|
|
`loadword_unsigned : M_access_modeD1<=`WORD_ACCESS;
|
1429 |
|
|
`loadlong : M_access_modeD1<=`LONG_ACCESS;
|
1430 |
|
|
`storebyte: M_access_modeD1<=`BYTE_ACCESS;
|
1431 |
|
|
`storeword: M_access_modeD1<=`WORD_ACCESS;
|
1432 |
|
|
`storelong: M_access_modeD1<=`LONG_ACCESS;
|
1433 |
|
|
default: M_access_modeD1<=`LONG_ACCESS;
|
1434 |
|
|
endcase
|
1435 |
|
|
end
|
1436 |
|
|
|
1437 |
|
|
|
1438 |
|
|
|
1439 |
|
|
|
1440 |
|
|
// [2:0] RF_input Shift_Amount_sel
|
1441 |
|
|
always @ (posedge clock) begin
|
1442 |
|
|
if (sync_resetD1) begin
|
1443 |
|
|
RF_inputD2 <=`RF_ALU_sel;
|
1444 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
|
1445 |
|
|
end
|
1446 |
|
|
else if ((int_seqD1) || NOP_Signal ) RF_inputD2<=`RF_PC_SEL;//Jul.7.2004
|
1447 |
|
|
else
|
1448 |
|
|
case (opecodeD1)
|
1449 |
|
|
`lui :RF_inputD2 <=`SHIFT16_SEL;
|
1450 |
|
|
`jump_and_link_im: RF_inputD2<=`RF_PC_SEL;
|
1451 |
|
|
|
1452 |
|
|
6'b00_0000:
|
1453 |
|
|
case (opefuncD1)
|
1454 |
|
|
`jump_and_link_register : RF_inputD2<=`RF_PC_SEL;
|
1455 |
|
|
`lsl : begin
|
1456 |
|
|
RF_inputD2<=`RF_Shifter_sel ;
|
1457 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
|
1458 |
|
|
end
|
1459 |
|
|
`sllv : begin
|
1460 |
|
|
RF_inputD2<=`RF_Shifter_sel ;
|
1461 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
|
1462 |
|
|
end
|
1463 |
|
|
`asr : begin
|
1464 |
|
|
RF_inputD2<=`RF_Shifter_sel ;
|
1465 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
|
1466 |
|
|
end
|
1467 |
|
|
`srav : begin
|
1468 |
|
|
RF_inputD2<=`RF_Shifter_sel ;
|
1469 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
|
1470 |
|
|
end
|
1471 |
|
|
|
1472 |
|
|
`lsr : begin
|
1473 |
|
|
RF_inputD2<=`RF_Shifter_sel;
|
1474 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
|
1475 |
|
|
end
|
1476 |
|
|
`srlv : begin
|
1477 |
|
|
RF_inputD2<=`RF_Shifter_sel;
|
1478 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
|
1479 |
|
|
end
|
1480 |
|
|
|
1481 |
|
|
|
1482 |
|
|
`mfhi : RF_inputD2<=`RF_PC_SEL;
|
1483 |
|
|
`mflo : RF_inputD2<=`RF_PC_SEL;
|
1484 |
|
|
default : begin
|
1485 |
|
|
RF_inputD2<=`RF_ALU_sel;
|
1486 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
|
1487 |
|
|
end
|
1488 |
|
|
endcase
|
1489 |
|
|
default: begin
|
1490 |
|
|
RF_inputD2<=`RF_ALU_sel;
|
1491 |
|
|
Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
|
1492 |
|
|
end
|
1493 |
|
|
endcase
|
1494 |
|
|
end
|
1495 |
|
|
|
1496 |
|
|
|
1497 |
|
|
//[1:0] A_Right_SEL
|
1498 |
|
|
always @ (posedge clock) begin
|
1499 |
|
|
casex (opecode)
|
1500 |
|
|
`storebyte: A_Right_SELD1<=`A_RIGHT_ERT;
|
1501 |
|
|
`storeword: A_Right_SELD1<=`A_RIGHT_ERT;
|
1502 |
|
|
`storelong: A_Right_SELD1<=`A_RIGHT_ERT;
|
1503 |
|
|
`andi : A_Right_SELD1<=`Imm_unsigned ;
|
1504 |
|
|
`addi : A_Right_SELD1<=`Imm_signed ;
|
1505 |
|
|
`addiu : A_Right_SELD1<=`Imm_signed;
|
1506 |
|
|
`ori : A_Right_SELD1<=`Imm_unsigned;
|
1507 |
|
|
`xori : A_Right_SELD1<=`Imm_unsigned;
|
1508 |
|
|
|
1509 |
|
|
`beq : A_Right_SELD1<=`A_RIGHT_ERT;
|
1510 |
|
|
`bgtz : A_Right_SELD1<=`A_RIGHT_ERT;
|
1511 |
|
|
`blez : A_Right_SELD1<=`A_RIGHT_ERT;
|
1512 |
|
|
`bne : A_Right_SELD1<=`A_RIGHT_ERT;
|
1513 |
|
|
|
1514 |
|
|
|
1515 |
|
|
`comp_im_signed : A_Right_SELD1<=`Imm_signed;
|
1516 |
|
|
`comp_im_unsigned : A_Right_SELD1<=`Imm_signed;
|
1517 |
|
|
|
1518 |
|
|
//6'b00_0000:
|
1519 |
|
|
6'b00_000?://Jul.11.2004 target select
|
1520 |
|
|
case (opefunc)
|
1521 |
|
|
|
1522 |
|
|
default : A_Right_SELD1<=`A_RIGHT_ERT;
|
1523 |
|
|
endcase
|
1524 |
|
|
default: A_Right_SELD1<=`Imm_signed;
|
1525 |
|
|
endcase
|
1526 |
|
|
end
|
1527 |
|
|
|
1528 |
|
|
|
1529 |
|
|
//Interim A_Left_SELD1RRegSelD1
|
1530 |
|
|
always @ (posedge clock) begin
|
1531 |
|
|
case (opecode)
|
1532 |
|
|
default: A_Left_SELD1<=0;//always Left_latch
|
1533 |
|
|
endcase
|
1534 |
|
|
end
|
1535 |
|
|
|
1536 |
|
|
always @ (posedge clock) begin
|
1537 |
|
|
if ((control_state[5:0]==6'b00__0000 && int_req) ) RRegSelD1<=`NREG_SEL;//Jul.13.2004
|
1538 |
|
|
else case (opecode)
|
1539 |
|
|
`loadbyte_signed : RRegSelD1<=`MOUT_SEL;
|
1540 |
|
|
`loadbyte_unsigned : RRegSelD1<=`MOUT_SEL;
|
1541 |
|
|
`loadword_signed : RRegSelD1<=`MOUT_SEL;
|
1542 |
|
|
`loadword_unsigned : RRegSelD1<=`MOUT_SEL;
|
1543 |
|
|
`loadlong : RRegSelD1<=`MOUT_SEL;
|
1544 |
|
|
default: RRegSelD1<=`NREG_SEL;//Interim MULSEL
|
1545 |
|
|
endcase
|
1546 |
|
|
end
|
1547 |
|
|
|
1548 |
|
|
// [3:0] ALU_Func[1:0] ;
|
1549 |
|
|
always @ (posedge clock) begin
|
1550 |
|
|
|
1551 |
|
|
case (opecodeD1)
|
1552 |
|
|
`andi : ALU_FuncD2<=`ALU_AND;
|
1553 |
|
|
`addi : ALU_FuncD2<=`ALU_ADD ;
|
1554 |
|
|
`addiu : ALU_FuncD2<=`ALU_ADD;
|
1555 |
|
|
`ori : ALU_FuncD2<=`ALU_OR;
|
1556 |
|
|
`xori : ALU_FuncD2<=`ALU_XOR;
|
1557 |
|
|
`comp_im_signed : ALU_FuncD2<=`ALU_LESS_THAN_SIGNED;
|
1558 |
|
|
`comp_im_unsigned : ALU_FuncD2<=`ALU_LESS_THAN_UNSIGNED;
|
1559 |
|
|
6'b00_0000:
|
1560 |
|
|
case (opefuncD1)
|
1561 |
|
|
`add : ALU_FuncD2<=`ALU_ADD ;
|
1562 |
|
|
`addu : ALU_FuncD2<=`ALU_ADD ;
|
1563 |
|
|
`sub : ALU_FuncD2<=`ALU_SUBTRACT;
|
1564 |
|
|
`subu : ALU_FuncD2<=`ALU_SUBTRACT;
|
1565 |
|
|
`and : ALU_FuncD2<=`ALU_AND;
|
1566 |
|
|
`nor : ALU_FuncD2<=`ALU_NOR;
|
1567 |
|
|
`or : ALU_FuncD2<=`ALU_OR;
|
1568 |
|
|
`xor : ALU_FuncD2<=`ALU_XOR;
|
1569 |
|
|
`comp_signed : ALU_FuncD2<=`ALU_LESS_THAN_SIGNED;
|
1570 |
|
|
`comp_unsigned : ALU_FuncD2<=`ALU_LESS_THAN_UNSIGNED;
|
1571 |
|
|
|
1572 |
|
|
default : ALU_FuncD2<=`ALU_NOTHING;//Jul.6.2004 ALU_NOTHING;
|
1573 |
|
|
endcase
|
1574 |
|
|
default: ALU_FuncD2<=`ALU_NOTHING;//Jul.6.2004 ALU_NOTHING;
|
1575 |
|
|
endcase
|
1576 |
|
|
end
|
1577 |
|
|
|
1578 |
|
|
|
1579 |
|
|
// [1:0] Shift_Func;
|
1580 |
|
|
always @ (posedge clock) begin
|
1581 |
|
|
case (opecode)
|
1582 |
|
|
6'b00_0000:
|
1583 |
|
|
case (opefunc)
|
1584 |
|
|
`lsl : Shift_FuncD1<=`SHIFT_LEFT;
|
1585 |
|
|
`sllv : Shift_FuncD1<=`SHIFT_LEFT;
|
1586 |
|
|
`asr : Shift_FuncD1<=`SHIFT_RIGHT_SIGNED;
|
1587 |
|
|
`srav : Shift_FuncD1<=`SHIFT_RIGHT_SIGNED;
|
1588 |
|
|
`lsr : Shift_FuncD1<=`SHIFT_RIGHT_UNSIGNED;
|
1589 |
|
|
`srlv : Shift_FuncD1<=`SHIFT_RIGHT_UNSIGNED;
|
1590 |
|
|
default : Shift_FuncD1<=`SHIFT_LEFT;//Jul.5.2004 `SHIFT_NOTHING;
|
1591 |
|
|
endcase
|
1592 |
|
|
default: Shift_FuncD1<=`SHIFT_LEFT;//Jul.5.2004`SHIFT_NOTHING;
|
1593 |
|
|
endcase
|
1594 |
|
|
end
|
1595 |
|
|
|
1596 |
|
|
|
1597 |
|
|
|
1598 |
|
|
//RF_input_addr_sel
|
1599 |
|
|
always @ (posedge clock) begin
|
1600 |
|
|
if ((control_state[5:0]==6'b00__0000 && int_req) ) RF_input_addr_selD1<=`RF_INTR_SEL;
|
1601 |
|
|
else
|
1602 |
|
|
case (opecode)
|
1603 |
|
|
`andi : RF_input_addr_selD1<=`RF_Ert_sel;
|
1604 |
|
|
`addi : RF_input_addr_selD1<=`RF_Ert_sel;
|
1605 |
|
|
`ori : RF_input_addr_selD1<=`RF_Ert_sel;
|
1606 |
|
|
`xori : RF_input_addr_selD1<=`RF_Ert_sel;
|
1607 |
|
|
`jump_and_link_im: RF_input_addr_selD1<=`RF_R15_SEL;
|
1608 |
|
|
`lui : RF_input_addr_selD1<=`RF_Ert_sel;
|
1609 |
|
|
`comp_im_signed : RF_input_addr_selD1<=`RF_Ert_sel;
|
1610 |
|
|
`comp_im_unsigned: RF_input_addr_selD1<=`RF_Ert_sel;
|
1611 |
|
|
6'b00_0000:
|
1612 |
|
|
case (opefunc)
|
1613 |
|
|
`jump_and_link_register: RF_input_addr_selD1<=`RF_R15_SEL;
|
1614 |
|
|
|
1615 |
|
|
default : RF_input_addr_selD1<=`RF_Erd_sel;
|
1616 |
|
|
endcase
|
1617 |
|
|
default: RF_input_addr_selD1<=`RF_Ert_sel;
|
1618 |
|
|
endcase
|
1619 |
|
|
end
|
1620 |
|
|
|
1621 |
|
|
|
1622 |
|
|
|
1623 |
|
|
|
1624 |
|
|
|
1625 |
|
|
//PC_command decoder
|
1626 |
|
|
// always @ (posedge clock) begin
|
1627 |
|
|
always @(opecode,control_state,int_req,opefunc,NOP_Signal,takenD3,takenD4) begin//Jul.2.2004
|
1628 |
|
|
if (takenD3 || takenD4) PC_commandD1<=`PC_INC;//
|
1629 |
|
|
else case (opecode)
|
1630 |
|
|
|
1631 |
|
|
6'b00_0000:
|
1632 |
|
|
case (opefunc)
|
1633 |
|
|
`jmp_register : PC_commandD1<=`PC_REG;
|
1634 |
|
|
default: PC_commandD1<=`PC_INC;
|
1635 |
|
|
endcase
|
1636 |
|
|
default : PC_commandD1<=`PC_INC;
|
1637 |
|
|
endcase
|
1638 |
|
|
end
|
1639 |
|
|
//unsuppurted command detector Jul.11.2004
|
1640 |
|
|
always @(posedge clock) begin
|
1641 |
|
|
case (opecode)
|
1642 |
|
|
6'b000_001://Jul.11.2004 simple decode
|
1643 |
|
|
case (IR[20:16])
|
1644 |
|
|
|
1645 |
|
|
`bltzal :begin
|
1646 |
|
|
$display("unsupported command");
|
1647 |
|
|
$stop;
|
1648 |
|
|
end
|
1649 |
|
|
`bgezal : begin
|
1650 |
|
|
$display("unsupported command");
|
1651 |
|
|
$stop;
|
1652 |
|
|
end
|
1653 |
|
|
|
1654 |
|
|
`bltzall:begin
|
1655 |
|
|
$display("unsupported command");
|
1656 |
|
|
$stop;
|
1657 |
|
|
end
|
1658 |
|
|
`bltzl:begin
|
1659 |
|
|
$display("unsupported command");
|
1660 |
|
|
$stop;
|
1661 |
|
|
end
|
1662 |
|
|
`bgezall:begin
|
1663 |
|
|
$display("unsupported command");
|
1664 |
|
|
$stop;
|
1665 |
|
|
end
|
1666 |
|
|
`bgezl: begin
|
1667 |
|
|
$display("unsupported command");
|
1668 |
|
|
$stop;
|
1669 |
|
|
end
|
1670 |
|
|
endcase
|
1671 |
|
|
endcase
|
1672 |
|
|
|
1673 |
|
|
|
1674 |
|
|
end
|
1675 |
|
|
|
1676 |
|
|
|
1677 |
|
|
|
1678 |
|
|
always @ (posedge clock) begin
|
1679 |
|
|
if ((control_state[5:0]==6'b00_0000 && int_req) ) begin
|
1680 |
|
|
jumpQ<=1'b1;
|
1681 |
|
|
branchQ<=1'b0;////Jun.30.2004
|
1682 |
|
|
end else if (takenD3) begin
|
1683 |
|
|
jumpQ<=1'b0;//inhibit jump at delayed slot2
|
1684 |
|
|
branchQ<=1'b0;//TRY Jun.30.2004
|
1685 |
|
|
end else
|
1686 |
|
|
case (opecode)
|
1687 |
|
|
`jump: begin
|
1688 |
|
|
jumpQ<=1'b1;
|
1689 |
|
|
branchQ<=1'b0;//Jun.30.2004
|
1690 |
|
|
end
|
1691 |
|
|
`jump_and_link_im: begin
|
1692 |
|
|
jumpQ<=1'b1;
|
1693 |
|
|
branchQ<=1'b0;//Jun.30.2004
|
1694 |
|
|
end
|
1695 |
|
|
`beq : begin
|
1696 |
|
|
jumpQ<=1'b0;//Jun.30.2004
|
1697 |
|
|
branchQ<=1'b1;
|
1698 |
|
|
end
|
1699 |
|
|
`bgtz : begin
|
1700 |
|
|
jumpQ<=1'b0;//Jun.30.2004
|
1701 |
|
|
branchQ<=1'b1;
|
1702 |
|
|
end
|
1703 |
|
|
`blez : begin
|
1704 |
|
|
jumpQ<=1'b0;//Jun.30.2004
|
1705 |
|
|
branchQ<=1'b1;
|
1706 |
|
|
end
|
1707 |
|
|
`bne : begin
|
1708 |
|
|
jumpQ<=1'b0;//Jun.30.2004
|
1709 |
|
|
branchQ<=1'b1;
|
1710 |
|
|
end
|
1711 |
|
|
6'b000_001://Jul.11.2004 simple decode
|
1712 |
|
|
begin
|
1713 |
|
|
jumpQ<=1'b0;
|
1714 |
|
|
branchQ<=1'b1;
|
1715 |
|
|
end
|
1716 |
|
|
|
1717 |
|
|
default : begin
|
1718 |
|
|
jumpQ<=1'b0;
|
1719 |
|
|
branchQ<=1'b0;
|
1720 |
|
|
end
|
1721 |
|
|
endcase
|
1722 |
|
|
end
|
1723 |
|
|
|
1724 |
|
|
always @ (posedge clock) begin
|
1725 |
|
|
if (NOP_Signal) branchQQ<=1'b0;
|
1726 |
|
|
else branchQQ<=branchQ;
|
1727 |
|
|
end
|
1728 |
|
|
|
1729 |
|
|
|
1730 |
|
|
|
1731 |
|
|
//For Critical Path
|
1732 |
|
|
always @(posedge clock) begin
|
1733 |
|
|
if (sync_resetD1) beqQ<=0;
|
1734 |
|
|
else if ((control_state[5:0]==6'b00_0000 && int_req) ) beqQ<=1'b0;
|
1735 |
|
|
else if (opecode==`beq) beqQ<=1'b1;
|
1736 |
|
|
else beqQ<=1'b0;
|
1737 |
|
|
end
|
1738 |
|
|
|
1739 |
|
|
//Jul.11.2004 bltz
|
1740 |
|
|
always @(posedge clock) begin
|
1741 |
|
|
if (sync_resetD1) bltzQ<=0;
|
1742 |
|
|
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bltzQ<=1'b0;
|
1743 |
|
|
else if (opecode==6'b000_001 && IR[20:16]==`bltz) bltzQ<=1'b1;//Jul.13.2004
|
1744 |
|
|
else bltzQ<=1'b0;
|
1745 |
|
|
end
|
1746 |
|
|
//Jul.11.2004 bgez
|
1747 |
|
|
always @(posedge clock) begin
|
1748 |
|
|
if (sync_resetD1) bgezQ<=0;
|
1749 |
|
|
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bgezQ<=1'b0;
|
1750 |
|
|
else if (opecode==6'b000_0001 && IR[20:16]==`bgez) bgezQ<=1'b1;//Jul.13.2004
|
1751 |
|
|
else bgezQ<=1'b0;
|
1752 |
|
|
end
|
1753 |
|
|
|
1754 |
|
|
|
1755 |
|
|
always @(posedge clock) begin
|
1756 |
|
|
if (sync_resetD1) bgtzQ<=0;
|
1757 |
|
|
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bgtzQ<=1'b0;
|
1758 |
|
|
else if (opecode==`bgtz) bgtzQ<=1'b1;
|
1759 |
|
|
else bgtzQ<=1'b0;
|
1760 |
|
|
end
|
1761 |
|
|
always @(posedge clock) begin
|
1762 |
|
|
if (sync_resetD1) blezQ<=0;
|
1763 |
|
|
else if ((control_state[5:0]==6'b00_0000 && int_req) ) blezQ<=1'b0;
|
1764 |
|
|
else if (opecode==`blez) blezQ<=1'b1;
|
1765 |
|
|
else blezQ<=1'b0;
|
1766 |
|
|
end
|
1767 |
|
|
always @(posedge clock) begin
|
1768 |
|
|
if (sync_resetD1) bneQ<=0;
|
1769 |
|
|
else if ((control_state[5:0]==6'b00_0000 && int_req) ) bneQ<=1'b0;
|
1770 |
|
|
else if (opecode==`bne) bneQ<=1'b1;
|
1771 |
|
|
else bneQ<=1'b0;
|
1772 |
|
|
end
|
1773 |
|
|
|
1774 |
|
|
//
|
1775 |
|
|
always @(posedge clock) begin
|
1776 |
|
|
if (sync_resetD1) begin
|
1777 |
|
|
|
1778 |
|
|
excuting_flag<=1'b0;//
|
1779 |
|
|
end else
|
1780 |
|
|
begin
|
1781 |
|
|
if (!pause_out && excuting_flagDD) excuting_flag<=1'b0;
|
1782 |
|
|
else case (opecode)
|
1783 |
|
|
6'b00_0000:
|
1784 |
|
|
case (opefunc)
|
1785 |
|
|
`divs: excuting_flag<=1'b1;
|
1786 |
|
|
`divu: excuting_flag<=1'b1;
|
1787 |
|
|
`muls: excuting_flag<=1'b1;
|
1788 |
|
|
`mulu: excuting_flag<=1'b1;
|
1789 |
|
|
endcase
|
1790 |
|
|
endcase
|
1791 |
|
|
end
|
1792 |
|
|
end
|
1793 |
|
|
|
1794 |
|
|
always @(posedge clock) begin
|
1795 |
|
|
if (sync_resetD1) begin
|
1796 |
|
|
control_state<=6'b00_0000;
|
1797 |
|
|
end else
|
1798 |
|
|
begin
|
1799 |
|
|
casex (control_state[5:0])
|
1800 |
|
|
6'b00_0000:
|
1801 |
|
|
begin
|
1802 |
|
|
if(int_req) control_state<=6'b000_101;//
|
1803 |
|
|
else
|
1804 |
|
|
case (opecode)
|
1805 |
|
|
`jump: control_state<=6'b100_000;
|
1806 |
|
|
`jump_and_link_im: control_state<=6'b100_000;
|
1807 |
|
|
`beq : control_state<=6'b110_000;
|
1808 |
|
|
`bgtz : control_state<=6'b110_000;
|
1809 |
|
|
`blez : control_state<=6'b110_000;
|
1810 |
|
|
`bne : control_state<=6'b110_000;
|
1811 |
|
|
6'b000_001: control_state<=6'b110_000;//Jul.11.2004 Special Branch
|
1812 |
|
|
6'b00_0000:
|
1813 |
|
|
case (opefunc)
|
1814 |
|
|
`jump_and_link_register: control_state<=6'b101_000;
|
1815 |
|
|
`jmp_register : control_state<=6'b101_000;
|
1816 |
|
|
|
1817 |
|
|
`mfhi: if (excuting_flag) control_state<=8'b00_000_010;
|
1818 |
|
|
`mflo: if (excuting_flag) control_state<=8'b00_000_010;
|
1819 |
|
|
default: control_state<=6'b00_0000;//for safety
|
1820 |
|
|
endcase
|
1821 |
|
|
endcase
|
1822 |
|
|
|
1823 |
|
|
|
1824 |
|
|
|
1825 |
|
|
end
|
1826 |
|
|
6'b???_101: control_state<=6'b000_000;//interrupt_nop state
|
1827 |
|
|
6'b100_000: control_state<=6'b000_000;//fixed_jump state
|
1828 |
|
|
6'b101_000: control_state<=6'b001_100;//jump&link state
|
1829 |
|
|
6'b001_100: control_state<=6'b000_000;//NOP2 state
|
1830 |
|
|
6'b110_000: control_state<=6'b000_100;//delayed branch
|
1831 |
|
|
6'b000_100: `ifdef RAM4K//Priotiry Area
|
1832 |
|
|
if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1833 |
|
|
else case (opecode)
|
1834 |
|
|
`jump: control_state<=6'b100_000;
|
1835 |
|
|
`jump_and_link_im: control_state<=6'b100_000;
|
1836 |
|
|
`beq : control_state<=6'b110_000;
|
1837 |
|
|
`bgtz : control_state<=6'b110_000;
|
1838 |
|
|
`blez : control_state<=6'b110_000;
|
1839 |
|
|
`bne : control_state<=6'b110_000;
|
1840 |
|
|
6'b000_001: control_state<=6'b110_000;//Jul.11.2004 Special Branch
|
1841 |
|
|
6'b00_0000:
|
1842 |
|
|
case (opefunc)
|
1843 |
|
|
`jump_and_link_register: control_state<=6'b101_000;
|
1844 |
|
|
`jmp_register : control_state<=6'b101_000;
|
1845 |
|
|
`mfhi: if (excuting_flag) control_state<=8'b00_000_010;
|
1846 |
|
|
`mflo: if (excuting_flag) control_state<=8'b00_000_010;
|
1847 |
|
|
default: control_state<=6'b00_0000;//for safety
|
1848 |
|
|
endcase
|
1849 |
|
|
endcase
|
1850 |
|
|
`else//Priority Speed
|
1851 |
|
|
case (opecode)
|
1852 |
|
|
`jump: if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1853 |
|
|
else control_state<=6'b100_000;
|
1854 |
|
|
`jump_and_link_im: if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1855 |
|
|
else control_state<=6'b100_000;
|
1856 |
|
|
`beq : if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1857 |
|
|
else control_state<=6'b110_000;
|
1858 |
|
|
`bgtz : if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1859 |
|
|
else control_state<=6'b110_000;
|
1860 |
|
|
`blez : if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1861 |
|
|
else control_state<=6'b110_000;
|
1862 |
|
|
`bne : if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1863 |
|
|
else control_state<=6'b110_000;
|
1864 |
|
|
6'b000_001: if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1865 |
|
|
else control_state<=6'b110_000;//Jul.11.2004 Special Branch
|
1866 |
|
|
6'b00_0000:
|
1867 |
|
|
case (opefunc)
|
1868 |
|
|
`jump_and_link_register: if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1869 |
|
|
else control_state<=6'b101_000;
|
1870 |
|
|
`jmp_register : if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1871 |
|
|
else control_state<=6'b101_000;
|
1872 |
|
|
`mfhi: if (excuting_flag) begin
|
1873 |
|
|
if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1874 |
|
|
else control_state<=8'b00_000_010;
|
1875 |
|
|
end else if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1876 |
|
|
`mflo: if (excuting_flag) begin
|
1877 |
|
|
if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1878 |
|
|
else control_state<=8'b00_000_010;
|
1879 |
|
|
end else if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1880 |
|
|
|
1881 |
|
|
default: if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1882 |
|
|
else control_state<=6'b00_0000;//for safety
|
1883 |
|
|
endcase
|
1884 |
|
|
default : if (takenD3) control_state<=6'b001_100;//NOP1 state
|
1885 |
|
|
endcase
|
1886 |
|
|
|
1887 |
|
|
|
1888 |
|
|
`endif
|
1889 |
|
|
6'b???_010: case (control_state[7:6])
|
1890 |
|
|
2'b00: control_state<=8'b01_000_010;
|
1891 |
|
|
2'b01: if (!pause_out) control_state<=8'b11_000_010;//mul/div
|
1892 |
|
|
2'b11: control_state<=8'b10_000_010;
|
1893 |
|
|
2'b10: control_state<=8'b00_000_110;//NOP
|
1894 |
|
|
default: control_state<=8'h00;
|
1895 |
|
|
endcase
|
1896 |
|
|
6'b???_110: control_state<=8'h01;//Jul.12.2004 PCC=save_pc;
|
1897 |
|
|
6'b???_001: control_state<=8'h00; //Jul.12.2004 MUL IDLE avoid interrupt
|
1898 |
|
|
default: control_state<=8'h00;//for safety
|
1899 |
|
|
endcase
|
1900 |
|
|
end
|
1901 |
|
|
end
|
1902 |
|
|
|
1903 |
|
|
assign clear_int=control_state[2:0]==3'b101;//Jul.12.2004 interrupt_nop_state
|
1904 |
|
|
|
1905 |
|
|
always @(posedge clock) begin
|
1906 |
|
|
if (sync_reset) nop_bit<=1'b0;
|
1907 |
|
|
else if (6'b000_100==control_state[5:0] && !takenD3) nop_bit<=1'b0;//Not taken
|
1908 |
|
|
else nop_bit<=control_state[2];
|
1909 |
|
|
end
|
1910 |
|
|
assign NOP_Signal=nop_bit | control_state[1];//Jul.7.2004 int_bit mul_bit
|
1911 |
|
|
|
1912 |
|
|
|
1913 |
|
|
ram_module_altera
|
1914 |
|
|
|
1915 |
|
|
|
1916 |
|
|
|
1917 |
|
|
`ifdef RAM4K
|
1918 |
|
|
|
1919 |
|
|
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
|
1920 |
|
|
.Paddr(PC[11:0]),.Daddr(DAddress[11:0]),.wren(MWriteD2),
|
1921 |
|
|
.datain(memory_indata),.access_mode(M_access_modeD2),
|
1922 |
|
|
.M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
|
1923 |
|
|
`endif
|
1924 |
|
|
`ifdef RAM16K
|
1925 |
|
|
|
1926 |
|
|
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
|
1927 |
|
|
.Paddr(PC[13:0]),.Daddr(DAddress[13:0]),.wren(MWriteD2),
|
1928 |
|
|
.datain(memory_indata),.access_mode(M_access_modeD2),
|
1929 |
|
|
.M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
|
1930 |
|
|
|
1931 |
|
|
|
1932 |
|
|
|
1933 |
|
|
`endif
|
1934 |
|
|
|
1935 |
|
|
`ifdef RAM32K
|
1936 |
|
|
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
|
1937 |
|
|
.Paddr(PC[14:0]),.Daddr(DAddress[14:0]),.wren(MWriteD2),
|
1938 |
|
|
.datain(memory_indata),.access_mode(M_access_modeD2),
|
1939 |
|
|
.M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
|
1940 |
|
|
`endif
|
1941 |
|
|
|
1942 |
|
|
|
1943 |
|
|
|
1944 |
|
|
|
1945 |
|
|
endmodule</PRE>
|
1946 |
|
|
</TH>
|
1947 |
|
|
</TR>
|
1948 |
|
|
</TBODY>
|
1949 |
|
|
</TABLE>
|
1950 |
|
|
<P><B>2.2.6 PC module</B></P>
|
1951 |
|
|
<P>This module handles PC(program counter)</P>
|
1952 |
|
|
<TABLE border="1">
|
1953 |
|
|
<TBODY>
|
1954 |
|
|
<TR>
|
1955 |
|
|
<TH width="28" height="14" align="left">
|
1956 |
|
|
<PRE>//Jun.30.2004 NOP_DISABLE BUG FIX
|
1957 |
|
|
`include "define.h"
|
1958 |
|
|
module pc_module(clock,sync_reset,pc_commandD1,PCC,imm,ea_reg_source,takenD2,
|
1959 |
|
|
takenD3 ,branchQQ,jumpQ,NOP_Signal,control_state,IMMD1, PCCDD);
|
1960 |
|
|
input clock;
|
1961 |
|
|
input sync_reset;
|
1962 |
|
|
input [31:0] ea_reg_source;
|
1963 |
|
|
input [2:0] pc_commandD1;
|
1964 |
|
|
input takenD2;
|
1965 |
|
|
input [25:0] imm;
|
1966 |
|
|
input [25:0] IMMD1;
|
1967 |
|
|
`ifdef RAM4K
|
1968 |
|
|
output [11:0] PCC;
|
1969 |
|
|
`else
|
1970 |
|
|
output [25:0] PCC;
|
1971 |
|
|
`endif
|
1972 |
|
|
|
1973 |
|
|
|
1974 |
|
|
input takenD3;
|
1975 |
|
|
input branchQQ,jumpQ;
|
1976 |
|
|
input NOP_Signal;
|
1977 |
|
|
input [7:0] control_state;
|
1978 |
|
|
|
1979 |
|
|
reg [2:0] pc_commandD2,pc_commandD3;
|
1980 |
|
|
|
1981 |
|
|
`ifdef RAM4K
|
1982 |
|
|
reg [11:0] PC;
|
1983 |
|
|
reg [11:0] pcimm1D1,pcimm2D1;
|
1984 |
|
|
reg [15:0] immD1;//
|
1985 |
|
|
reg [11:0] pcimm1D2,pcimm2D2,pcimm2D3;
|
1986 |
|
|
reg [11:0] save_pc;
|
1987 |
|
|
wire [11:0] PCC;
|
1988 |
|
|
output [11:0] PCCDD;
|
1989 |
|
|
reg [11:0] PCCD,PCCDD;
|
1990 |
|
|
`else
|
1991 |
|
|
reg [25:0] PC;
|
1992 |
|
|
reg [25:0] pcimm1D1,pcimm2D1;
|
1993 |
|
|
reg [15:0] immD1;//
|
1994 |
|
|
reg [25:0] pcimm1D2,pcimm2D2,pcimm2D3;
|
1995 |
|
|
reg [25:0] save_pc;
|
1996 |
|
|
wire [25:0] PCC;
|
1997 |
|
|
output [25:0] PCCDD;
|
1998 |
|
|
reg [25:0] PCCD,PCCDD;
|
1999 |
|
|
|
2000 |
|
|
`endif
|
2001 |
|
|
|
2002 |
|
|
reg takenD4;
|
2003 |
|
|
reg branchQQQtakenD4;
|
2004 |
|
|
|
2005 |
|
|
|
2006 |
|
|
|
2007 |
|
|
//combination
|
2008 |
|
|
|
2009 |
|
|
always@(posedge clock) PCCD<=PCC;
|
2010 |
|
|
always@(posedge clock) PCCDD<=PCCD;
|
2011 |
|
|
|
2012 |
|
|
|
2013 |
|
|
always @(posedge clock) begin
|
2014 |
|
|
pc_commandD2 <=pc_commandD1;
|
2015 |
|
|
|
2016 |
|
|
end
|
2017 |
|
|
//
|
2018 |
|
|
always @(posedge clock) begin
|
2019 |
|
|
if (NOP_Signal) pc_commandD3<=3'b000;//Jun.30.2004
|
2020 |
|
|
else pc_commandD3 <=pc_commandD2;
|
2021 |
|
|
|
2022 |
|
|
end
|
2023 |
|
|
|
2024 |
|
|
always @(IMMD1 ) begin
|
2025 |
|
|
pcimm1D1={IMMD1,2'b00};//Jul.7.2004 {imm[23:0],2'b00};//+{PC[25:2],2'b00};
|
2026 |
|
|
|
2027 |
|
|
end
|
2028 |
|
|
|
2029 |
|
|
|
2030 |
|
|
`ifdef RAM4K
|
2031 |
|
|
always @(posedge clock) begin
|
2032 |
|
|
pcimm2D1<={PC[11:2],2'b00};
|
2033 |
|
|
end
|
2034 |
|
|
`else
|
2035 |
|
|
|
2036 |
|
|
always @(posedge clock) begin
|
2037 |
|
|
pcimm2D1<={PC[25:2],2'b00};
|
2038 |
|
|
end
|
2039 |
|
|
|
2040 |
|
|
`endif
|
2041 |
|
|
|
2042 |
|
|
always @(posedge clock) begin
|
2043 |
|
|
pcimm1D2<=pcimm1D1;
|
2044 |
|
|
|
2045 |
|
|
end
|
2046 |
|
|
|
2047 |
|
|
always @(posedge clock) begin
|
2048 |
|
|
|
2049 |
|
|
pcimm2D2<={{8 {immD1[15]}},immD1[15:0],2'b00}+pcimm2D1;//Jul.14.2004
|
2050 |
|
|
end
|
2051 |
|
|
always @(posedge clock) begin
|
2052 |
|
|
pcimm2D3<=pcimm2D2;
|
2053 |
|
|
end
|
2054 |
|
|
|
2055 |
|
|
|
2056 |
|
|
always @(posedge clock) begin
|
2057 |
|
|
immD1<=imm[15:0];//Jul.14.2004
|
2058 |
|
|
end
|
2059 |
|
|
|
2060 |
|
|
|
2061 |
|
|
always @(posedge clock) begin
|
2062 |
|
|
if (control_state==8'b00_000_010) save_pc<=PCCDD;
|
2063 |
|
|
end
|
2064 |
|
|
|
2065 |
|
|
|
2066 |
|
|
|
2067 |
|
|
|
2068 |
|
|
|
2069 |
|
|
always @(posedge clock) begin
|
2070 |
|
|
if (sync_reset) PC<=26'h0_00_0000_0000;
|
2071 |
|
|
|
2072 |
|
|
else if (branchQQQtakenD4) PC<=pcimm2D3+4;//NOP
|
2073 |
|
|
else if (jumpQ && !NOP_Signal) PC<=pcimm1D1+4;
|
2074 |
|
|
|
2075 |
|
|
else if (pc_commandD3==`PC_REG) PC<=ea_reg_source[25:0]+4;
|
2076 |
|
|
else if (control_state[2:0]==3'b110) PC<=save_pc+4;//mul/div
|
2077 |
|
|
else case(pc_commandD1)
|
2078 |
|
|
`PC_INC: PC<=PC+4;
|
2079 |
|
|
default: PC<=PC+4;
|
2080 |
|
|
endcase
|
2081 |
|
|
|
2082 |
|
|
|
2083 |
|
|
|
2084 |
|
|
end
|
2085 |
|
|
always @(posedge clock) begin
|
2086 |
|
|
if (sync_reset) takenD4<=1'b0;
|
2087 |
|
|
else takenD4<=takenD3;
|
2088 |
|
|
|
2089 |
|
|
end
|
2090 |
|
|
|
2091 |
|
|
always @(posedge clock) begin
|
2092 |
|
|
if (sync_reset) branchQQQtakenD4<=1'b0;
|
2093 |
|
|
else branchQQQtakenD4<=branchQQ && takenD3;
|
2094 |
|
|
end
|
2095 |
|
|
|
2096 |
|
|
assign PCC= branchQQQtakenD4 ? pcimm2D3 :
|
2097 |
|
|
jumpQ && !NOP_Signal ? pcimm1D1 :
|
2098 |
|
|
pc_commandD3==`PC_REG ? ea_reg_source[25:0] :
|
2099 |
|
|
control_state[2:0] ==3'b110 ? save_pc:PC;//Jun.27.2004
|
2100 |
|
|
|
2101 |
|
|
endmodule</PRE>
|
2102 |
|
|
</TH>
|
2103 |
|
|
</TR>
|
2104 |
|
|
</TBODY>
|
2105 |
|
|
</TABLE>
|
2106 |
|
|
<P><BR>
|
2107 |
|
|
<B>2.2.7 Pipelined Regfile</B> <BR>
|
2108 |
|
|
</P>
|
2109 |
|
|
<P>32bitsx32word Register is rather big for FPGA. Therefore I implemented
|
2110 |
|
|
by using 3port RAM(or 2port RAMx2).<BR>
|
2111 |
|
|
Data forwarding mechanism is must for pipelined processor.</P>
|
2112 |
|
|
<P><IMG src="pipelined_reg.gif" width="1091" height="767" border="0"></P>
|
2113 |
|
|
<TABLE border="1">
|
2114 |
|
|
<TBODY>
|
2115 |
|
|
<TR>
|
2116 |
|
|
<TH width="28" height="14" align="left">
|
2117 |
|
|
<PRE>//Jun.30.2004 Mux sentibity list bug fix
|
2118 |
|
|
//Jul.2.2004 Cleanup
|
2119 |
|
|
//Jul.7.2004 int bug fix
|
2120 |
|
|
//Jan.20.2005 apply @*
|
2121 |
|
|
`include "define.h"
|
2122 |
|
|
module Pipelined_RegFile(clock,sync_reset,
|
2123 |
|
|
dest_addrD2,source_addr,target_addr, wren,memory_wdata,
|
2124 |
|
|
A_Right_SELD1,A_Left_SELD1,PCD1,IMMD1,ALU_FuncD2,Shift_FuncD2,
|
2125 |
|
|
Shift_amountD2,RRegSelD1,MOUT,RF_inputD2,alu_source,alu_target,
|
2126 |
|
|
MWriteD2,MWriteD1,mul_alu_selD2,mul_div_funcD2,pause_out,
|
2127 |
|
|
Shift_Amount_selD2,int_stateD1,PCCDD
|
2128 |
|
|
);
|
2129 |
|
|
parameter adder_type="GENERIC";
|
2130 |
|
|
`ifdef RAM4K
|
2131 |
|
|
input [11:0] PCD1;
|
2132 |
|
|
`else
|
2133 |
|
|
input [25:0] PCD1;
|
2134 |
|
|
`endif
|
2135 |
|
|
input [15:0] IMMD1;//Jul.6.2004
|
2136 |
|
|
input [4:0] dest_addrD2;
|
2137 |
|
|
input [4:0] source_addr;
|
2138 |
|
|
input [4:0] target_addr;
|
2139 |
|
|
input wren;
|
2140 |
|
|
input clock;
|
2141 |
|
|
input A_Left_SELD1;
|
2142 |
|
|
input [3:0] ALU_FuncD2;
|
2143 |
|
|
input [4:0] Shift_amountD2;
|
2144 |
|
|
input [1:0] Shift_FuncD2;
|
2145 |
|
|
input [1:0] A_Right_SELD1;
|
2146 |
|
|
input sync_reset;
|
2147 |
|
|
input [1:0] RRegSelD1;
|
2148 |
|
|
output [31:0] alu_target,alu_source;
|
2149 |
|
|
output [31:0] memory_wdata;
|
2150 |
|
|
input [31:0] MOUT;
|
2151 |
|
|
input [1:0] RF_inputD2;
|
2152 |
|
|
input MWriteD2,MWriteD1;
|
2153 |
|
|
input [1:0] mul_alu_selD2;
|
2154 |
|
|
input [3:0] mul_div_funcD2;
|
2155 |
|
|
output pause_out;
|
2156 |
|
|
input Shift_Amount_selD2;
|
2157 |
|
|
input int_stateD1;
|
2158 |
|
|
|
2159 |
|
|
reg [31:0] AReg,NReg,RReg,DReg;
|
2160 |
|
|
reg [31:0] alu_left_latch,alu_right_latch;
|
2161 |
|
|
reg [31:0] memory_wdata;
|
2162 |
|
|
|
2163 |
|
|
`ifdef RAM4K
|
2164 |
|
|
input [11:0] PCCDD;
|
2165 |
|
|
reg [11:0] PCD2;
|
2166 |
|
|
`else
|
2167 |
|
|
input [25:0] PCCDD;
|
2168 |
|
|
reg [25:0] PCD2;
|
2169 |
|
|
`endif
|
2170 |
|
|
|
2171 |
|
|
reg [15:0] IMMD2;//Jul.6.2004
|
2172 |
|
|
|
2173 |
|
|
reg [4:0] dadrD3,dadrD4,dadrD5,dadrD6;
|
2174 |
|
|
reg [4:0] sadrD1,sadrD2;
|
2175 |
|
|
reg [4:0] tadrD1,tadrD2;
|
2176 |
|
|
reg WD3,WD4,WD5,WD6;
|
2177 |
|
|
reg [1:0] A_Right_SELD2;
|
2178 |
|
|
reg [1:0] RRegSelD2, RRegSelD3, RRegSelD4;
|
2179 |
|
|
reg [31:0] RRegin;
|
2180 |
|
|
reg test1D,test2D;
|
2181 |
|
|
wire [31:0] alu_right;
|
2182 |
|
|
reg [31:0] alu_left;
|
2183 |
|
|
|
2184 |
|
|
wire [31:0] source_out,target_out;
|
2185 |
|
|
wire [31:0] alu_out,shift_out;
|
2186 |
|
|
wire [31:0] alu_source=alu_left;
|
2187 |
|
|
wire [31:0] alu_target=alu_right;
|
2188 |
|
|
wire [31:0] regfile_in;
|
2189 |
|
|
wire [31:0] test,test2;
|
2190 |
|
|
wire test1;
|
2191 |
|
|
|
2192 |
|
|
reg stest1D,stest2D;
|
2193 |
|
|
reg stest1D_dup1,stest1D_dup2,stest1D_dup3,stest1D_dup4;
|
2194 |
|
|
reg [31:0] mul_alu_out;
|
2195 |
|
|
reg div_mode_ff;
|
2196 |
|
|
reg sign_ff;
|
2197 |
|
|
reg RRegSelD4_dup1,RRegSelD4_dup2,RRegSelD4_dup3;
|
2198 |
|
|
|
2199 |
|
|
|
2200 |
|
|
wire mul_div_enable,mul_div_sign,mul_div_mode;
|
2201 |
|
|
|
2202 |
|
|
wire [31:0] mul_div_out;
|
2203 |
|
|
wire [31:0] c_mult;
|
2204 |
|
|
wire [4:0] Shift_Amount;
|
2205 |
|
|
|
2206 |
|
|
localparam [4:0] zero_=0,
|
2207 |
|
|
at_=1,
|
2208 |
|
|
v0_=2,
|
2209 |
|
|
v1_=3,
|
2210 |
|
|
a0_=4,
|
2211 |
|
|
a1_=5,
|
2212 |
|
|
a2_=6,
|
2213 |
|
|
a3_=7,
|
2214 |
|
|
t0_=8, t1_=9,t2_=10,t3_=11,t4_=12,t5_=13,t6_=14,t7_=15,
|
2215 |
|
|
s0_=16,s1_=17,s2_=18,s3_=19,s4_=20,s5_=21,s6_=22,s7_=23,t8_=24,t9_=25,
|
2216 |
|
|
k0_=26,k1_=27,gp_=28,sp_=29,s8_=30,ra_=31;
|
2217 |
|
|
|
2218 |
|
|
|
2219 |
|
|
|
2220 |
|
|
|
2221 |
|
|
|
2222 |
|
|
always @(posedge clock) begin
|
2223 |
|
|
|
2224 |
|
|
dadrD3<=dest_addrD2;
|
2225 |
|
|
dadrD4<=dadrD3;
|
2226 |
|
|
dadrD5<=dadrD4;
|
2227 |
|
|
dadrD6<=dadrD5;
|
2228 |
|
|
|
2229 |
|
|
tadrD1<=target_addr;
|
2230 |
|
|
tadrD2<=tadrD1;
|
2231 |
|
|
|
2232 |
|
|
sadrD1<=source_addr;
|
2233 |
|
|
sadrD2<=sadrD1;
|
2234 |
|
|
|
2235 |
|
|
|
2236 |
|
|
if ( (mul_div_funcD2 ==4'b0000 ) ||
|
2237 |
|
|
(mul_div_funcD2 ==4'b0001 ) ||
|
2238 |
|
|
(mul_div_funcD2 ==4'b0010 ) ) WD3<=wren;//NOTHING,READLO/HI ˆÈŠO‚ł̓‰ƒCƒg‚ðŽ~‚ß‚é
|
2239 |
|
|
else WD3<=1'b0;
|
2240 |
|
|
|
2241 |
|
|
WD4<=WD3;
|
2242 |
|
|
WD5<=WD4;
|
2243 |
|
|
WD6<=WD5;
|
2244 |
|
|
|
2245 |
|
|
A_Right_SELD2<=A_Right_SELD1;
|
2246 |
|
|
|
2247 |
|
|
IMMD2<=IMMD1;
|
2248 |
|
|
if (int_stateD1) PCD2<=PCCDD;//Jul.7.2004
|
2249 |
|
|
else PCD2<=PCD1;
|
2250 |
|
|
|
2251 |
|
|
|
2252 |
|
|
RRegSelD2<=RRegSelD1;
|
2253 |
|
|
RRegSelD3<=RRegSelD2;
|
2254 |
|
|
RRegSelD4<=RRegSelD3;
|
2255 |
|
|
RRegSelD4_dup1<=RRegSelD3[0];
|
2256 |
|
|
RRegSelD4_dup2<=RRegSelD3[0];
|
2257 |
|
|
RRegSelD4_dup3<=RRegSelD3[0];
|
2258 |
|
|
|
2259 |
|
|
|
2260 |
|
|
end
|
2261 |
|
|
|
2262 |
|
|
|
2263 |
|
|
|
2264 |
|
|
//AReg
|
2265 |
|
|
always @(posedge clock) begin
|
2266 |
|
|
|
2267 |
|
|
case (RF_inputD2)
|
2268 |
|
|
`RF_ALU_sel : AReg<=alu_out;
|
2269 |
|
|
`RF_Shifter_sel: AReg<=shift_out;
|
2270 |
|
|
`SHIFT16_SEL: AReg<= {IMMD2[15:0],16'h00};
|
2271 |
|
|
`RF_PC_SEL : AReg<=mul_alu_out;
|
2272 |
|
|
endcase
|
2273 |
|
|
end
|
2274 |
|
|
|
2275 |
|
|
//ARegSel
|
2276 |
|
|
always @(*) begin//Mar.5.2005
|
2277 |
|
|
if (! mul_alu_selD2[1] ) mul_alu_out={6'b00_0000,PCD2};
|
2278 |
|
|
else mul_alu_out=c_mult;
|
2279 |
|
|
end
|
2280 |
|
|
|
2281 |
|
|
|
2282 |
|
|
|
2283 |
|
|
|
2284 |
|
|
//NReg
|
2285 |
|
|
always @(posedge clock) NReg<=AReg;
|
2286 |
|
|
|
2287 |
|
|
|
2288 |
|
|
//RReg
|
2289 |
|
|
always @(posedge clock) begin
|
2290 |
|
|
case (RRegSelD4_dup1)
|
2291 |
|
|
`MOUT_SEL : RReg<=MOUT;
|
2292 |
|
|
`NREG_SEL: RReg<=NReg;
|
2293 |
|
|
default : RReg<=MOUT;
|
2294 |
|
|
endcase
|
2295 |
|
|
end
|
2296 |
|
|
|
2297 |
|
|
//DReg
|
2298 |
|
|
always @(posedge clock) begin
|
2299 |
|
|
DReg<=RReg;
|
2300 |
|
|
end
|
2301 |
|
|
|
2302 |
|
|
|
2303 |
|
|
|
2304 |
|
|
|
2305 |
|
|
always @(*) begin
|
2306 |
|
|
case (RRegSelD4_dup2)
|
2307 |
|
|
`MOUT_SEL : RRegin=MOUT;
|
2308 |
|
|
`NREG_SEL: RRegin=NReg;
|
2309 |
|
|
default : RRegin=MOUT;
|
2310 |
|
|
endcase
|
2311 |
|
|
end
|
2312 |
|
|
//target_reg
|
2313 |
|
|
always @(*) memory_wdata=alu_right;
|
2314 |
|
|
|
2315 |
|
|
mul_div MulDiv(.clock(clock),.sync_reset(sync_reset),.a(alu_left),.b(alu_right),
|
2316 |
|
|
.mul_div_out(c_mult),.mul_div_sign(mul_div_funcD2[1]),
|
2317 |
|
|
.mul_div_word(1'b1),.mul_div_mode(mul_div_funcD2[2]),
|
2318 |
|
|
.stop_state(pause_out),.mul_div_enable(mul_div_funcD2[3]),.lohi(mul_div_funcD2[0]));
|
2319 |
|
|
|
2320 |
|
|
assign mul_div_enable= mul_div_funcD2;
|
2321 |
|
|
always @(posedge clock) begin
|
2322 |
|
|
if (sync_reset) div_mode_ff<=1'b0;
|
2323 |
|
|
else if (mul_div_enable) div_mode_ff<=mul_div_mode;
|
2324 |
|
|
end
|
2325 |
|
|
|
2326 |
|
|
always @(posedge clock) begin
|
2327 |
|
|
if (sync_reset) sign_ff<=1'b0;
|
2328 |
|
|
else if (mul_div_enable) sign_ff<=mul_div_sign;
|
2329 |
|
|
end
|
2330 |
|
|
|
2331 |
|
|
assign mul_div_mode=!(IMMD2[1] ==`MUL_DIV_MUL_SEL);//div high / mul low
|
2332 |
|
|
assign mul_div_sign=!IMMD2[0];
|
2333 |
|
|
|
2334 |
|
|
|
2335 |
|
|
|
2336 |
|
|
alu alu1(.a(alu_left),.b(alu_right),.alu_func(ALU_FuncD2),.alu_out(alu_out));
|
2337 |
|
|
|
2338 |
|
|
|
2339 |
|
|
|
2340 |
|
|
shifter sh1(.a(alu_right),.shift_out(shift_out),.shift_func(Shift_FuncD2),
|
2341 |
|
|
.shift_amount(Shift_Amount));
|
2342 |
|
|
|
2343 |
|
|
assign Shift_Amount=Shift_Amount_selD2==`SHIFT_AMOUNT_REG_SEL ?
|
2344 |
|
|
alu_left[4:0] : Shift_amountD2;
|
2345 |
|
|
|
2346 |
|
|
|
2347 |
|
|
//alu left latch
|
2348 |
|
|
always @(posedge clock) begin
|
2349 |
|
|
begin
|
2350 |
|
|
if (sadrD1==dadrD4 && WD4) alu_left_latch<=RRegin;
|
2351 |
|
|
//OK
|
2352 |
|
|
else if (sadrD1==dadrD5 && WD5) alu_left_latch<=RReg;//This must be priority encoder
|
2353 |
|
|
else if (sadrD1==dadrD6 && WD6) alu_left_latch<=DReg;
|
2354 |
|
|
else alu_left_latch<=source_out;
|
2355 |
|
|
end
|
2356 |
|
|
end
|
2357 |
|
|
|
2358 |
|
|
|
2359 |
|
|
//alu right latch
|
2360 |
|
|
always @(posedge clock) begin
|
2361 |
|
|
begin
|
2362 |
|
|
case (A_Right_SELD1)
|
2363 |
|
|
`Imm_signed : alu_right_latch<={ {16{IMMD1[15]}},IMMD1[15:0]};
|
2364 |
|
|
`Imm_unsigned : alu_right_latch<={ 16'h000,IMMD1[15:0]};
|
2365 |
|
|
`A_RIGHT_ERT : begin
|
2366 |
|
|
|
2367 |
|
|
if (tadrD1==dadrD4 && WD4 ) alu_right_latch<=RRegin;
|
2368 |
|
|
else //OK
|
2369 |
|
|
if (tadrD1==dadrD5 && WD5 ) alu_right_latch<=RReg;
|
2370 |
|
|
else if (tadrD1==dadrD6 && WD6) alu_right_latch<=DReg;
|
2371 |
|
|
else alu_right_latch<=target_out;
|
2372 |
|
|
end
|
2373 |
|
|
`IMM_26_SEL : begin
|
2374 |
|
|
alu_right_latch<={6'b00_0000,IMMD1};
|
2375 |
|
|
end
|
2376 |
|
|
default : alu_right_latch<={ {16{IMMD1[15]}},IMMD1[15:0]};
|
2377 |
|
|
endcase
|
2378 |
|
|
end
|
2379 |
|
|
end
|
2380 |
|
|
`ifdef ALTERA
|
2381 |
|
|
ram_regfile32xx32 RFile(
|
2382 |
|
|
.data(regfile_in),
|
2383 |
|
|
.wraddress(dadrD5),
|
2384 |
|
|
.rdaddress_a(target_addr),
|
2385 |
|
|
.rdaddress_b(source_addr),
|
2386 |
|
|
.wren(WD5),
|
2387 |
|
|
.clock(clock),
|
2388 |
|
|
.qa(target_out),
|
2389 |
|
|
.qb(source_out));
|
2390 |
|
|
`else
|
2391 |
|
|
|
2392 |
|
|
ram32x32_xilinx RFile (
|
2393 |
|
|
.data(regfile_in),
|
2394 |
|
|
.wraddress(dadrD5),
|
2395 |
|
|
.rdaddress_a(target_addr),
|
2396 |
|
|
.rdaddress_b(source_addr),
|
2397 |
|
|
.wren(WD5),
|
2398 |
|
|
.clock(clock),
|
2399 |
|
|
.qa(target_out),
|
2400 |
|
|
.qb(source_out));
|
2401 |
|
|
`endif
|
2402 |
|
|
assign regfile_in=dadrD5==5'b0_0000 ? 32'h0000_0000 :RReg;
|
2403 |
|
|
|
2404 |
|
|
|
2405 |
|
|
|
2406 |
|
|
|
2407 |
|
|
always @* begin //
|
2408 |
|
|
case (stest1D_dup1)
|
2409 |
|
|
1'b1: alu_left[7:0]=AReg[7:0];
|
2410 |
|
|
1'b0:
|
2411 |
|
|
case(stest2D)
|
2412 |
|
|
1'b1:
|
2413 |
|
|
case (RRegSelD4_dup3)
|
2414 |
|
|
`MOUT_SEL : alu_left[7:0]=MOUT[7:0];
|
2415 |
|
|
`NREG_SEL: alu_left[7:0]=NReg[7:0];
|
2416 |
|
|
endcase
|
2417 |
|
|
1'b0: alu_left[7:0]=alu_left_latch[7:0];
|
2418 |
|
|
endcase
|
2419 |
|
|
endcase
|
2420 |
|
|
end
|
2421 |
|
|
|
2422 |
|
|
always @* begin //
|
2423 |
|
|
case (stest1D_dup2)
|
2424 |
|
|
1'b1: alu_left[15:8]=AReg[15:8];
|
2425 |
|
|
1'b0:
|
2426 |
|
|
case(stest2D)
|
2427 |
|
|
1'b1:
|
2428 |
|
|
case (RRegSelD4_dup3)
|
2429 |
|
|
`MOUT_SEL : alu_left[15:8]=MOUT[15:8];
|
2430 |
|
|
`NREG_SEL: alu_left[15:8]=NReg[15:8];
|
2431 |
|
|
endcase
|
2432 |
|
|
1'b0: alu_left[15:8]=alu_left_latch[15:8];
|
2433 |
|
|
endcase
|
2434 |
|
|
endcase
|
2435 |
|
|
end
|
2436 |
|
|
|
2437 |
|
|
always @* begin//
|
2438 |
|
|
case (stest1D_dup3)
|
2439 |
|
|
1'b1: alu_left[23:16]=AReg[23:16];
|
2440 |
|
|
1'b0:
|
2441 |
|
|
case(stest2D)
|
2442 |
|
|
1'b1:
|
2443 |
|
|
case (RRegSelD4_dup3)
|
2444 |
|
|
`MOUT_SEL : alu_left[23:16]=MOUT[23:16];
|
2445 |
|
|
`NREG_SEL: alu_left[23:16]=NReg[23:16];
|
2446 |
|
|
endcase
|
2447 |
|
|
1'b0: alu_left[23:16]=alu_left_latch[23:16];
|
2448 |
|
|
endcase
|
2449 |
|
|
endcase
|
2450 |
|
|
end
|
2451 |
|
|
|
2452 |
|
|
always @* begin //
|
2453 |
|
|
case (stest1D_dup4)
|
2454 |
|
|
1'b1: alu_left[31:24]=AReg[31:24];
|
2455 |
|
|
1'b0:
|
2456 |
|
|
case(stest2D)
|
2457 |
|
|
1'b1:
|
2458 |
|
|
case (RRegSelD4_dup3)
|
2459 |
|
|
`MOUT_SEL : alu_left[31:24]=MOUT[31:24];
|
2460 |
|
|
`NREG_SEL: alu_left[31:24]=NReg[31:24];
|
2461 |
|
|
endcase
|
2462 |
|
|
1'b0: alu_left[31:24]=alu_left_latch[31:24];
|
2463 |
|
|
endcase
|
2464 |
|
|
endcase
|
2465 |
|
|
end
|
2466 |
|
|
|
2467 |
|
|
|
2468 |
|
|
|
2469 |
|
|
|
2470 |
|
|
assign alu_right=test1D ? AReg :
|
2471 |
|
|
test2D ? RRegin : alu_right_latch;
|
2472 |
|
|
|
2473 |
|
|
always @(posedge clock) begin
|
2474 |
|
|
stest1D<=(sadrD1==dest_addrD2) && wren;
|
2475 |
|
|
stest1D_dup1<=(sadrD1==dest_addrD2) && wren;
|
2476 |
|
|
stest1D_dup2<=(sadrD1==dest_addrD2) && wren;
|
2477 |
|
|
stest1D_dup3<=(sadrD1==dest_addrD2) && wren;
|
2478 |
|
|
stest1D_dup4<=(sadrD1==dest_addrD2) && wren;
|
2479 |
|
|
|
2480 |
|
|
end
|
2481 |
|
|
always @(posedge clock) begin
|
2482 |
|
|
stest2D<=(sadrD1==dadrD3) && WD3 ;
|
2483 |
|
|
end
|
2484 |
|
|
|
2485 |
|
|
|
2486 |
|
|
|
2487 |
|
|
|
2488 |
|
|
always @(posedge clock) begin
|
2489 |
|
|
test1D<=tadrD1==dest_addrD2 && (wren ) && A_Right_SELD1==`A_RIGHT_ERT;
|
2490 |
|
|
end
|
2491 |
|
|
|
2492 |
|
|
always @(posedge clock) begin
|
2493 |
|
|
test2D<=tadrD1==dadrD3 && (WD3 ) && A_Right_SELD1==`A_RIGHT_ERT;
|
2494 |
|
|
end
|
2495 |
|
|
|
2496 |
|
|
|
2497 |
|
|
`ifdef Veritak
|
2498 |
|
|
reg [30*8:1] alu_function;
|
2499 |
|
|
reg [30*8:1] shift_function;
|
2500 |
|
|
reg [30*8:1] AReg_Input_Sel;
|
2501 |
|
|
|
2502 |
|
|
always @*//Jan.20.2005 @(ALU_FuncD2,alu_left,alu_right)
|
2503 |
|
|
case (ALU_FuncD2)
|
2504 |
|
|
`ALU_NOTHING : $sprintf(alu_function,"non_operation");
|
2505 |
|
|
`ALU_ADD : $sprintf(alu_function,"ADD %h,%h",alu_left,alu_right);
|
2506 |
|
|
`ALU_SUBTRACT :$sprintf(alu_function,"SUB %h,%h,alu_left,alu_right");
|
2507 |
|
|
`ALU_LESS_THAN_UNSIGNED :$sprintf(alu_function ,"LT_Unsigned %h,%h",alu_left,alu_right);
|
2508 |
|
|
`ALU_LESS_THAN_SIGNED : $sprintf(alu_function,"LT_Signed %h,%h",alu_left,alu_right);
|
2509 |
|
|
`ALU_OR : $sprintf(alu_function,"OR %h,%h",alu_left,alu_right);
|
2510 |
|
|
`ALU_AND : $sprintf(alu_function,"XOR %h,%h,alu_left,alu_right");
|
2511 |
|
|
`ALU_XOR : $sprintf(alu_function,"AND %h,%h",alu_left,alu_right);
|
2512 |
|
|
`ALU_NOR : $sprintf(alu_function,"NOR %h,%h",alu_left,alu_right);
|
2513 |
|
|
default: $sprintf(alu_function,"non_operation");
|
2514 |
|
|
endcase
|
2515 |
|
|
|
2516 |
|
|
always @* begin //
|
2517 |
|
|
case (Shift_FuncD2)
|
2518 |
|
|
`SHIFT_LEFT : $sprintf(shift_function,"SLL %d",Shift_Amount);
|
2519 |
|
|
`SHIFT_RIGHT_UNSIGNED : $sprintf(shift_function,"SLR %d",Shift_Amount);
|
2520 |
|
|
`SHIFT_RIGHT_SIGNED : $sprintf(shift_function,"SAR %d",Shift_Amount);
|
2521 |
|
|
default: $sprintf(shift_function,"non_operation");
|
2522 |
|
|
endcase
|
2523 |
|
|
end
|
2524 |
|
|
|
2525 |
|
|
|
2526 |
|
|
always @* begin //
|
2527 |
|
|
case (RF_inputD2)
|
2528 |
|
|
`RF_ALU_sel : $sprintf(AReg_Input_Sel,"ALU");
|
2529 |
|
|
`RF_Shifter_sel: $sprintf(AReg_Input_Sel,"Shifter");
|
2530 |
|
|
`SHIFT16_SEL: $sprintf(AReg_Input_Sel,"IMM16<<16");
|
2531 |
|
|
`RF_PC_SEL : $sprintf(AReg_Input_Sel,"PC/MulOutSEL");
|
2532 |
|
|
endcase
|
2533 |
|
|
end
|
2534 |
|
|
|
2535 |
|
|
|
2536 |
|
|
`endif
|
2537 |
|
|
|
2538 |
|
|
|
2539 |
|
|
|
2540 |
|
|
|
2541 |
|
|
endmodule</PRE>
|
2542 |
|
|
</TH>
|
2543 |
|
|
</TR>
|
2544 |
|
|
</TBODY>
|
2545 |
|
|
</TABLE>
|
2546 |
|
|
<P><B>2.2.8 UART Write Port</B> <BR>
|
2547 |
|
|
<BR>
|
2548 |
|
|
With 512 Bytes FIFO Uart Write Port.115.2KBPS in 50MHz System Clock.</P>
|
2549 |
|
|
<TABLE border="1">
|
2550 |
|
|
<TBODY>
|
2551 |
|
|
<TR>
|
2552 |
|
|
<TH width="28" height="14" align="left">
|
2553 |
|
|
<PRE>`include "define.h"
|
2554 |
|
|
//Apr.5.2005 Tak.Sugawara
|
2555 |
|
|
//Jul.14.2004
|
2556 |
|
|
|
2557 |
|
|
|
2558 |
|
|
module uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
|
2559 |
|
|
input sync_reset,clk;
|
2560 |
|
|
input [7:0] data_in;
|
2561 |
|
|
input write_request;
|
2562 |
|
|
output txd,write_done;
|
2563 |
|
|
output write_busy;
|
2564 |
|
|
|
2565 |
|
|
|
2566 |
|
|
|
2567 |
|
|
wire queue_full;
|
2568 |
|
|
wire queing, read_request;
|
2569 |
|
|
wire [7:0] queue_data;
|
2570 |
|
|
reg read_request_ff;
|
2571 |
|
|
|
2572 |
|
|
|
2573 |
|
|
//________|--|___write_request (upper module : its period should be 1clock time.)
|
2574 |
|
|
//__________________________|-|______write_done (Responds by this module posedge interrupt)
|
2575 |
|
|
//With 512Bytes FIFO.
|
2576 |
|
|
//No error handling is supported.
|
2577 |
|
|
|
2578 |
|
|
reg [8:0] clk_ctr;
|
2579 |
|
|
reg [2:0] bit_ctr;
|
2580 |
|
|
reg [2:0] ua_state;
|
2581 |
|
|
reg [7:0] tx_sr;
|
2582 |
|
|
reg write_done_n;
|
2583 |
|
|
reg txd;
|
2584 |
|
|
|
2585 |
|
|
wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
|
2586 |
|
|
clk_ctr_enable_state, bit_ctr_enable_state ;
|
2587 |
|
|
wire tx_state;
|
2588 |
|
|
wire empty;
|
2589 |
|
|
assign write_busy=queue_full;//Apr.2.2005
|
2590 |
|
|
|
2591 |
|
|
always @ (posedge clk) begin
|
2592 |
|
|
if (sync_reset) read_request_ff<=1'b0;
|
2593 |
|
|
else read_request_ff<=read_request;
|
2594 |
|
|
end
|
2595 |
|
|
|
2596 |
|
|
assign queing= !empty;
|
2597 |
|
|
assign read_request = queing && ua_state==3'b000;//Jul.14.2004
|
2598 |
|
|
|
2599 |
|
|
assign write_done=ua_state==3'b101;
|
2600 |
|
|
|
2601 |
|
|
`ifdef ALTERA
|
2602 |
|
|
fifo512_cyclone fifo(
|
2603 |
|
|
.data(data_in),
|
2604 |
|
|
.wrreq(write_request),
|
2605 |
|
|
.rdreq(read_request),
|
2606 |
|
|
.clock(clk),
|
2607 |
|
|
.q(queue_data),
|
2608 |
|
|
.full(queue_full),
|
2609 |
|
|
.empty(empty));
|
2610 |
|
|
`else//XILINX coregen
|
2611 |
|
|
|
2612 |
|
|
fifo fifo(
|
2613 |
|
|
.clk(clk),
|
2614 |
|
|
.sinit(sync_reset),
|
2615 |
|
|
.din(data_in),
|
2616 |
|
|
.wr_en(write_request),
|
2617 |
|
|
.rd_en(read_request),
|
2618 |
|
|
.dout(queue_data),
|
2619 |
|
|
.full(queue_full),
|
2620 |
|
|
.empty(empty));
|
2621 |
|
|
|
2622 |
|
|
|
2623 |
|
|
`endif
|
2624 |
|
|
|
2625 |
|
|
|
2626 |
|
|
|
2627 |
|
|
// 7bit counter
|
2628 |
|
|
always @(posedge clk ) begin
|
2629 |
|
|
if (sync_reset)
|
2630 |
|
|
clk_ctr <= 0;
|
2631 |
|
|
else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
|
2632 |
|
|
else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
|
2633 |
|
|
else clk_ctr <= 0;
|
2634 |
|
|
end
|
2635 |
|
|
|
2636 |
|
|
|
2637 |
|
|
assign clk_ctr_equ15 = clk_ctr==`COUNTER_VALUE1;
|
2638 |
|
|
assign clk_ctr_equ31 = clk_ctr==`COUNTER_VALUE2;
|
2639 |
|
|
|
2640 |
|
|
// 3bit counter
|
2641 |
|
|
always @(posedge clk) begin
|
2642 |
|
|
if (sync_reset)
|
2643 |
|
|
bit_ctr <= 0;
|
2644 |
|
|
else if (bit_ctr_enable_state) begin
|
2645 |
|
|
if (clk_ctr_equ15)
|
2646 |
|
|
bit_ctr <= bit_ctr + 1;
|
2647 |
|
|
end
|
2648 |
|
|
else
|
2649 |
|
|
bit_ctr <= 0;
|
2650 |
|
|
end
|
2651 |
|
|
|
2652 |
|
|
assign bit_ctr_equ7 = (bit_ctr==7);
|
2653 |
|
|
|
2654 |
|
|
|
2655 |
|
|
|
2656 |
|
|
assign clk_ctr_enable_state = bit_ctr_enable_state || ua_state==3'b001 || ua_state==3'b100 ;
|
2657 |
|
|
assign bit_ctr_enable_state = ua_state==3'b010 || ua_state==3'b011;
|
2658 |
|
|
|
2659 |
|
|
|
2660 |
|
|
always @(posedge clk ) begin
|
2661 |
|
|
if (sync_reset) ua_state <= 3'b000;
|
2662 |
|
|
else begin
|
2663 |
|
|
case (ua_state)
|
2664 |
|
|
3'b000: if (queing) ua_state <= 3'b001; //wait write_request
|
2665 |
|
|
3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; // write start bit
|
2666 |
|
|
3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011; // start bit, bit0-7 data send
|
2667 |
|
|
3'b011: if (clk_ctr_equ15) ua_state <= 3'b100; // bit7 data send
|
2668 |
|
|
3'b100: if (clk_ctr_equ15) ua_state <= 3'b101; // stop bit // stop bit send
|
2669 |
|
|
3'b101: ua_state <= 3'h0; // TAK // byte read cycle end
|
2670 |
|
|
default: ua_state <= 3'h0;
|
2671 |
|
|
endcase
|
2672 |
|
|
end
|
2673 |
|
|
end
|
2674 |
|
|
|
2675 |
|
|
|
2676 |
|
|
|
2677 |
|
|
|
2678 |
|
|
|
2679 |
|
|
|
2680 |
|
|
|
2681 |
|
|
|
2682 |
|
|
|
2683 |
|
|
|
2684 |
|
|
|
2685 |
|
|
|
2686 |
|
|
// tx shift reg.
|
2687 |
|
|
always @(posedge clk ) begin
|
2688 |
|
|
if (sync_reset) tx_sr<=0;
|
2689 |
|
|
else if (read_request_ff) tx_sr <= queue_data[7:0]; //data_in[7:0]; // load
|
2690 |
|
|
else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
|
2691 |
|
|
end
|
2692 |
|
|
|
2693 |
|
|
assign tx_state=( ua_state==3'h2 || ua_state==3'h3) && clk_ctr_equ15;
|
2694 |
|
|
|
2695 |
|
|
|
2696 |
|
|
// tx
|
2697 |
|
|
always @(posedge clk ) begin
|
2698 |
|
|
if (sync_reset) txd <=1'b1;
|
2699 |
|
|
else if (sync_reset) txd<=1'b1;
|
2700 |
|
|
else if (ua_state==3'h0) txd<=1'b1;
|
2701 |
|
|
else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0; // start bit
|
2702 |
|
|
else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
|
2703 |
|
|
else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1; // stop bit
|
2704 |
|
|
end
|
2705 |
|
|
endmodule
|
2706 |
|
|
</PRE>
|
2707 |
|
|
</TH>
|
2708 |
|
|
</TR>
|
2709 |
|
|
</TBODY>
|
2710 |
|
|
</TABLE>
|
2711 |
|
|
<P><BR>
|
2712 |
|
|
<B>2.2.9 UART READ PORT</B><BR>
|
2713 |
|
|
<BR>
|
2714 |
|
|
Host must service within 1-byte time because of no fifo.</P>
|
2715 |
|
|
<TABLE border="1">
|
2716 |
|
|
<TBODY>
|
2717 |
|
|
<TR>
|
2718 |
|
|
<TH width="28" height="14" align="left">
|
2719 |
|
|
<PRE>`include "define.h"
|
2720 |
|
|
|
2721 |
|
|
|
2722 |
|
|
|
2723 |
|
|
|
2724 |
|
|
|
2725 |
|
|
module uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
|
2726 |
|
|
input sync_reset;
|
2727 |
|
|
input clk, rxd;
|
2728 |
|
|
output [7:0] buffer_reg;
|
2729 |
|
|
output int_req;
|
2730 |
|
|
|
2731 |
|
|
|
2732 |
|
|
//________|-|______int_req (This module,, posedge interrupt)
|
2733 |
|
|
//
|
2734 |
|
|
//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...
|
2735 |
|
|
//
|
2736 |
|
|
//No error handling (overrun ) is supported.
|
2737 |
|
|
|
2738 |
|
|
reg rxq1;
|
2739 |
|
|
reg [8:0] clk_ctr;
|
2740 |
|
|
reg [2:0] bit_ctr;
|
2741 |
|
|
reg [2:0] ua_state;
|
2742 |
|
|
reg [7:0] rx_sr; //.,tx_sr;
|
2743 |
|
|
reg int_req;
|
2744 |
|
|
reg [7:0] buffer_reg;
|
2745 |
|
|
|
2746 |
|
|
wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
|
2747 |
|
|
clk_ctr_enable_state, bit_ctr_enable_state ;
|
2748 |
|
|
wire clk_ctr_equ0;
|
2749 |
|
|
|
2750 |
|
|
|
2751 |
|
|
|
2752 |
|
|
|
2753 |
|
|
//sync_reset
|
2754 |
|
|
|
2755 |
|
|
//synchronization
|
2756 |
|
|
always @(posedge clk ) begin
|
2757 |
|
|
rxq1 <=rxd ;
|
2758 |
|
|
end
|
2759 |
|
|
|
2760 |
|
|
// 7bit counter
|
2761 |
|
|
always @(posedge clk ) begin
|
2762 |
|
|
if (sync_reset)
|
2763 |
|
|
clk_ctr <= 0;
|
2764 |
|
|
else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;
|
2765 |
|
|
else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;
|
2766 |
|
|
else clk_ctr <= 0;
|
2767 |
|
|
end
|
2768 |
|
|
assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;//
|
2769 |
|
|
assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;//
|
2770 |
|
|
assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
|
2771 |
|
|
|
2772 |
|
|
|
2773 |
|
|
// 3bit counter
|
2774 |
|
|
always @(posedge clk) begin
|
2775 |
|
|
if (sync_reset)
|
2776 |
|
|
bit_ctr <= 0;
|
2777 |
|
|
else if (bit_ctr_enable_state) begin
|
2778 |
|
|
if (clk_ctr_equ15)
|
2779 |
|
|
bit_ctr <= bit_ctr + 1;
|
2780 |
|
|
end
|
2781 |
|
|
else
|
2782 |
|
|
bit_ctr <= 0;
|
2783 |
|
|
end
|
2784 |
|
|
|
2785 |
|
|
assign bit_ctr_equ7 = (bit_ctr==7);
|
2786 |
|
|
|
2787 |
|
|
|
2788 |
|
|
assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;
|
2789 |
|
|
assign bit_ctr_enable_state = ua_state==3'h2;
|
2790 |
|
|
|
2791 |
|
|
//
|
2792 |
|
|
always @(posedge clk ) begin
|
2793 |
|
|
if (sync_reset) ua_state <= 3'h0;
|
2794 |
|
|
else begin
|
2795 |
|
|
case (ua_state)
|
2796 |
|
|
3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search
|
2797 |
|
|
3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive
|
2798 |
|
|
3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
|
2799 |
|
|
3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive
|
2800 |
|
|
3'h4: ua_state <= 3'b000;
|
2801 |
|
|
default: ua_state <= 3'b000;
|
2802 |
|
|
endcase
|
2803 |
|
|
end
|
2804 |
|
|
end
|
2805 |
|
|
|
2806 |
|
|
|
2807 |
|
|
//reg_we
|
2808 |
|
|
always @(posedge clk ) begin
|
2809 |
|
|
if (sync_reset) buffer_reg<=8'h00;
|
2810 |
|
|
else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;
|
2811 |
|
|
end
|
2812 |
|
|
|
2813 |
|
|
//int_req
|
2814 |
|
|
always @(posedge clk ) begin
|
2815 |
|
|
if (sync_reset) int_req<=1'b0;
|
2816 |
|
|
else if (ua_state==3'h4 ) int_req<=1'b1; //
|
2817 |
|
|
else int_req<=1'b0;
|
2818 |
|
|
end
|
2819 |
|
|
|
2820 |
|
|
|
2821 |
|
|
// rx shift reg.
|
2822 |
|
|
always @(posedge clk ) begin
|
2823 |
|
|
if (sync_reset) rx_sr <= 0;
|
2824 |
|
|
else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
|
2825 |
|
|
end
|
2826 |
|
|
|
2827 |
|
|
endmodule</PRE>
|
2828 |
|
|
</TH>
|
2829 |
|
|
</TR>
|
2830 |
|
|
</TBODY>
|
2831 |
|
|
</TABLE>
|
2832 |
|
|
</BODY>
|
2833 |
|
|
</HTML>
|