URL https://opencores.org/ocsvn/yacc/yacc/trunk

Subversion Repositories yacc

[/] [yacc/] [trunk/] [bench/] [verilog/] [yacc_test2.v] - Blame information for rev 4

Details | Compare with Previous | View Log


//YACC Test Bench
//Apr.5.2005 Tak.Sugawara
 
`include "define.h"
`timescale 1ns/1ps
 
module yacc_test;
        reg clock=0;
        reg Reset=0;
        reg int_req_usr=0;
        reg RXD=1'b1;
        wire TXD;
        wire [31:0] mem_data_w;
        wire mem_write;
        wire [15:0] mem_address;
        always #20 clock=~clock;
 
 
 
        initial begin
                Reset=0;
                #800 Reset=1;
        end
 
`ifdef RTL_SIMULATION
 yacc cpu(.clock(clock),.Async_Reset(Reset),.MemoryWData(mem_data_w),
                  .MWriteFF(mem_write),
                  .data_port_address(mem_address),.RXD(RXD),.TXD(TXD));
`else
        yacc cpu(.clock(clock),.Async_Reset(Reset),        .RXD(RXD),.TXD(TXD));
 
`endif
 
 
 
 
 
 
 
 
        task Cprint;// String OUT until the byte 00 or xx detected with least Byte first and justified.
                integer i;
                begin :Block
                        i=0;
                        while (1) begin
                                if (char_buffer[i*8 +:8] ===8'h00 || char_buffer[i*8 +:8]===8'hxx) begin
                                                disable Block;
                                end
                                $write("%c",char_buffer[i*8 +:8]);
                                i=i+1;
                        end
                end
        endtask
 
   reg [0:640*2-1] char_buffer;
   integer  counter=0;
   always @ (posedge clock ) begin
            if ((mem_write === 1'b1)) begin
                   if (mem_address==`Print_Port_Address) begin
                                if (mem_data_w[7:0]===8'h00) begin
                                        char_buffer[counter*8 +:8]=mem_data_w[7:0];
                                        if (char_buffer[0  +:8*7]==="$finish") begin
                                                        $stop;
 
                                        end else if (char_buffer[0  +:8*5]==="$time") begin
                                                        $display("Current Time on Simulation=%d",$time);
 
                                        end else  Cprint;//$write("%s",char_buffer);
 
                                        for (counter=0; counter< 80*2; counter=counter+1) begin
                                                char_buffer[counter*8 +:8]=8'h00;
                                        end
                                        counter=0;
 
                                end else begin
                                        char_buffer[counter*8 +:8]=mem_data_w[7:0];
                                        counter=counter+1;
                                end
                   end
           else if (mem_address==`Print_CAHR_Port_Address) begin
                                $write("%h ",mem_data_w[7:0]);
                   end else if (mem_address==`Print_INT_Port_Address) begin
                                $write("%h ",mem_data_w[15:0]);//Little Endian 
                   end else if (mem_address==`Print_LONG_Port_Address) begin
                                $write("%h ",mem_data_w[31:0]);//Big Endian
                   end
        end //if
   end //always
 
 
//uart read port
  wire [7:0] buffer_reg;
  wire int_req;
  reg sync_reset;
 
  localparam LF=8'h0a;
        always @(posedge clock, negedge Reset) begin
                if (!Reset) sync_reset <=1'b1;
                else sync_reset<=1'b0;
        end
 
 
 
   uart_read   uart_read_port( .sync_reset(sync_reset), .clk(clock), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));
 
        always @(posedge int_req) begin
                begin :local
 
                        reg [7:0] local_mem [0:1000];
                        integer i=0;
 
                        if (i>=1000) $stop;//assert(0);
 
                        if (buffer_reg==LF) begin :local2 //pop stack
                                integer j;
                                j=0;
                                while( j < i) begin
                                        $write( "%c",local_mem[j]);
                                        j=j+1;
                                end
                                $write("     : time=%t\n",$time);
                                i=0;//clear stack        
                        end else begin//push stack
 
                                local_mem[i]=buffer_reg;
                                i=i+1;
                         end
                end
 
        end
endmodule
 

Line No.	Rev	Author	Line
1	2	tak.sugawa	`//YACC Test Bench`
2			`//Apr.5.2005 Tak.Sugawara`
3
4			`include "define.h"
5			`timescale 1ns/1ps
6
7			`module yacc_test;`
8			`reg clock=0;`
9			`reg Reset=0;`
10			`reg int_req_usr=0;`
11			`reg RXD=1'b1;`
12			`wire TXD;`
13			`wire [31:0] mem_data_w;`
14			`wire mem_write;`
15			`wire [15:0] mem_address;`
16			`always #20 clock=~clock;`
17
18
19
20			`initial begin`
21			`Reset=0;`
22			`#800 Reset=1;`
23			`end`
24
25			`ifdef RTL_SIMULATION
26			`yacc cpu(.clock(clock),.Async_Reset(Reset),.MemoryWData(mem_data_w),`
27			`.MWriteFF(mem_write),`
28			`.data_port_address(mem_address),.RXD(RXD),.TXD(TXD));`
29			`else
30			`yacc cpu(.clock(clock),.Async_Reset(Reset), .RXD(RXD),.TXD(TXD));`
31
32			`endif
33
34
35
36
37
38
39
40
41			`task Cprint;// String OUT until the byte 00 or xx detected with least Byte first and justified.`
42			`integer i;`
43			`begin :Block`
44			`i=0;`
45			`while (1) begin`
46			`if (char_buffer[i8 +:8] ===8'h00 \|\| char_buffer[i8 +:8]===8'hxx) begin`
47			`disable Block;`
48			`end`
49			`$write("%c",char_buffer[i*8 +:8]);`
50			`i=i+1;`
51			`end`
52			`end`
53			`endtask`
54
55			`reg [0:640*2-1] char_buffer;`
56			`integer counter=0;`
57			`always @ (posedge clock ) begin`
58			`if ((mem_write === 1'b1)) begin`
59			if (mem_address==`Print_Port_Address) begin
60			`if (mem_data_w[7:0]===8'h00) begin`
61			`char_buffer[counter*8 +:8]=mem_data_w[7:0];`
62			`if (char_buffer[0 +:8*7]==="$finish") begin`
63			`$stop;`
64
65			`end else if (char_buffer[0 +:8*5]==="$time") begin`
66			`$display("Current Time on Simulation=%d",$time);`
67
68			`end else Cprint;//$write("%s",char_buffer);`
69
70			`for (counter=0; counter< 80*2; counter=counter+1) begin`
71			`char_buffer[counter*8 +:8]=8'h00;`
72			`end`
73			`counter=0;`
74
75			`end else begin`
76			`char_buffer[counter*8 +:8]=mem_data_w[7:0];`
77			`counter=counter+1;`
78			`end`
79			`end`
80			else if (mem_address==`Print_CAHR_Port_Address) begin
81			`$write("%h ",mem_data_w[7:0]);`
82			end else if (mem_address==`Print_INT_Port_Address) begin
83			`$write("%h ",mem_data_w[15:0]);//Little Endian`
84			end else if (mem_address==`Print_LONG_Port_Address) begin
85			`$write("%h ",mem_data_w[31:0]);//Big Endian`
86			`end`
87			`end //if`
88			`end //always`
89
90
91			`//uart read port`
92			`wire [7:0] buffer_reg;`
93			`wire int_req;`
94			`reg sync_reset;`
95
96			`localparam LF=8'h0a;`
97			`always @(posedge clock, negedge Reset) begin`
98			`if (!Reset) sync_reset <=1'b1;`
99			`else sync_reset<=1'b0;`
100			`end`
101
102
103
104			`uart_read uart_read_port( .sync_reset(sync_reset), .clk(clock), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));`
105
106			`always @(posedge int_req) begin`
107			`begin :local`
108
109			`reg [7:0] local_mem [0:1000];`
110			`integer i=0;`
111
112			`if (i>=1000) $stop;//assert(0);`
113
114			`if (buffer_reg==LF) begin :local2 //pop stack`
115			`integer j;`
116			`j=0;`
117			`while( j < i) begin`
118			`$write( "%c",local_mem[j]);`
119			`j=j+1;`
120			`end`
121			`$write(" : time=%t\n",$time);`
122			`i=0;//clear stack`
123			`end else begin//push stack`
124
125			`local_mem[i]=buffer_reg;`
126			`i=i+1;`
127			`end`
128			`end`
129
130			`end`
131			`endmodule`
132

Browse

Tools

Subversion Repositories yacc

[/] [yacc/] [trunk/] [bench/] [verilog/] [yacc_test2.v] - Blame information for rev 4