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<P><B>4 Benchmark Test</B><BR>
<BR>
This test was using RTL simulation bench. When C program calls &nbsp;print(&quot;$time&quot;),
test bench in verilog prints $time.So call at start and finish of dhrystone
benchmark program. By using this technique you can measure exact clock
time for execution of benchmark program.<BR>
<BR>
</P>
<P>print &quot;C&quot; program</P>
<TABLE border="1">
  <TBODY>
    <TR>
      <TH align="left">
      <PRE>void print(unsigned char* ptr)//Verilog Test Bench Use
{
        #ifdef DOS
                        printf(&quot;%s &quot;,ptr);
        #else
 
        while (*ptr) {
 
                *(volatile unsigned char*)print_port=*(ptr++);
        }
 
        *(volatile unsigned char*)print_port=0x00;//Write Done
        #endif
}
</PRE>
      </TH>
    </TR>
  </TBODY>
</TABLE>
<P><BR>
Test bench in Verilog HDL</P>
<TABLE border="1">
  <TBODY>
    <TR>
      <TH align="left">
      <PRE>//YACC Test Bench
//Apr.5.2005 Tak.Sugawara
 
`include &quot;define.h&quot;
`timescale 1ns/1ps
 
module yacc_test;
        reg clock=0;
        reg Reset=0;
        reg int_req_usr=0;
        reg RXD=1'b1;
        wire TXD;
        wire [31:0] mem_data_w;
        wire mem_write;
        wire [15:0] mem_address;
        always #20 clock=~clock;
 
 
 
        initial begin
                Reset=0;
                #800 Reset=1;
        end
 
`ifdef RTL_SIMULATION
 yacc cpu(.clock(clock),.Async_Reset(Reset),.MemoryWData(mem_data_w),
                  .MWriteFF(mem_write),
                  .data_port_address(mem_address),.RXD(RXD),.TXD(TXD));
`else
        yacc cpu(.clock(clock),.Async_Reset(Reset),        .RXD(RXD),.TXD(TXD));
 
`endif
 
 
 
 
 
 
 
 
        task Cprint;// String OUT until the byte 00 or xx detected with least Byte first and justified.
                integer i;
                begin :Block
                        i=0;
                        while (1) begin
                                if (char_buffer[i*8 +:8] ===8'h00 || char_buffer[i*8 +:8]===8'hxx) begin
                                                disable Block;
                                end
                                $write(&quot;%c&quot;,char_buffer[i*8 +:8]);
                                i=i+1;
                        end
                end
        endtask
 
   reg [0:640*2-1] char_buffer;
   integer  counter=0;
   always @ (posedge clock ) begin
            if ((mem_write === 1'b1)) begin
                   if (mem_address==`Print_Port_Address) begin
                                if (mem_data_w[7:0]===8'h00) begin
                                        char_buffer[counter*8 +:8]=mem_data_w[7:0];
                                        if (char_buffer[0  +:8*7]===&quot;$finish&quot;) begin
                                                        $stop;
 
                                        end else if (char_buffer[0  +:8*5]===&quot;$time&quot;) begin
                                                        $display(&quot;Current Time on Simulation=%d&quot;,$time);
 
                                        end else  Cprint;//$write(&quot;%s&quot;,char_buffer);
 
                                        for (counter=0; counter&lt; 80*2; counter=counter+1) begin
                                                char_buffer[counter*8 +:8]=8'h00;
                                        end
                                        counter=0;
 
                                end else begin
                                        char_buffer[counter*8 +:8]=mem_data_w[7:0];
                                        counter=counter+1;
                                end
                   end
           else if (mem_address==`Print_CAHR_Port_Address) begin
                                $write(&quot;%h &quot;,mem_data_w[7:0]);
                   end else if (mem_address==`Print_INT_Port_Address) begin
                                $write(&quot;%h &quot;,mem_data_w[15:0]);//Little Endian
                   end else if (mem_address==`Print_LONG_Port_Address) begin
                                $write(&quot;%h &quot;,mem_data_w[31:0]);//Big Endian
                   end
        end //if
   end //always
 
 
//uart read port
  wire [7:0] buffer_reg;
  wire int_req;
  reg sync_reset;
 
  localparam LF=8'h0a;
        always @(posedge clock, negedge Reset) begin
                if (!Reset) sync_reset &lt;=1'b1;
                else sync_reset&lt;=1'b0;
        end
 
 
 
   uart_read   uart_read_port( .sync_reset(sync_reset), .clk(clock), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));
 
        always @(posedge int_req) begin
                begin :local
 
                        reg [7:0] local_mem [0:1000];
                        integer i=0;
 
                        if (i&gt;=1000) $stop;//assert(0);
 
                        if (buffer_reg==LF) begin :local2 //pop stack
                                integer j;
                                j=0;
                                while( j &lt; i) begin
                                        $write( &quot;%c&quot;,local_mem[j]);
                                        j=j+1;
                                end
                                $write(&quot;     : time=%t\n&quot;,$time);
                                i=0;//clear stack
                        end else begin//push stack
 
                                local_mem[i]=buffer_reg;
                                i=i+1;
                         end
                end
 
        end
endmodule
 
</PRE>
      </TH>
    </TR>
  </TBODY>
</TABLE>
<P><BR>
</P>
<P>Figure below shows Spartan3 and Stratix2 result.<BR>
<BR>
Test Start :330310ns<BR>
Test Stop: 498050ns<BR>
<BR>
Since 10 cycles was done,<BR>
&nbsp;1 Cycle Time=(498050-330310)/10=167740ns<BR>
This means<BR>
&nbsp;596000Dhrystones/Sec<BR>
<BR>
VAX Computer is&nbsp;1757Dhrysones/Sec,this results 34DMIPS<BR>
<BR>
In this test bench System Clock is set at 50MHz,<BR>
Therefore Final Result is as follows.<BR>
<BR>
<B>17DMIPS for Spartan3</B> (allowable synthesized maximum frequency is 25MHz)<BR>
<B>110DMIPS for Stratix2</B>(allowable synthesized maximum frequency is 165MHz)<BR>
<BR>
</P>
<P><IMG src="dhrystone.png" width="783" height="715" border="0"></P>
<P>Note:<BR>
In Dhrystone benchmark, assembled &quot;strcmp&quot;&nbsp;was&nbsp;used&nbsp;instead&nbsp;of &quot;C strcmp &quot;.This is important for <B><I>fast</I></B> DMIPS.<BR>
<BR>
</P>
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[/] [yacc/] [trunk/] [doc/] [benchmark.htm] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	tak.sugawa	`<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">`
2			`<HTML>`
3			`<HEAD>`
4			`<META http-equiv="Content-Type" content="text/html; charset=iso-8859-1">`
5			`<META name="GENERATOR" content="IBM WebSphere Studio Homepage Builder Version 9.0.2.0 for Windows">`
6			`<META http-equiv="Content-Style-Type" content="text/css">`
7			`<TITLE></TITLE>`
8			`</HEAD>`
9			`<BODY>`
10			`<P><B>4 Benchmark Test</B><BR>`
11			`<BR>`
12			`This test was using RTL simulation bench. When C program calls  print("$time"),`
13			`test bench in verilog prints $time.So call at start and finish of dhrystone`
14			`benchmark program. By using this technique you can measure exact clock`
15			`time for execution of benchmark program.<BR>`
16			`<BR>`
17			`</P>`
18			`<P>print "C" program</P>`
19			`<TABLE border="1">`
20			`<TBODY>`
21			`<TR>`
22			`<TH align="left">`
23			`<PRE>void print(unsigned char* ptr)//Verilog Test Bench Use`
24			`{`
25			`#ifdef DOS`
26			`printf("%s ",ptr);`
27			`#else`
28
29			`while (*ptr) {`
30
31			`(volatile unsigned char)print_port=*(ptr++);`
32			`}`
33
34			`(volatile unsigned char)print_port=0x00;//Write Done`
35			`#endif`
36			`}`
37			`</PRE>`
38			`</TH>`
39			`</TR>`
40			`</TBODY>`
41			`</TABLE>`
42			`<P><BR>`
43			`Test bench in Verilog HDL</P>`
44			`<TABLE border="1">`
45			`<TBODY>`
46			`<TR>`
47			`<TH align="left">`
48			`<PRE>//YACC Test Bench`
49			`//Apr.5.2005 Tak.Sugawara`
50
51			`include "define.h"
52			`timescale 1ns/1ps
53
54			`module yacc_test;`
55			`reg clock=0;`
56			`reg Reset=0;`
57			`reg int_req_usr=0;`
58			`reg RXD=1'b1;`
59			`wire TXD;`
60			`wire [31:0] mem_data_w;`
61			`wire mem_write;`
62			`wire [15:0] mem_address;`
63			`always #20 clock=~clock;`
64
65
66
67			`initial begin`
68			`Reset=0;`
69			`#800 Reset=1;`
70			`end`
71
72			`ifdef RTL_SIMULATION
73			`yacc cpu(.clock(clock),.Async_Reset(Reset),.MemoryWData(mem_data_w),`
74			`.MWriteFF(mem_write),`
75			`.data_port_address(mem_address),.RXD(RXD),.TXD(TXD));`
76			`else
77			`yacc cpu(.clock(clock),.Async_Reset(Reset), .RXD(RXD),.TXD(TXD));`
78
79			`endif
80
81
82
83
84
85
86
87
88			`task Cprint;// String OUT until the byte 00 or xx detected with least Byte first and justified.`
89			`integer i;`
90			`begin :Block`
91			`i=0;`
92			`while (1) begin`
93			`if (char_buffer[i8 +:8] ===8'h00 \|\| char_buffer[i8 +:8]===8'hxx) begin`
94			`disable Block;`
95			`end`
96			`$write("%c",char_buffer[i*8 +:8]);`
97			`i=i+1;`
98			`end`
99			`end`
100			`endtask`
101
102			`reg [0:640*2-1] char_buffer;`
103			`integer counter=0;`
104			`always @ (posedge clock ) begin`
105			`if ((mem_write === 1'b1)) begin`
106			if (mem_address==`Print_Port_Address) begin
107			`if (mem_data_w[7:0]===8'h00) begin`
108			`char_buffer[counter*8 +:8]=mem_data_w[7:0];`
109			`if (char_buffer[0 +:8*7]==="$finish") begin`
110			`$stop;`
111
112			`end else if (char_buffer[0 +:8*5]==="$time") begin`
113			`$display("Current Time on Simulation=%d",$time);`
114
115			`end else Cprint;//$write("%s",char_buffer);`
116
117			`for (counter=0; counter< 80*2; counter=counter+1) begin`
118			`char_buffer[counter*8 +:8]=8'h00;`
119			`end`
120			`counter=0;`
121
122			`end else begin`
123			`char_buffer[counter*8 +:8]=mem_data_w[7:0];`
124			`counter=counter+1;`
125			`end`
126			`end`
127			else if (mem_address==`Print_CAHR_Port_Address) begin
128			`$write("%h ",mem_data_w[7:0]);`
129			end else if (mem_address==`Print_INT_Port_Address) begin
130			`$write("%h ",mem_data_w[15:0]);//Little Endian`
131			end else if (mem_address==`Print_LONG_Port_Address) begin
132			`$write("%h ",mem_data_w[31:0]);//Big Endian`
133			`end`
134			`end //if`
135			`end //always`
136
137
138			`//uart read port`
139			`wire [7:0] buffer_reg;`
140			`wire int_req;`
141			`reg sync_reset;`
142
143			`localparam LF=8'h0a;`
144			`always @(posedge clock, negedge Reset) begin`
145			`if (!Reset) sync_reset <=1'b1;`
146			`else sync_reset<=1'b0;`
147			`end`
148
149
150
151			`uart_read uart_read_port( .sync_reset(sync_reset), .clk(clock), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));`
152
153			`always @(posedge int_req) begin`
154			`begin :local`
155
156			`reg [7:0] local_mem [0:1000];`
157			`integer i=0;`
158
159			`if (i>=1000) $stop;//assert(0);`
160
161			`if (buffer_reg==LF) begin :local2 //pop stack`
162			`integer j;`
163			`j=0;`
164			`while( j < i) begin`
165			`$write( "%c",local_mem[j]);`
166			`j=j+1;`
167			`end`
168			`$write(" : time=%t\n",$time);`
169			`i=0;//clear stack`
170			`end else begin//push stack`
171
172			`local_mem[i]=buffer_reg;`
173			`i=i+1;`
174			`end`
175			`end`
176
177			`end`
178			`endmodule`
179
180			`</PRE>`
181			`</TH>`
182			`</TR>`
183			`</TBODY>`
184			`</TABLE>`
185			`<P><BR>`
186			`</P>`
187			`<P>Figure below shows Spartan3 and Stratix2 result.<BR>`
188			`<BR>`
189			`Test Start :330310ns<BR>`
190			`Test Stop: 498050ns<BR>`
191			`<BR>`
192			`Since 10 cycles was done,<BR>`
193			` 1 Cycle Time=(498050-330310)/10=167740ns<BR>`
194			`This means<BR>`
195			` 596000Dhrystones/Sec<BR>`
196			`<BR>`
197			`VAX Computer is 1757Dhrysones/Sec,this results 34DMIPS<BR>`
198			`<BR>`
199			`In this test bench System Clock is set at 50MHz,<BR>`
200			`Therefore Final Result is as follows.<BR>`
201			`<BR>`
202			`<B>17DMIPS for Spartan3</B> (allowable synthesized maximum frequency is 25MHz)<BR>`
203			`<B>110DMIPS for Stratix2</B>(allowable synthesized maximum frequency is 165MHz)<BR>`
204			`<BR>`
205			`</P>`
206			`<P><IMG src="dhrystone.png" width="783" height="715" border="0"></P>`
207			`<P>Note:<BR>`
208			`In Dhrystone benchmark, assembled "strcmp" was used instead of "C strcmp ".This is important for <B><I>fast</I></B> DMIPS.<BR>`
209			`<BR>`
210			`</P>`
211			`</BODY>`
212			`</HTML>`