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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<HTML>
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<HEAD>
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<META http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
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<META name="GENERATOR" content="IBM WebSphere Studio Homepage Builder Version 9.0.2.0 for Windows">
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<META http-equiv="Content-Style-Type" content="text/css">
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<TITLE></TITLE>
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</HEAD>
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<BODY>
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<P><B>7 Examples of C compilation</B><BR>
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FPGA Vendor's library is not attached since they are property of vendors.
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Set them under \lib folder as below to run RTL/Delay simulation in Veritak.(XilinxCorelib
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is not attached in free Web Edition. BaseX or higher edition will be necessary.)<BR>
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<IMG src="folder_structure.png" width="847" height="334" border="0"><BR>
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<BR>
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<B>7.1 RTL</B><BR>
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<BR>
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In RTL simulation using UART is too slow for debugging the cpu. Therefore output is changed
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to console instead of UART PORT. Please note RTL
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simulation takes very long time in running actual 10msec .</P>
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<TABLE border=1>
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<TBODY>
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<TR>
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<TD width=176>Folder</TD>
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<TD width=136>C Program</TD>
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<TD>Description</TD>
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<TD>Batch File</TD>
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<TD>Veritak Project(\bench\verilog)</TD>
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</TR>
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<TR>
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<TD width=176>\bench\c_src\count</TD>
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<TD width=136>count_tak.c</TD>
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<TD>By Steve Rhords</TD>
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<TD>compile.bat</TD>
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<TD>altera_rtl/xilinx_rtl</TD>
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</TR>
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<TR>
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<TD width=176>\bench\c_src\pi</TD>
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<TD width=136>pi2.c</TD>
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<TD>pi 10digits</TD>
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<TD>compile.bat</TD>
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<TD>altera_rtl_no_wave/xilinx_rtl_no_wave</TD>
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</TR>
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<TR>
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<TD width=176>\bench\c_src\dhrystone</TD>
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<TD width=136>dhry21_tak.c</TD>
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<TD>Dhrystone</TD>
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<TD>compile.bat</TD>
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<TD>altera_rtl_no_wave/xilinx_rtl_no_wave</TD>
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</TR>
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<TR>
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<TD width=176>\bench\c_src\reed solomon</TD>
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<TD width=136>rs_tak.c</TD>
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<TD>By Phil Karn</TD>
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<TD>compile.bat</TD>
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<TD>altera_rtl_no_wave/xilinx_rtl_no_wave</TD>
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</TR>
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<TR>
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<TD width=176>\bench\c_src\calculator</TD>
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<TD width=136>uart_echo_test.c</TD>
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<TD>Interactive Calculator. Interrupt debug use</TD>
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<TD>compile.bat</TD>
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<TD>altera_calculator_test_using_uart_echo/xilinx_calculator_test_using_uart_echo<BR>
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</TD>
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</TR>
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</TBODY>
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</TABLE>
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<P><BR>
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(1) count </P>
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<P><IMG src="count_rtl_sim.png" width="783" height="734" border="0"></P>
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<P>(2)Pi<BR>
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<IMG src="xilinx_pi_rtl_sim.png" width="877" height="295" border="0"><BR>
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<BR>
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(3)Reed Solomon<IMG src="rs_rtl_sim_by_cyclone.png" width="1007" height="719" border="0"></P>
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<P><BR>
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(4) Calculator<BR>
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This is console output only, not interactive. Using echo-back technique,
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UART interrupt test was done.<BR>
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<IMG src="xilinx_calculator_rtl_sim.png" width="877" height="715" border="0"></P>
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<P>RTL Simulation Procedure<BR>
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</P>
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<UL>
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<LI>Compile C program using compile.bat
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<LI>conver_mips.exe will generate memory initialization file for both Altera
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and Xilinx,which will be sent to\rtl\xilinx and \rtl\altera.
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<LI>Load Veritak Project=>Go
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</UL>
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<P><B>7.2 Gate Simulation</B><BR>
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Using "count" above,Post-Layout Gate Simulation was performed.<BR>
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</P>
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<TABLE border=1>
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<TBODY>
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<TR>
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<TD>Folder</TD>
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<TD>Veritak Project File</TD>
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<TD>Frequency</TD>
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</TR>
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<TR>
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<TD>\syn\altra_stratix2\simulation\custom</TD>
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<TD>Gate_altera</TD>
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<TD>165MHz</TD>
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</TR>
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<TR>
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<TD>\syn\altera\simulation\custom</TD>
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<TD>Gate_altera</TD>
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<TD>100MHz</TD>
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</TR>
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<TR>
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<TD>\syn\xilinx</TD>
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<TD>Gate_xilinx</TD>
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<TD>25MHz</TD>
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</TR>
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</TBODY>
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</TABLE>
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<P><BR>
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<BR>
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<B>7.3 FPGA</B></P>
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<TABLE border=1>
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<TBODY>
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<TR>
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<TD>Folder</TD>
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<TD>C Program</TD>
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<TD>Batch File</TD>
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<TD>Description</TD>
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</TR>
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<TR>
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<TD>\syn\c_src\count</TD>
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<TD>count_tak.c</TD>
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<TD>compile.bat</TD>
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<TD>By Steve Rhords</TD>
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</TR>
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<TR>
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<TD>\syn\c_src\pi</TD>
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<TD>pi2.c</TD>
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<TD>compile.bat</TD>
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<TD>pi 800 digits calculation</TD>
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</TR>
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<TR>
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<TD>\syn\c_src\reed solomon</TD>
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<TD>rs_tak.c</TD>
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<TD>compile.bat</TD>
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<TD>By Phil Karn</TD>
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</TR>
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<TR>
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<TD>\syn\yacc\bench\c_src\calculator</TD>
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<TD>uart_echo_test.c</TD>
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<TD>compile.bat</TD>
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<TD>Interactive Calculater</TD>
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</TR>
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</TBODY>
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</TABLE>
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<P><Synthesis Procedure><BR>
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</P>
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<UL>
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<LI>Run Batch File
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<LI>Synthesize top of hardware Regenerate RAM using core-generator, then Synthesize
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top of hardware
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</UL>
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<P><BR>
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<BR>
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FPGA Confirmation<BR>
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</P>
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<TABLE border=1>
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<TBODY>
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<TR>
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<TD>FPGA</TD>
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<TD>FPGA BOARD</TD>
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<TD>Device</TD>
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<TD>Clock</TD>
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<TD>CPU<BR>
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CLOCK</TD>
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<TD>UART Baud Rate</TD>
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<TD>Synthesized by</TD>
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</TR>
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<TR>
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<TD>Altera</TD>
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<TD><EM>Future Electronics Cyclone/Nios II Development</EM> <EM>Board</EM></TD>
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<TD>EP1C12Q240C6</TD>
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<TD>50MHz</TD>
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<TD>50MHz</TD>
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<TD>115.2KBPS</TD>
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<TD>Quartus4.2</TD>
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</TR>
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<TR>
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<TD>Xilinx</TD>
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<TD>Xilin‚˜ Spartan3 Starter Kit</TD>
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<TD>XC3S200-4FT256C </TD>
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<TD>50MHz</TD>
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<TD>25MHz</TD>
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<TD>57.6KBPS</TD>
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<TD>ISE7.1</TD>
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</TR>
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</TBODY>
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</TABLE>
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<P><IMG src="future.jpg" width="320" height="240" border="0"><IMG src="spartan3.jpg" width="320" height="240" border="0"></P>
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<P><EM>Future Electronics Cyclone/Nios II Development</EM> <EM>Board</EM>
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Spartan3 Starter Kit</P>
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<P>(1) count<BR>
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Same as RTL simulation except for endless loop.<BR>
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(2) pi<BR>
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3.1415...follows by 800 digits.It was the same
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result as PC.<BR>
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<BR>
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<IMG src="pi800_by_cyclone.png" width="860" height="566" border="0"><BR>
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<BR>
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(3)Interactive Calculator<BR>
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Use PC terminal software.You can calcuate like C program.<BR>
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<IMG src="calculator.png" width="860" height="540" border="0"><BR>
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<BR>
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<BR>
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(4) Reed Solomon<BR>
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Very Complex program (255,223) performs 120 cycles of 21bytes correction(including
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erasures). No miss-correction is detected.</P>
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<P><IMG src="rs_by_xilinx.png" width="836" height="566" border="0"></P>
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</BODY>
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