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<P><B>1.0 Overview</B><BR>
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<BR>
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YACC (<B>Y</B>et <B>A</B>nother <B>C</B>PU <B>C</B>PU) is MIPS I (TM) subset cpu written in Verilog.-2001HDL. YACC
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has 5 pipeline and shows 110DMIPS in stratix2 with synthesized allowable
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clock of 165MHz. It is independent design of plasma, although YACC uses gcc-elf-mips
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tools provided by Steve Rhords, author of plasma (Most mips written in VHDL).<BR>
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The core was developed by using Veritak Simulator, with post layout gate
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simulation, and tested by actual FPGAs, using Xilinx spartan3 starter kit
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and Cyclone by Altera,running 800 digits of pi calculation ,(255,223) Reed
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Solomon Error Correction ,and Interactive calculator written by C language.</P>
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<P><B><FONT class="block_title" size="+0">1.1 Disclaimer</FONT></B>
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<P>MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS
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Technologies, Inc. MIPS Technologies, Inc. does not endorse and is not
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associated with this project. Tak.Sugawara is not affiliated
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in any way with MIPS Technologies, Inc.<BR>
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</P>
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<P><B>1.2 Legal</B><BR>
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<BR>I have no idea if implementing this core will or will not violate<BR>
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patents, copyrights or cause any other type of lawsuits.<BR>
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<BR>
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I provide this core "as is", without any warranties. If you decide to<BR>
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build this core, you are responsible for any legal resolutions, such<BR>
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as patents and copyrights, and perhaps others ....<BR>
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<BR>
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THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY<BR>
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT<BR>
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND<BR>
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FITNESS FOR A PARTICULAR PURPOSE.</P>
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<P><BR>
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<BR>
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<B> 1.3 Background</B><BR>
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<BR>
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When I am developing VHDL to Verilog translator , I found plasma core in opencores. It is excellent work to learn a lot. After I <A href="http://www.sugawara-systems.com/opencores/plasma.htm">translated plasma</A> written by VHDL to Verilog HDL almost automatically using
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Veritak Translator, I stated to design my own CPU per following target
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spec.</P>
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<UL>
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<LI>works with free C compiler ->use plasma resources
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<LI>pretend to be <B><I>fast</I></B> (Actually ..)
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<UL>
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<LI>5 stage pipeline
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<LI>use dual port memory in FPGA (Dhrystone benchmark test requires only
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16KB memory !)
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</UL>
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<LI>works with Altera/Xilinx FPGAs
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<LI>with minimum logic cells in FPGA
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</UL>
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