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tak.sugawa |
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<HTML>
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<HEAD>
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<META http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
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<META name="GENERATOR" content="IBM WebSphere Studio Homepage Builder Version 9.0.2.0 for Windows">
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<META http-equiv="Content-Style-Type" content="text/css">
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<TITLE></TITLE>
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<LINK rel="stylesheet" href="table.css" type="text/css" id="_HPB_TABLE_CSS_ID_">
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</HEAD>
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<BODY>
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<P><B>2. Design</B><BR>
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<B>2.1 Pipeline Consideration</B><BR>
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<BR>
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If PC is incremental then YACC performs all instruction at 1 clock
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cycle including memory R/W. However, if PC is not incremental, Jump address
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calculation is necessary , which requires more cycles in YACC.</P>
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<P>(1) Normal Commands :- 1Clock Cycle</P>
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<TABLE border="1">
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<TBODY>
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<TR>
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<TH valign="middle" align="center">Time Slot</TH>
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<TH valign="middle" align="center">Stage1</TH>
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<TH valign="middle" align="center">Stage2</TH>
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<TH valign="middle" align="center">Stage3</TH>
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<TH valign="middle" align="center">Stage4</TH>
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<TH valign="middle" align="center">Stage5</TH>
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</TR>
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<TR>
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<TD valign="middle" align="center"> </TD>
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<TD valign="middle" align="center">Set Register File Address</TD>
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<TD valign="middle" align="center">Read Register File<BR>
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ALU_LEFT/Right Latch</TD>
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<TD valign="middle" align="center">Mem Write<BR>
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AReg<=ALU</TD>
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<TD valign="middle" align="center">Mem Read<BR>
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NReg<=AReg</TD>
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<TD valign="middle" align="center">Write Register File<BR>
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RReg<=NReg</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">1</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">2</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">Fetch & Decode</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">3</TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">ALU</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">4</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">MEM</TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">5</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">WB</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">6</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">7</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">8</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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</TBODY>
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</TABLE>
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<P>(2) Jump address is known at fetch Cycle -2 Clock Cycle</P>
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<P>GCC tries to insert delayed branch command just after jump command. Therefore
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no performance penalty will be in most cases.</P>
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<TABLE border="1">
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<TBODY>
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<TR>
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<TH valign="middle" align="center">Time Slot</TH>
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<TH valign="middle" align="center">Stage1</TH>
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<TH valign="middle" align="center">Stage2</TH>
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<TH valign="middle" align="center">Stage3</TH>
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<TH valign="middle" align="center">Stage4</TH>
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<TH valign="middle" align="center">Stage5</TH>
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</TR>
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<TR>
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<TD valign="middle" align="center"> </TD>
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<TD valign="middle" align="center">Set Register File Address</TD>
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<TD valign="middle" align="center">Read Register File<BR>
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ALU_LEFT/Right Latch</TD>
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<TD valign="middle" align="center">Mem Write<BR>
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AReg<=ALU</TD>
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<TD valign="middle" align="center">Mem Read<BR>
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NReg<=AReg</TD>
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<TD valign="middle" align="center">Write Register File<BR>
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RReg<=NReg</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">1</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Jump Detected)</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">2</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">Set Jump Address</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">3</TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Jumped Address)</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">4</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">5</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">6</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">7</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">8</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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</TBODY>
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</TABLE>
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<P>(3) Register Jump : -3 Clock Cycle</P>
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<P> Jump Address is not determined until Register File is read. This
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will result performance penalty.</P>
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<TABLE border="1">
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<TBODY>
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<TR>
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<TH valign="middle" align="center">Time Slot</TH>
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<TH valign="middle" align="center">Stage1</TH>
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<TH valign="middle" align="center">Stage2</TH>
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<TH valign="middle" align="center">Stage3</TH>
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<TH valign="middle" align="center">Stage4</TH>
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<TH valign="middle" align="center">Stage5</TH>
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</TR>
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<TR>
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<TD valign="middle" align="center"> </TD>
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<TD valign="middle" align="center">Set Register File Address</TD>
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<TD valign="middle" align="center">Read Register File<BR>
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ALU_LEFT/Right Latch</TD>
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<TD valign="middle" align="center">Mem Write<BR>
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AReg<=ALU</TD>
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<TD valign="middle" align="center">Mem Read<BR>
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NReg<=AReg</TD>
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<TD valign="middle" align="center">Write Register File<BR>
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RReg<=NReg</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">1</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Register Jump Detected)</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">2</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile </TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">3</TD>
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<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00">Set Jump Address</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">4</TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Jumped Address)</TD>
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<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
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<TD valign="middle" align="center"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">5</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
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<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
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<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">6</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
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<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
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<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">7</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
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<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
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</TR>
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<TR>
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<TD valign="middle" align="center">8</TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center"></TD>
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<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
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</TR>
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</TBODY>
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</TABLE>
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<P>
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<BR>
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</P>
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<P>(4) Branch with Branch commands : -4 Clock Cycle</P>
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<P> We can not set branch address until take is set. This will be big
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penalty in YACC. To improve this situation, branch prediction mechanism
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will be necessary. (Not implemented in YACC).</P>
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<TABLE border="1">
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<TBODY>
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<TR>
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<TH valign="middle" align="center">Time Slot</TH>
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<TH valign="middle" align="center">Stage1</TH>
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<TH valign="middle" align="center">Stage2</TH>
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<TH valign="middle" align="center">Stage3</TH>
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<TH valign="middle" align="center">Stage4</TH>
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<TH valign="middle" align="center">Stage5</TH>
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</TR>
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<TR>
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<TD valign="middle" align="center"> </TD>
|
307 |
|
|
<TD valign="middle" align="center">Set Register File Address</TD>
|
308 |
|
|
<TD valign="middle" align="center">Read Register File<BR>
|
309 |
|
|
ALU_LEFT/Right Latch</TD>
|
310 |
|
|
<TD valign="middle" align="center">Mem Write<BR>
|
311 |
|
|
AReg<=ALU</TD>
|
312 |
|
|
<TD valign="middle" align="center">Mem Read<BR>
|
313 |
|
|
NReg<=AReg</TD>
|
314 |
|
|
<TD valign="middle" align="center">Write Register File<BR>
|
315 |
|
|
RReg<=NReg</TD>
|
316 |
|
|
</TR>
|
317 |
|
|
<TR>
|
318 |
|
|
<TD valign="middle" align="center">1</TD>
|
319 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Branch command Detected)</TD>
|
320 |
|
|
<TD valign="middle" align="center"></TD>
|
321 |
|
|
<TD valign="middle" align="center"></TD>
|
322 |
|
|
<TD valign="middle" align="center"></TD>
|
323 |
|
|
<TD valign="middle" align="center"></TD>
|
324 |
|
|
</TR>
|
325 |
|
|
<TR>
|
326 |
|
|
<TD valign="middle" align="center">2</TD>
|
327 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
|
328 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile </TD>
|
329 |
|
|
<TD valign="middle" align="center"></TD>
|
330 |
|
|
<TD valign="middle" align="center"></TD>
|
331 |
|
|
<TD valign="middle" align="center"></TD>
|
332 |
|
|
</TR>
|
333 |
|
|
<TR>
|
334 |
|
|
<TD valign="middle" align="center">3</TD>
|
335 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
|
336 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
|
337 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">Set Not Taken</TD>
|
338 |
|
|
<TD valign="middle" align="center"></TD>
|
339 |
|
|
<TD valign="middle" align="center"></TD>
|
340 |
|
|
</TR>
|
341 |
|
|
<TR>
|
342 |
|
|
<TD valign="middle" align="center">4</TD>
|
343 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
|
344 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
345 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
|
346 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">Set Branch Address</TD>
|
347 |
|
|
<TD valign="middle" align="center"></TD>
|
348 |
|
|
</TR>
|
349 |
|
|
<TR>
|
350 |
|
|
<TD valign="middle" align="center">5</TD>
|
351 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Branch Address)</TD>
|
352 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
353 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
354 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
|
355 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
|
356 |
|
|
</TR>
|
357 |
|
|
<TR>
|
358 |
|
|
<TD valign="middle" align="center">6</TD>
|
359 |
|
|
<TD valign="middle" align="center"></TD>
|
360 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
|
361 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
362 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
363 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
|
364 |
|
|
</TR>
|
365 |
|
|
<TR>
|
366 |
|
|
<TD valign="middle" align="center">7</TD>
|
367 |
|
|
<TD valign="middle" align="center"></TD>
|
368 |
|
|
<TD valign="middle" align="center"></TD>
|
369 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
|
370 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
371 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
372 |
|
|
</TR>
|
373 |
|
|
<TR>
|
374 |
|
|
<TD valign="middle" align="center">8</TD>
|
375 |
|
|
<TD valign="middle" align="center"></TD>
|
376 |
|
|
<TD valign="middle" align="center"></TD>
|
377 |
|
|
<TD valign="middle" align="center"></TD>
|
378 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
|
379 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
380 |
|
|
</TR>
|
381 |
|
|
</TBODY>
|
382 |
|
|
</TABLE>
|
383 |
|
|
<P>(5) Not Branch with Branch commands : -3 Clock Cycle</P>
|
384 |
|
|
<P> After Taken is Not set, we understand PC is incremental.</P>
|
385 |
|
|
<TABLE border="1">
|
386 |
|
|
<TBODY>
|
387 |
|
|
<TR>
|
388 |
|
|
<TH valign="middle" align="center">Time Slot</TH>
|
389 |
|
|
<TH valign="middle" align="center">Stage1</TH>
|
390 |
|
|
<TH valign="middle" align="center">Stage2</TH>
|
391 |
|
|
<TH valign="middle" align="center">Stage3</TH>
|
392 |
|
|
<TH valign="middle" align="center">Stage4</TH>
|
393 |
|
|
<TH valign="middle" align="center">Stage5</TH>
|
394 |
|
|
</TR>
|
395 |
|
|
<TR>
|
396 |
|
|
<TD valign="middle" align="center"> </TD>
|
397 |
|
|
<TD valign="middle" align="center">Set Register File Address</TD>
|
398 |
|
|
<TD valign="middle" align="center">Read Register File<BR>
|
399 |
|
|
ALU_LEFT/Right Latch</TD>
|
400 |
|
|
<TD valign="middle" align="center">Mem Write<BR>
|
401 |
|
|
AReg<=ALU</TD>
|
402 |
|
|
<TD valign="middle" align="center">Mem Read<BR>
|
403 |
|
|
NReg<=AReg</TD>
|
404 |
|
|
<TD valign="middle" align="center">Write Register File<BR>
|
405 |
|
|
RReg<=NReg</TD>
|
406 |
|
|
</TR>
|
407 |
|
|
<TR>
|
408 |
|
|
<TD valign="middle" align="center">1</TD>
|
409 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Branch command Detected)</TD>
|
410 |
|
|
<TD valign="middle" align="center"></TD>
|
411 |
|
|
<TD valign="middle" align="center"></TD>
|
412 |
|
|
<TD valign="middle" align="center"></TD>
|
413 |
|
|
<TD valign="middle" align="center"></TD>
|
414 |
|
|
</TR>
|
415 |
|
|
<TR>
|
416 |
|
|
<TD valign="middle" align="center">2</TD>
|
417 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
|
418 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile </TD>
|
419 |
|
|
<TD valign="middle" align="center"></TD>
|
420 |
|
|
<TD valign="middle" align="center"></TD>
|
421 |
|
|
<TD valign="middle" align="center"></TD>
|
422 |
|
|
</TR>
|
423 |
|
|
<TR>
|
424 |
|
|
<TD valign="middle" align="center">3</TD>
|
425 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">Fetch & Decode</TD>
|
426 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
|
427 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">Set Not Taken</TD>
|
428 |
|
|
<TD valign="middle" align="center"></TD>
|
429 |
|
|
<TD valign="middle" align="center"></TD>
|
430 |
|
|
</TR>
|
431 |
|
|
<TR>
|
432 |
|
|
<TD valign="middle" align="center">4</TD>
|
433 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & DecFetch (Not Branched Address)</TD>
|
434 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
435 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
|
436 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
|
437 |
|
|
<TD valign="middle" align="center"></TD>
|
438 |
|
|
</TR>
|
439 |
|
|
<TR>
|
440 |
|
|
<TD valign="middle" align="center">5</TD>
|
441 |
|
|
<TD valign="middle" align="center"></TD>
|
442 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile </TD>
|
443 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
444 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
|
445 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
|
446 |
|
|
</TR>
|
447 |
|
|
<TR>
|
448 |
|
|
<TD valign="middle" align="center">6</TD>
|
449 |
|
|
<TD valign="middle" align="center"></TD>
|
450 |
|
|
<TD valign="middle" align="center"></TD>
|
451 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
|
452 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
453 |
|
|
<TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
|
454 |
|
|
</TR>
|
455 |
|
|
<TR>
|
456 |
|
|
<TD valign="middle" align="center">7</TD>
|
457 |
|
|
<TD valign="middle" align="center"></TD>
|
458 |
|
|
<TD valign="middle" align="center"></TD>
|
459 |
|
|
<TD valign="middle" align="center"></TD>
|
460 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
|
461 |
|
|
<TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
|
462 |
|
|
</TR>
|
463 |
|
|
<TR>
|
464 |
|
|
<TD valign="middle" align="center">8</TD>
|
465 |
|
|
<TD valign="middle" align="center"></TD>
|
466 |
|
|
<TD valign="middle" align="center"></TD>
|
467 |
|
|
<TD valign="middle" align="center"></TD>
|
468 |
|
|
<TD valign="middle" align="center"></TD>
|
469 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
|
470 |
|
|
</TR>
|
471 |
|
|
</TBODY>
|
472 |
|
|
</TABLE>
|
473 |
|
|
<P>(6) Interrupt -2 Clock Cycle</P>
|
474 |
|
|
<P>In YACC interrupt is like jump command.To simplify the interrupt logic,Interrupt
|
475 |
|
|
is inhibited during mul/div/jump/branch commands in YACC implementation.</P>
|
476 |
|
|
<TABLE border="1">
|
477 |
|
|
<TBODY>
|
478 |
|
|
<TR>
|
479 |
|
|
<TH valign="middle" align="center">Time Slot</TH>
|
480 |
|
|
<TH valign="middle" align="center">Stage1</TH>
|
481 |
|
|
<TH valign="middle" align="center">Stage2</TH>
|
482 |
|
|
<TH valign="middle" align="center">Stage3</TH>
|
483 |
|
|
<TH valign="middle" align="center">Stage4</TH>
|
484 |
|
|
<TH valign="middle" align="center">Stage5</TH>
|
485 |
|
|
</TR>
|
486 |
|
|
<TR>
|
487 |
|
|
<TD valign="middle" align="center"> </TD>
|
488 |
|
|
<TD valign="middle" align="center">Set Register File Address</TD>
|
489 |
|
|
<TD valign="middle" align="center">Read Register File<BR>
|
490 |
|
|
ALU_LEFT/Right Latch</TD>
|
491 |
|
|
<TD valign="middle" align="center">Mem Write<BR>
|
492 |
|
|
AReg<=ALU</TD>
|
493 |
|
|
<TD valign="middle" align="center">Mem Read<BR>
|
494 |
|
|
NReg<=AReg</TD>
|
495 |
|
|
<TD valign="middle" align="center">Write Register File<BR>
|
496 |
|
|
RReg<=NReg</TD>
|
497 |
|
|
</TR>
|
498 |
|
|
<TR>
|
499 |
|
|
<TD valign="middle" align="center">1</TD>
|
500 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">Fetch & Decode(Interrupt)</TD>
|
501 |
|
|
<TD valign="middle" align="center"></TD>
|
502 |
|
|
<TD valign="middle" align="center"></TD>
|
503 |
|
|
<TD valign="middle" align="center"></TD>
|
504 |
|
|
<TD valign="middle" align="center"></TD>
|
505 |
|
|
</TR>
|
506 |
|
|
<TR>
|
507 |
|
|
<TD valign="middle" align="center">2</TD>
|
508 |
|
|
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
|
509 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00">Set Interrupt Address/<BR>
|
510 |
|
|
Save Returned Address</TD>
|
511 |
|
|
<TD valign="middle" align="center"></TD>
|
512 |
|
|
<TD valign="middle" align="center"></TD>
|
513 |
|
|
<TD valign="middle" align="center"></TD>
|
514 |
|
|
</TR>
|
515 |
|
|
<TR>
|
516 |
|
|
<TD valign="middle" align="center">3</TD>
|
517 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">Fetch & Decode(Interrupt Address)</TD>
|
518 |
|
|
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
|
519 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
|
520 |
|
|
<TD valign="middle" align="center"></TD>
|
521 |
|
|
<TD valign="middle" align="center"></TD>
|
522 |
|
|
</TR>
|
523 |
|
|
<TR>
|
524 |
|
|
<TD valign="middle" align="center">4</TD>
|
525 |
|
|
<TD valign="middle" align="center"></TD>
|
526 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
|
527 |
|
|
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
|
528 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
|
529 |
|
|
<TD valign="middle" align="center"></TD>
|
530 |
|
|
</TR>
|
531 |
|
|
<TR>
|
532 |
|
|
<TD valign="middle" align="center">5</TD>
|
533 |
|
|
<TD valign="middle" align="center"></TD>
|
534 |
|
|
<TD valign="middle" align="center"></TD>
|
535 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
|
536 |
|
|
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
|
537 |
|
|
<TD valign="middle" align="center" bgcolor="#ffff00"></TD>
|
538 |
|
|
</TR>
|
539 |
|
|
<TR>
|
540 |
|
|
<TD valign="middle" align="center">6</TD>
|
541 |
|
|
<TD valign="middle" align="center"></TD>
|
542 |
|
|
<TD valign="middle" align="center"></TD>
|
543 |
|
|
<TD valign="middle" align="center"></TD>
|
544 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
|
545 |
|
|
<TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
|
546 |
|
|
</TR>
|
547 |
|
|
<TR>
|
548 |
|
|
<TD valign="middle" align="center">7</TD>
|
549 |
|
|
<TD valign="middle" align="center"></TD>
|
550 |
|
|
<TD valign="middle" align="center"></TD>
|
551 |
|
|
<TD valign="middle" align="center"></TD>
|
552 |
|
|
<TD valign="middle" align="center"></TD>
|
553 |
|
|
<TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
|
554 |
|
|
</TR>
|
555 |
|
|
<TR>
|
556 |
|
|
<TD valign="middle" align="center">8</TD>
|
557 |
|
|
<TD valign="middle" align="center"></TD>
|
558 |
|
|
<TD valign="middle" align="center"></TD>
|
559 |
|
|
<TD valign="middle" align="center"></TD>
|
560 |
|
|
<TD valign="middle" align="center"></TD>
|
561 |
|
|
<TD valign="middle" align="center"></TD>
|
562 |
|
|
</TR>
|
563 |
|
|
</TBODY>
|
564 |
|
|
</TABLE>
|
565 |
|
|
<P>
|
566 |
|
|
<BR>
|
567 |
|
|
</P>
|
568 |
|
|
</BODY>
|
569 |
|
|
</HTML>
|