OpenCores
URL https://opencores.org/ocsvn/yacc/yacc/trunk

Subversion Repositories yacc

[/] [yacc/] [trunk/] [doc/] [pipeline.htm] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tak.sugawa 
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
2 
<HTML>
3 
<HEAD>
4 
<META http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
5 
<META name="GENERATOR" content="IBM WebSphere Studio Homepage Builder Version 9.0.2.0 for Windows">
6 
<META http-equiv="Content-Style-Type" content="text/css">
7 
<TITLE></TITLE>
8 
<LINK rel="stylesheet" href="table.css" type="text/css" id="_HPB_TABLE_CSS_ID_">
9 
</HEAD>
10 
<BODY>
11 
<P><B>2. Design</B><BR>
12 
<B>2.1 Pipeline Consideration</B><BR>
13 
<BR>
14 
If PC is incremental &nbsp;then YACC performs all instruction at 1 clock
15 
cycle including memory R/W. However, if PC is not incremental, Jump address
16 
calculation is necessary , which requires more cycles in YACC.</P>
17 
<P>(1) Normal Commands :- 1Clock Cycle</P>
18 
<TABLE border="1">
19 
  <TBODY>
20 
    <TR>
21 
      <TH valign="middle" align="center">Time Slot</TH>
22 
      <TH valign="middle" align="center">Stage1</TH>
23 
      <TH valign="middle" align="center">Stage2</TH>
24 
      <TH valign="middle" align="center">Stage3</TH>
25 
      <TH valign="middle" align="center">Stage4</TH>
26 
      <TH valign="middle" align="center">Stage5</TH>
27 
    </TR>
28 
    <TR>
29 
      <TD valign="middle" align="center">&nbsp;</TD>
30 
      <TD valign="middle" align="center">Set Register File Address</TD>
31 
      <TD valign="middle" align="center">Read Register File<BR>
32 
      ALU_LEFT/Right Latch</TD>
33 
      <TD valign="middle" align="center">Mem Write<BR>
34 
      AReg&lt;=ALU</TD>
35 
      <TD valign="middle" align="center">Mem Read<BR>
36 
      NReg&lt;=AReg</TD>
37 
      <TD valign="middle" align="center">Write Register File<BR>
38 
      RReg&lt;=NReg</TD>
39 
    </TR>
40 
    <TR>
41 
      <TD valign="middle" align="center">1</TD>
42 
      <TD valign="middle" align="center" bgcolor="#ffff00">Fetch &amp; Decode</TD>
43 
      <TD valign="middle" align="center"></TD>
44 
      <TD valign="middle" align="center"></TD>
45 
      <TD valign="middle" align="center"></TD>
46 
      <TD valign="middle" align="center"></TD>
47 
    </TR>
48 
    <TR>
49 
      <TD valign="middle" align="center">2</TD>
50 
      <TD valign="middle" align="center" bgcolor="#00cccc">Fetch &amp; Decode</TD>
51 
      <TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile</TD>
52 
      <TD valign="middle" align="center"></TD>
53 
      <TD valign="middle" align="center"></TD>
54 
      <TD valign="middle" align="center"></TD>
55 
    </TR>
56 
    <TR>
57 
      <TD valign="middle" align="center">3</TD>
58 
      <TD valign="middle" align="center" bgcolor="#cccccc">Fetch &amp; Decode</TD>
59 
      <TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
60 
      <TD valign="middle" align="center" bgcolor="#ffff00">ALU</TD>
61 
      <TD valign="middle" align="center"></TD>
62 
      <TD valign="middle" align="center"></TD>
63 
    </TR>
64 
    <TR>
65 
      <TD valign="middle" align="center">4</TD>
66 
      <TD valign="middle" align="center"></TD>
67 
      <TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
68 
      <TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
69 
      <TD valign="middle" align="center" bgcolor="#ffff00">MEM</TD>
70 
      <TD valign="middle" align="center"></TD>
71 
    </TR>
72 
    <TR>
73 
      <TD valign="middle" align="center">5</TD>
74 
      <TD valign="middle" align="center"></TD>
75 
      <TD valign="middle" align="center"></TD>
76 
      <TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
77 
      <TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
78 
      <TD valign="middle" align="center" bgcolor="#ffff00">WB</TD>
79 
    </TR>
80 
    <TR>
81 
      <TD valign="middle" align="center">6</TD>
82 
      <TD valign="middle" align="center"></TD>
83 
      <TD valign="middle" align="center"></TD>
84 
      <TD valign="middle" align="center"></TD>
85 
      <TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
86 
      <TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
87 
    </TR>
88 
    <TR>
89 
      <TD valign="middle" align="center">7</TD>
90 
      <TD valign="middle" align="center"></TD>
91 
      <TD valign="middle" align="center"></TD>
92 
      <TD valign="middle" align="center"></TD>
93 
      <TD valign="middle" align="center"></TD>
94 
      <TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
95 
    </TR>
96 
    <TR>
97 
      <TD valign="middle" align="center">8</TD>
98 
      <TD valign="middle" align="center"></TD>
99 
      <TD valign="middle" align="center"></TD>
100 
      <TD valign="middle" align="center"></TD>
101 
      <TD valign="middle" align="center"></TD>
102 
      <TD valign="middle" align="center"></TD>
103 
    </TR>
104 
  </TBODY>
105 
</TABLE>
106 
<P>(2) Jump address is known at fetch Cycle -2 Clock Cycle</P>
107 
<P>GCC tries to insert delayed branch command just after jump command. Therefore
108 
no performance penalty&nbsp;will&nbsp;be&nbsp; in most cases.</P>
109 
<TABLE border="1">
110 
  <TBODY>
111 
    <TR>
112 
      <TH valign="middle" align="center">Time Slot</TH>
113 
      <TH valign="middle" align="center">Stage1</TH>
114 
      <TH valign="middle" align="center">Stage2</TH>
115 
      <TH valign="middle" align="center">Stage3</TH>
116 
      <TH valign="middle" align="center">Stage4</TH>
117 
      <TH valign="middle" align="center">Stage5</TH>
118 
    </TR>
119 
    <TR>
120 
      <TD valign="middle" align="center">&nbsp;</TD>
121 
      <TD valign="middle" align="center">Set Register File Address</TD>
122 
      <TD valign="middle" align="center">Read Register File<BR>
123 
      ALU_LEFT/Right Latch</TD>
124 
      <TD valign="middle" align="center">Mem Write<BR>
125 
      AReg&lt;=ALU</TD>
126 
      <TD valign="middle" align="center">Mem Read<BR>
127 
      NReg&lt;=AReg</TD>
128 
      <TD valign="middle" align="center">Write Register File<BR>
129 
      RReg&lt;=NReg</TD>
130 
    </TR>
131 
    <TR>
132 
      <TD valign="middle" align="center">1</TD>
133 
      <TD valign="middle" align="center" bgcolor="#ffff00">Fetch &amp; Decode(Jump Detected)</TD>
134 
      <TD valign="middle" align="center"></TD>
135 
      <TD valign="middle" align="center"></TD>
136 
      <TD valign="middle" align="center"></TD>
137 
      <TD valign="middle" align="center"></TD>
138 
    </TR>
139 
    <TR>
140 
      <TD valign="middle" align="center">2</TD>
141 
      <TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
142 
      <TD valign="middle" align="center" bgcolor="#ffff00">Set Jump Address</TD>
143 
      <TD valign="middle" align="center"></TD>
144 
      <TD valign="middle" align="center"></TD>
145 
      <TD valign="middle" align="center"></TD>
146 
    </TR>
147 
    <TR>
148 
      <TD valign="middle" align="center">3</TD>
149 
      <TD valign="middle" align="center" bgcolor="#cccccc">Fetch &amp; Decode(Jumped Address)</TD>
150 
      <TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
151 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
152 
      <TD valign="middle" align="center"></TD>
153 
      <TD valign="middle" align="center"></TD>
154 
    </TR>
155 
    <TR>
156 
      <TD valign="middle" align="center">4</TD>
157 
      <TD valign="middle" align="center"></TD>
158 
      <TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
159 
      <TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
160 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
161 
      <TD valign="middle" align="center"></TD>
162 
    </TR>
163 
    <TR>
164 
      <TD valign="middle" align="center">5</TD>
165 
      <TD valign="middle" align="center"></TD>
166 
      <TD valign="middle" align="center"></TD>
167 
      <TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
168 
      <TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
169 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
170 
    </TR>
171 
    <TR>
172 
      <TD valign="middle" align="center">6</TD>
173 
      <TD valign="middle" align="center"></TD>
174 
      <TD valign="middle" align="center"></TD>
175 
      <TD valign="middle" align="center"></TD>
176 
      <TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
177 
      <TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
178 
    </TR>
179 
    <TR>
180 
      <TD valign="middle" align="center">7</TD>
181 
      <TD valign="middle" align="center"></TD>
182 
      <TD valign="middle" align="center"></TD>
183 
      <TD valign="middle" align="center"></TD>
184 
      <TD valign="middle" align="center"></TD>
185 
      <TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
186 
    </TR>
187 
    <TR>
188 
      <TD valign="middle" align="center">8</TD>
189 
      <TD valign="middle" align="center"></TD>
190 
      <TD valign="middle" align="center"></TD>
191 
      <TD valign="middle" align="center"></TD>
192 
      <TD valign="middle" align="center"></TD>
193 
      <TD valign="middle" align="center"></TD>
194 
    </TR>
195 
  </TBODY>
196 
</TABLE>
197 
<P>(3) &nbsp;Register Jump&nbsp;: -3 Clock Cycle</P>
198 
<P>&nbsp;Jump Address is not determined until Register File is read. This
199 
will result performance penalty.</P>
200 
<TABLE border="1">
201 
  <TBODY>
202 
    <TR>
203 
      <TH valign="middle" align="center">Time Slot</TH>
204 
      <TH valign="middle" align="center">Stage1</TH>
205 
      <TH valign="middle" align="center">Stage2</TH>
206 
      <TH valign="middle" align="center">Stage3</TH>
207 
      <TH valign="middle" align="center">Stage4</TH>
208 
      <TH valign="middle" align="center">Stage5</TH>
209 
    </TR>
210 
    <TR>
211 
      <TD valign="middle" align="center">&nbsp;</TD>
212 
      <TD valign="middle" align="center">Set Register File Address</TD>
213 
      <TD valign="middle" align="center">Read Register File<BR>
214 
      ALU_LEFT/Right Latch</TD>
215 
      <TD valign="middle" align="center">Mem Write<BR>
216 
      AReg&lt;=ALU</TD>
217 
      <TD valign="middle" align="center">Mem Read<BR>
218 
      NReg&lt;=AReg</TD>
219 
      <TD valign="middle" align="center">Write Register File<BR>
220 
      RReg&lt;=NReg</TD>
221 
    </TR>
222 
    <TR>
223 
      <TD valign="middle" align="center">1</TD>
224 
      <TD valign="middle" align="center" bgcolor="#ffff00">Fetch &amp; Decode(Register Jump Detected)</TD>
225 
      <TD valign="middle" align="center"></TD>
226 
      <TD valign="middle" align="center"></TD>
227 
      <TD valign="middle" align="center"></TD>
228 
      <TD valign="middle" align="center"></TD>
229 
    </TR>
230 
    <TR>
231 
      <TD valign="middle" align="center">2</TD>
232 
      <TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
233 
      <TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile&nbsp;</TD>
234 
      <TD valign="middle" align="center"></TD>
235 
      <TD valign="middle" align="center"></TD>
236 
      <TD valign="middle" align="center"></TD>
237 
    </TR>
238 
    <TR>
239 
      <TD valign="middle" align="center">3</TD>
240 
      <TD valign="middle" align="center" bgcolor="#00cc00">Fetch &amp; Decode</TD>
241 
      <TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
242 
      <TD valign="middle" align="center" bgcolor="#ffff00">Set Jump Address</TD>
243 
      <TD valign="middle" align="center"></TD>
244 
      <TD valign="middle" align="center"></TD>
245 
    </TR>
246 
    <TR>
247 
      <TD valign="middle" align="center">4</TD>
248 
      <TD valign="middle" align="center" bgcolor="#cccccc">Fetch &amp; Decode(Jumped Address)</TD>
249 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
250 
      <TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
251 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
252 
      <TD valign="middle" align="center"></TD>
253 
    </TR>
254 
    <TR>
255 
      <TD valign="middle" align="center">5</TD>
256 
      <TD valign="middle" align="center"></TD>
257 
      <TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
258 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
259 
      <TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
260 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
261 
    </TR>
262 
    <TR>
263 
      <TD valign="middle" align="center">6</TD>
264 
      <TD valign="middle" align="center"></TD>
265 
      <TD valign="middle" align="center"></TD>
266 
      <TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
267 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
268 
      <TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
269 
    </TR>
270 
    <TR>
271 
      <TD valign="middle" align="center">7</TD>
272 
      <TD valign="middle" align="center"></TD>
273 
      <TD valign="middle" align="center"></TD>
274 
      <TD valign="middle" align="center"></TD>
275 
      <TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
276 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
277 
    </TR>
278 
    <TR>
279 
      <TD valign="middle" align="center">8</TD>
280 
      <TD valign="middle" align="center"></TD>
281 
      <TD valign="middle" align="center"></TD>
282 
      <TD valign="middle" align="center"></TD>
283 
      <TD valign="middle" align="center"></TD>
284 
      <TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
285 
    </TR>
286 
  </TBODY>
287 
</TABLE>
288 
<P>
289 
<BR>
290 
</P>
291 
<P>(4) &nbsp;Branch with Branch commands&nbsp;: -4 Clock Cycle</P>
292 
<P>&nbsp;We can not set branch address until take is set. This will be big
293 
penalty in YACC. To improve this situation, branch prediction mechanism
294 
will be necessary. (Not implemented in YACC).</P>
295 
<TABLE border="1">
296 
  <TBODY>
297 
    <TR>
298 
      <TH valign="middle" align="center">Time Slot</TH>
299 
      <TH valign="middle" align="center">Stage1</TH>
300 
      <TH valign="middle" align="center">Stage2</TH>
301 
      <TH valign="middle" align="center">Stage3</TH>
302 
      <TH valign="middle" align="center">Stage4</TH>
303 
      <TH valign="middle" align="center">Stage5</TH>
304 
    </TR>
305 
    <TR>
306 
      <TD valign="middle" align="center">&nbsp;</TD>
307 
      <TD valign="middle" align="center">Set Register File Address</TD>
308 
      <TD valign="middle" align="center">Read Register File<BR>
309 
      ALU_LEFT/Right Latch</TD>
310 
      <TD valign="middle" align="center">Mem Write<BR>
311 
      AReg&lt;=ALU</TD>
312 
      <TD valign="middle" align="center">Mem Read<BR>
313 
      NReg&lt;=AReg</TD>
314 
      <TD valign="middle" align="center">Write Register File<BR>
315 
      RReg&lt;=NReg</TD>
316 
    </TR>
317 
    <TR>
318 
      <TD valign="middle" align="center">1</TD>
319 
      <TD valign="middle" align="center" bgcolor="#ffff00">Fetch &amp; Decode(Branch&nbsp;command Detected)</TD>
320 
      <TD valign="middle" align="center"></TD>
321 
      <TD valign="middle" align="center"></TD>
322 
      <TD valign="middle" align="center"></TD>
323 
      <TD valign="middle" align="center"></TD>
324 
    </TR>
325 
    <TR>
326 
      <TD valign="middle" align="center">2</TD>
327 
      <TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
328 
      <TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile&nbsp;</TD>
329 
      <TD valign="middle" align="center"></TD>
330 
      <TD valign="middle" align="center"></TD>
331 
      <TD valign="middle" align="center"></TD>
332 
    </TR>
333 
    <TR>
334 
      <TD valign="middle" align="center">3</TD>
335 
      <TD valign="middle" align="center" bgcolor="#00cc00">Fetch &amp; Decode</TD>
336 
      <TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
337 
      <TD valign="middle" align="center" bgcolor="#ffff00">Set Not&nbsp;Taken</TD>
338 
      <TD valign="middle" align="center"></TD>
339 
      <TD valign="middle" align="center"></TD>
340 
    </TR>
341 
    <TR>
342 
      <TD valign="middle" align="center">4</TD>
343 
      <TD valign="middle" align="center" bgcolor="#00cc00">Fetch &amp; Decode</TD>
344 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
345 
      <TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
346 
      <TD valign="middle" align="center" bgcolor="#ffff00">Set Branch Address</TD>
347 
      <TD valign="middle" align="center"></TD>
348 
    </TR>
349 
    <TR>
350 
      <TD valign="middle" align="center">5</TD>
351 
      <TD valign="middle" align="center" bgcolor="#cccccc">Fetch &amp; Decode(Branch Address)</TD>
352 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
353 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
354 
      <TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
355 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
356 
    </TR>
357 
    <TR>
358 
      <TD valign="middle" align="center">6</TD>
359 
      <TD valign="middle" align="center"></TD>
360 
      <TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
361 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
362 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
363 
      <TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
364 
    </TR>
365 
    <TR>
366 
      <TD valign="middle" align="center">7</TD>
367 
      <TD valign="middle" align="center"></TD>
368 
      <TD valign="middle" align="center"></TD>
369 
      <TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
370 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
371 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
372 
    </TR>
373 
    <TR>
374 
      <TD valign="middle" align="center">8</TD>
375 
      <TD valign="middle" align="center"></TD>
376 
      <TD valign="middle" align="center"></TD>
377 
      <TD valign="middle" align="center"></TD>
378 
      <TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
379 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
380 
    </TR>
381 
  </TBODY>
382 
</TABLE>
383 
<P>(5) &nbsp;Not Branch with Branch commands&nbsp;: -3 Clock Cycle</P>
384 
<P>&nbsp;After Taken is Not set, we understand PC is incremental.</P>
385 
<TABLE border="1">
386 
  <TBODY>
387 
    <TR>
388 
      <TH valign="middle" align="center">Time Slot</TH>
389 
      <TH valign="middle" align="center">Stage1</TH>
390 
      <TH valign="middle" align="center">Stage2</TH>
391 
      <TH valign="middle" align="center">Stage3</TH>
392 
      <TH valign="middle" align="center">Stage4</TH>
393 
      <TH valign="middle" align="center">Stage5</TH>
394 
    </TR>
395 
    <TR>
396 
      <TD valign="middle" align="center">&nbsp;</TD>
397 
      <TD valign="middle" align="center">Set Register File Address</TD>
398 
      <TD valign="middle" align="center">Read Register File<BR>
399 
      ALU_LEFT/Right Latch</TD>
400 
      <TD valign="middle" align="center">Mem Write<BR>
401 
      AReg&lt;=ALU</TD>
402 
      <TD valign="middle" align="center">Mem Read<BR>
403 
      NReg&lt;=AReg</TD>
404 
      <TD valign="middle" align="center">Write Register File<BR>
405 
      RReg&lt;=NReg</TD>
406 
    </TR>
407 
    <TR>
408 
      <TD valign="middle" align="center">1</TD>
409 
      <TD valign="middle" align="center" bgcolor="#ffff00">Fetch &amp; Decode(Branch&nbsp;command Detected)</TD>
410 
      <TD valign="middle" align="center"></TD>
411 
      <TD valign="middle" align="center"></TD>
412 
      <TD valign="middle" align="center"></TD>
413 
      <TD valign="middle" align="center"></TD>
414 
    </TR>
415 
    <TR>
416 
      <TD valign="middle" align="center">2</TD>
417 
      <TD valign="middle" align="center" bgcolor="#00cccc">Delayed Branch Command</TD>
418 
      <TD valign="middle" align="center" bgcolor="#ffff00">ReadRegisterFile&nbsp;</TD>
419 
      <TD valign="middle" align="center"></TD>
420 
      <TD valign="middle" align="center"></TD>
421 
      <TD valign="middle" align="center"></TD>
422 
    </TR>
423 
    <TR>
424 
      <TD valign="middle" align="center">3</TD>
425 
      <TD valign="middle" align="center" bgcolor="#00cc00">Fetch &amp; Decode</TD>
426 
      <TD valign="middle" align="center" bgcolor="#00cccc">ReadRegisterFile</TD>
427 
      <TD valign="middle" align="center" bgcolor="#ffff00">Set Not&nbsp;Taken</TD>
428 
      <TD valign="middle" align="center"></TD>
429 
      <TD valign="middle" align="center"></TD>
430 
    </TR>
431 
    <TR>
432 
      <TD valign="middle" align="center">4</TD>
433 
      <TD valign="middle" align="center" bgcolor="#cccccc">Fetch &amp; DecFetch (Not Branched Address)</TD>
434 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
435 
      <TD valign="middle" align="center" bgcolor="#00cccc">ALU</TD>
436 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
437 
      <TD valign="middle" align="center"></TD>
438 
    </TR>
439 
    <TR>
440 
      <TD valign="middle" align="center">5</TD>
441 
      <TD valign="middle" align="center"></TD>
442 
      <TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile&nbsp;</TD>
443 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
444 
      <TD valign="middle" align="center" bgcolor="#00cccc">MEM</TD>
445 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
446 
    </TR>
447 
    <TR>
448 
      <TD valign="middle" align="center">6</TD>
449 
      <TD valign="middle" align="center"></TD>
450 
      <TD valign="middle" align="center"></TD>
451 
      <TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
452 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
453 
      <TD valign="middle" align="center" bgcolor="#00cccc">WB</TD>
454 
    </TR>
455 
    <TR>
456 
      <TD valign="middle" align="center">7</TD>
457 
      <TD valign="middle" align="center"></TD>
458 
      <TD valign="middle" align="center"></TD>
459 
      <TD valign="middle" align="center"></TD>
460 
      <TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
461 
      <TD valign="middle" align="center" bgcolor="#00cc00">NOP</TD>
462 
    </TR>
463 
    <TR>
464 
      <TD valign="middle" align="center">8</TD>
465 
      <TD valign="middle" align="center"></TD>
466 
      <TD valign="middle" align="center"></TD>
467 
      <TD valign="middle" align="center"></TD>
468 
      <TD valign="middle" align="center"></TD>
469 
      <TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
470 
    </TR>
471 
  </TBODY>
472 
</TABLE>
473 
<P>(6) Interrupt -2 Clock Cycle</P>
474 
<P>In YACC interrupt is like jump command.To simplify the interrupt logic,Interrupt
475 
is inhibited during mul/div/jump/branch commands in YACC implementation.</P>
476 
<TABLE border="1">
477 
  <TBODY>
478 
    <TR>
479 
      <TH valign="middle" align="center">Time Slot</TH>
480 
      <TH valign="middle" align="center">Stage1</TH>
481 
      <TH valign="middle" align="center">Stage2</TH>
482 
      <TH valign="middle" align="center">Stage3</TH>
483 
      <TH valign="middle" align="center">Stage4</TH>
484 
      <TH valign="middle" align="center">Stage5</TH>
485 
    </TR>
486 
    <TR>
487 
      <TD valign="middle" align="center">&nbsp;</TD>
488 
      <TD valign="middle" align="center">Set Register File Address</TD>
489 
      <TD valign="middle" align="center">Read Register File<BR>
490 
      ALU_LEFT/Right Latch</TD>
491 
      <TD valign="middle" align="center">Mem Write<BR>
492 
      AReg&lt;=ALU</TD>
493 
      <TD valign="middle" align="center">Mem Read<BR>
494 
      NReg&lt;=AReg</TD>
495 
      <TD valign="middle" align="center">Write Register File<BR>
496 
      RReg&lt;=NReg</TD>
497 
    </TR>
498 
    <TR>
499 
      <TD valign="middle" align="center">1</TD>
500 
      <TD valign="middle" align="center" bgcolor="#ffff00">Fetch &amp; Decode(Interrupt)</TD>
501 
      <TD valign="middle" align="center"></TD>
502 
      <TD valign="middle" align="center"></TD>
503 
      <TD valign="middle" align="center"></TD>
504 
      <TD valign="middle" align="center"></TD>
505 
    </TR>
506 
    <TR>
507 
      <TD valign="middle" align="center">2</TD>
508 
      <TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
509 
      <TD valign="middle" align="center" bgcolor="#ffff00">Set Interrupt Address/<BR>
510 
      Save Returned Address</TD>
511 
      <TD valign="middle" align="center"></TD>
512 
      <TD valign="middle" align="center"></TD>
513 
      <TD valign="middle" align="center"></TD>
514 
    </TR>
515 
    <TR>
516 
      <TD valign="middle" align="center">3</TD>
517 
      <TD valign="middle" align="center" bgcolor="#cccccc">Fetch &amp; Decode(Interrupt Address)</TD>
518 
      <TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
519 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
520 
      <TD valign="middle" align="center"></TD>
521 
      <TD valign="middle" align="center"></TD>
522 
    </TR>
523 
    <TR>
524 
      <TD valign="middle" align="center">4</TD>
525 
      <TD valign="middle" align="center"></TD>
526 
      <TD valign="middle" align="center" bgcolor="#cccccc">ReadRegisterFile</TD>
527 
      <TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
528 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
529 
      <TD valign="middle" align="center"></TD>
530 
    </TR>
531 
    <TR>
532 
      <TD valign="middle" align="center">5</TD>
533 
      <TD valign="middle" align="center"></TD>
534 
      <TD valign="middle" align="center"></TD>
535 
      <TD valign="middle" align="center" bgcolor="#cccccc">ALU</TD>
536 
      <TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
537 
      <TD valign="middle" align="center" bgcolor="#ffff00"></TD>
538 
    </TR>
539 
    <TR>
540 
      <TD valign="middle" align="center">6</TD>
541 
      <TD valign="middle" align="center"></TD>
542 
      <TD valign="middle" align="center"></TD>
543 
      <TD valign="middle" align="center"></TD>
544 
      <TD valign="middle" align="center" bgcolor="#cccccc">MEM</TD>
545 
      <TD valign="middle" align="center" bgcolor="#cccc00">NOP</TD>
546 
    </TR>
547 
    <TR>
548 
      <TD valign="middle" align="center">7</TD>
549 
      <TD valign="middle" align="center"></TD>
550 
      <TD valign="middle" align="center"></TD>
551 
      <TD valign="middle" align="center"></TD>
552 
      <TD valign="middle" align="center"></TD>
553 
      <TD valign="middle" align="center" bgcolor="#cccccc">WB</TD>
554 
    </TR>
555 
    <TR>
556 
      <TD valign="middle" align="center">8</TD>
557 
      <TD valign="middle" align="center"></TD>
558 
      <TD valign="middle" align="center"></TD>
559 
      <TD valign="middle" align="center"></TD>
560 
      <TD valign="middle" align="center"></TD>
561 
      <TD valign="middle" align="center"></TD>
562 
    </TR>
563 
  </TBODY>
564 
</TABLE>
565 
<P>
566 
<BR>
567 
</P>
568 
</BODY>
569 
</HTML>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.