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[/] [yacc/] [trunk/] [rtl/] [altera/] [fifo512_cyclone_bb.v] - Blame information for rev 4

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1 2 tak.sugawa
//Copyright (C) 1991-2004 Altera Corporation
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//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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//support information,  device programming or simulation file,  and any other
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//associated  documentation or information  provided by  Altera  or a partner
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//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
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//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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//other  use  of such  megafunction  design,  netlist,  support  information,
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//device programming or simulation file,  or any other  related documentation
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//or information  is prohibited  for  any  other purpose,  including, but not
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//limited to  modification,  reverse engineering,  de-compiling, or use  with
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//any other  silicon devices,  unless such use is  explicitly  licensed under
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//a separate agreement with  Altera  or a megafunction partner.  Title to the
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//intellectual property,  including patents,  copyrights,  trademarks,  trade
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//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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//support  information,  device programming or simulation file,  or any other
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//related documentation or information provided by  Altera  or a megafunction
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//partner, remains with Altera, the megafunction partner, or their respective
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//licensors. No other licenses, including any licenses needed under any third
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//party's intellectual property, are provided herein.
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module fifo512_cyclone (
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        data,
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        wrreq,
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        rdreq,
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        clock,
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        q,
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        full,
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        empty);
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        input   [7:0]  data;
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        input     wrreq;
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        input     rdreq;
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        input     clock;
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        output  [7:0]  q;
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        output    full;
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        output    empty;
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endmodule
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