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//Copyright (C) 1991-2004 Altera Corporation

//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),

//support information,  device programming or simulation file,  and any other

//associated  documentation or information  provided by  Altera  or a partner

//under  Altera's   Megafunction   Partnership   Program  may  be  used  only

//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any

//other  use  of such  megafunction  design,  netlist,  support  information,

//device programming or simulation file,  or any other  related documentation

//or information  is prohibited  for  any  other purpose,  including, but not

//limited to  modification,  reverse engineering,  de-compiling, or use  with

//any other  silicon devices,  unless such use is  explicitly  licensed under

//a separate agreement with  Altera  or a megafunction partner.  Title to the

//intellectual property,  including patents,  copyrights,  trademarks,  trade

//secrets,  or maskworks,  embodied in any such megafunction design, netlist,

//support  information,  device programming or simulation file,  or any other

//related documentation or information provided by  Altera  or a megafunction

//partner, remains with Altera, the megafunction partner, or their respective

//licensors. No other licenses, including any licenses needed under any third

//party's intellectual property, are provided herein.

module ram_regfile32xx32 (

        data,

        wraddress,

        rdaddress_a,

        rdaddress_b,

        wren,

        clock,

        qa,

        qb);

        input   [31:0]  data;

        input   [4:0]  wraddress;

        input   [4:0]  rdaddress_a;

        input   [4:0]  rdaddress_b;

        input     wren;

        input     clock;

        output  [31:0]  qa;

        output  [31:0]  qb;

endmodule