OpenCores
URL https://opencores.org/ocsvn/yacc/yacc/trunk

Subversion Repositories yacc

[/] [yacc/] [trunk/] [rtl/] [decoder.v] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tak.sugawa
//Jun.28.2004
2
//Jun.30.2004 jump bug fix
3
//Jul.11.2004 target special zero 
4
//Jan.20.2005 apply @*
5
`include "define.h"
6
//`define ALTERA
7
module decoder(clock,sync_reset,MWriteD1,RegWriteD2,A_Right_SELD1,RF_inputD2,
8
RF_input_addr,M_signD1,M_signD2,M_access_modeD1,M_access_modeD2,
9
ALU_FuncD2,Shift_FuncD2,source_addrD1,target_addrD1,IMMD2,
10
source_addrD2,target_addrD2,Shift_amountD2,PC_commandD1,IMMD1,IRD1,takenD3,takenD2,beqQ,bneQ,blezQ,bgtzQ,
11
DAddress,PC,memory_indata,MOUT,IMM,branchQQ,jumpQ,int_req,clear_int,int_address,
12
A_Left_SELD1,RRegSelD1,MWriteD2,NOP_Signal,mul_alu_selD2,mul_div_funcD2,
13
pause_out,control_state,Shift_Amount_selD2,uread_port,int_stateD1,bgezQ,bltzQ,write_busy);
14
 
15
        input clock,sync_reset;
16
        input takenD3,takenD2;
17
        output MWriteD1,RegWriteD2;
18
        output [1:0] A_Right_SELD1;
19
        output [1:0] RF_inputD2;
20
        output M_signD1,M_signD2;
21
        output [1:0] M_access_modeD1,M_access_modeD2;
22
        output [3:0] ALU_FuncD2;
23
        output [1:0] Shift_FuncD2;
24
        output [25:0] IMMD2,IMMD1;
25
        output [4:0] source_addrD2,target_addrD2;
26
        output [4:0] source_addrD1,target_addrD1,Shift_amountD2;
27
        output [4:0] RF_input_addr;
28
        output [2:0] PC_commandD1;
29
        output [31:0] IRD1;
30
        output beqQ,bneQ,blezQ,bgtzQ;
31
        output bgezQ,bltzQ;
32
        input [7:0] uread_port;
33
        output int_stateD1;
34
        input write_busy;//Apr.2.2005
35
 
36
`ifdef RAM4K
37
        input  [11:0] DAddress,PC;
38
        input [11:0] int_address;
39
`else
40
        input  [25:0] DAddress,PC;
41
        input [25:0] int_address;
42
`endif
43
 
44
 
45
        input [31:0] memory_indata;
46
        output [31:0] MOUT;
47
        output [25:0] IMM;
48
        output branchQQ,jumpQ;
49
        input int_req;
50
        output clear_int;
51
 
52
        output  A_Left_SELD1;
53
        output [1:0] RRegSelD1;
54
        output MWriteD2;
55
        output NOP_Signal;
56
        output [1:0] mul_alu_selD2;
57
        output [3:0] mul_div_funcD2;
58
        input pause_out;
59
        output [7:0] control_state;
60
        output Shift_Amount_selD2;
61
//For Debug Use
62
        localparam [4:0] zero_=0,
63
                                     at_=1,
64
                                     v0_=2,
65
                                     v1_=3,
66
                                     a0_=4,
67
                                     a1_=5,
68
                                     a2_=6,
69
                                     a3_=7,
70
                                     t0_=8, t1_=9,t2_=10,t3_=11,t4_=12,t5_=13,t6_=14,t7_=15,
71
                                     s0_=16,s1_=17,s2_=18,s3_=19,s4_=20,s5_=21,s6_=22,s7_=23,t8_=24,t9_=25,
72
                                     k0_=26,k1_=27,gp_=28,sp_=29,s8_=30,ra_=31;
73
 
74
 
75
//regsiters
76
        reg [31:0] IRD1;
77
        reg [31:0] IRD2;
78
        reg [1:0] RF_input_addr_selD1;
79
        reg [4:0] RF_input_addr;
80
        reg [1:0] Shift_FuncD1,Shift_FuncD2;
81
        reg [3:0] ALU_FuncD2;
82
        reg [1:0] A_Right_SELD1;
83
        reg [1:0] RF_inputD2,RF_inputD1;
84
        reg [1:0] M_access_modeD1,M_access_modeD2;
85
        reg M_signD1,M_signD2;
86
 
87
        reg MWriteD1,RegWriteD2,RegWriteD1,MWriteD2;
88
        reg [2:0] PC_commandD1;
89
        reg beqQ,bneQ,blezQ,bgtzQ;
90
        reg bltzQ,bgezQ;//Jul.11.2004
91
        reg branchQ,branchQQ,jumpQ;
92
        reg [7:0] control_state;
93
        reg sync_resetD1;
94
        reg [31:0] memory_indataD2;
95
        reg  A_Left_SELD1;
96
        reg  [1:0] RRegSelD1;
97
        reg takenD4,takenD5;
98
        reg nop_bit;
99
        reg [1:0] mul_alu_selD2;
100
        reg mul_div_funcD1;
101
        reg div_mode_ff;
102
        reg [3:0] mul_div_funcD2;
103
        reg excuting_flag;
104
        reg excuting_flagD,excuting_flagDD;
105
        reg Shift_Amount_selD2;
106
        reg int_seqD1;
107
//wires                                 
108
        wire [31:0] IR;
109
 
110
        wire [5:0] opecode=IR[31:26];
111
        wire [5:0] opecodeD1=IRD1[31:26];
112
        wire [5:0] opefuncD1=IRD1[5:0];
113
        wire [5:0] opefunc=IR[5:0];
114
        wire [4:0] destination_addrD1;//Apr.8.2005
115
 
116
        wire NOP_Signal;
117
        wire finish_operation;
118
 
119
 
120
 
121
        assign int_stateD1=control_state==5;
122
 
123
        assign IMMD2=IRD2[25:0];
124
        assign IMMD1=IRD1[25:0];
125
        assign source_addrD2=IRD2[25:21];
126
        assign target_addrD2=IRD2[20:16];
127
        assign source_addrD1=IRD1[25:21];
128
        assign target_addrD1=IRD1[20:16];
129
        assign destination_addrD1=IRD1[15:11];
130
        assign Shift_amountD2=IRD2[10:6];
131
        assign IMM=IR[25:0];
132
 
133
`ifdef  Veritak //Disassenblar
134
        reg [30*8:1] inst;
135
        wire [5:0] op=IR[31:26];
136
        wire [25:0] bra=PC+{{10{IR[15]}},IR[15:0]}*4;//+4;
137
        wire [4:0] rs=IR[25:21];
138
        wire [4:0] rt=IR[20:16];
139
        wire [4:0] rd=IR[15:11];
140
        wire [4:0] sh=IR[10:6];
141
        reg [5*8:1] reg_name="abcd";
142
 
143
     reg [30*8:1] instD1,instD2;
144
 
145
        function [4*8:1] get_reg_name;
146
                input [4:0] field;
147
                begin
148
                        case (field)
149
                                0: get_reg_name="$z0";
150
                                1: get_reg_name="$at";
151
                                2: get_reg_name="$v0";
152
                                3: get_reg_name="$v1";
153
                                4: get_reg_name="$a0";
154
                                5: get_reg_name="$a1";
155
                                6: get_reg_name="$a2";
156
                                7: get_reg_name="$a3";
157
                                8,9,10,11,12,13,14,15:
158
                                   $sprintf(get_reg_name,"$t%1d",field-8);
159
                                16,17,18,19,20,21,22,23,24,25: $sprintf(get_reg_name,"$s%1d",field-16);
160
                                26:get_reg_name="$k0";
161
                                27:get_reg_name="$k1";
162
                                28:get_reg_name="$gp";
163
                                29:get_reg_name="$sp";
164
                                30:get_reg_name="$s8";
165
                                31:get_reg_name="$ra";
166
                        endcase
167
                end
168
        endfunction
169
 
170
        always @(posedge clock) begin
171
                instD1<=inst;
172
                instD2<=instD1;
173
        end
174
 
175
        always @*begin:sprintf //Jan.20.2005  @ (IR,op,bra,rs,rt,rd,sh) begin :sprintf
176
          reg [4*8:1] rdn;//Mar.15.2005 =get_reg_name(rd);//
177
          reg [4*8:1] rsn;//Mar.15.2005=get_reg_name(rs);
178
          reg [4*8:1] rtn;//Mar.15.2005 =get_reg_name(rt);
179
          rdn=get_reg_name(rd);
180
          rsn=get_reg_name(rs);
181
          rtn=get_reg_name(rt);
182
          case (op)
183
           0:
184
                case (IR[5:0])
185
                        0: if (rd==0 && rt==0 && rs==0 ) $sprintf(inst,"nop");
186
                           else $sprintf(inst,"sll %s,%s,%2d\n",rdn,rtn,sh);
187
                        2:
188
                                $sprintf(inst," srl %s,%s,%2d\n",rdn,rtn,sh);
189
 
190
                      3:
191
                                $sprintf(inst," sra %s,%s,%2d\n",rdn,rtn,sh);
192
 
193
                       4:
194
                                $sprintf(inst," sllv %s,%s,%s\n",rdn,rtn,rsn);
195
 
196
                       6:
197
                                $sprintf(inst," srlv %s,%s,%s\n",rdn,rtn,rsn);
198
 
199
                 7:
200
                        $sprintf(inst," srav %s,%s,%s\n",rdn,rtn,rsn);
201
 
202
                 8:
203
                        $sprintf(inst," jr %s\n",rsn);
204
 
205
                 9:
206
                        $sprintf(inst," jalr %s\n",rsn);
207
 
208
                 12:
209
                        $sprintf(inst," syscall\n");
210
 
211
                 13:
212
                        $sprintf(inst," break");
213
 
214
                 16:
215
                        $sprintf(inst," mfhi %s\n",rdn);
216
 
217
                 17:
218
                        $sprintf(inst," mthi %s\n",rsn);
219
 
220
                 18:
221
                        $sprintf(inst," mflo %s\n",rdn);
222
 
223
                 19:
224
                        $sprintf(inst," mtlo %s\n",rsn);
225
 
226
                 24:
227
                        $sprintf(inst," mult %s,%s\n",rsn,rtn);
228
 
229
                 25:
230
                        $sprintf(inst," multu %s,%s\n",rsn,rtn);
231
 
232
                 26:
233
                        $sprintf(inst," div %s,%s\n",rsn,rtn);
234
 
235
                 27:
236
                        $sprintf(inst," divu %s,%s\n",rsn,rtn);
237
 
238
                 32:
239
 
240
                        $sprintf(inst," add %s,%s,%s",rdn,rsn,rtn);
241
 
242
                 33:
243
                        if(rt==0)
244
                                $sprintf(inst," move %s,%s\n",rdn,rsn);
245
                        else
246
                                $sprintf(inst," addu %s,%s,%s\n",rdn,rsn,rtn);
247
 
248
                 34:
249
                        $sprintf(inst," sub %s,%s,%s\n",rdn,rsn,rtn);
250
 
251
                 35:
252
                        $sprintf(inst," subu %s,%s,%s\n",rdn,rsn,rtn);
253
 
254
                 36:
255
                        $sprintf(inst," and %s,%s,%s\n",rdn,rsn,rtn);
256
 
257
                 37:
258
                        if(rt==0)
259
                                $sprintf(inst," move %s,%s\n",rdn,rsn);
260
                         else
261
                                $sprintf(inst," or %s,%s,%s\n",rdn,rsn,rtn);
262
 
263
                 38:
264
                        $sprintf(inst," xor %s,%s,%s\n",rdn,rsn,rtn);
265
 
266
                 39:
267
                        $sprintf(inst," nor %s,%s,%s\n",rdn,rsn,rtn);
268
 
269
                 42:
270
                        $sprintf(inst," slt %s,%s,%s\n",rdn,rsn,rtn);
271
 
272
                 43:
273
                        $sprintf(inst," sltu %s,%s,%s\n",rdn,rsn,rtn);
274
 
275
                default:
276
                        $sprintf(inst,"Unknown Func. %08h\n",IR);
277
 
278
 
279
 
280
 
281
                endcase
282
            1:
283
                case (IR[20:16])
284
                 0:
285
                        $sprintf(inst," bltz %s,$%08h\n",rsn,bra);
286
 
287
                 1:
288
                        $sprintf(inst," bgez %s,$%08h\n",rsn,bra);
289
 
290
                 16:
291
                        $sprintf(inst," bltzal %s,$%08h\n",rsn,bra);
292
 
293
                 17:
294
                        $sprintf(inst," bgezal %s,$%08h\n",rsn,bra);
295
 
296
                default:
297
                        $sprintf(inst,"Unknown1 %08h\n",IR);
298
 
299
                endcase
300
 
301
         2:
302
                $sprintf(inst," j $%08h\n",((IR*4)&32'h0ffffffc)+(PC&32'hf0000000));
303
 
304
         3:
305
                $sprintf(inst," jal $%08h\n",((IR*4)&32'h0ffffffc)+(PC&32'hf0000000));
306
 
307
         4:
308
                if(rs==0 && rt==0)
309
                        $sprintf(inst," bra $%08h\n",bra);
310
                else
311
                        $sprintf(inst," beq %s,%s,$%08h\n",rsn,rtn,bra);
312
 
313
         5:
314
                $sprintf(inst," bne %s,%s,$%08h\n",rsn,rtn,bra);
315
 
316
         6:
317
                $sprintf(inst," blez %s,$%08h\n",rsn,bra);
318
 
319
         7:
320
                $sprintf(inst," bgtz %s,$%08h\n",rsn,bra);
321
 
322
         8:
323
                $sprintf(inst," addi %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
324
 
325
         9:
326
                if(rs==0)
327
                        $sprintf(inst," li %s,#$%08h\n",rtn,IR[15:0]);
328
                else
329
                        $sprintf(inst," addiu %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
330
 
331
         10:
332
                $sprintf(inst," slti %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
333
 
334
         11:
335
                $sprintf(inst," sltiu %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
336
 
337
         12:
338
                $sprintf(inst," andi %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
339
 
340
         13:
341
                if(rs==0)
342
                        $sprintf(inst," li %s,#$%08h\n",rtn,IR[15:0]);
343
                else
344
                        $sprintf(inst," ori %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
345
 
346
         14:
347
                $sprintf(inst," xori %s,%s,#$%04h\n",rtn,rsn,IR[15:0]);
348
 
349
         15://load upper immediate
350
 
351
                        $sprintf(inst," lui %s,#$%04h",rtn,IR[15:0]);
352
 
353
         16, 17, 18, 19: begin
354
                if(rs>=16)
355
                        $sprintf(inst," cop%d $%08h\n",op&3,IR[25:0]);
356
                 else
357
                case(rsn)
358
                 0:
359
                        $sprintf(inst," mfc%d %s,%s\n",op&3,rtn,rdn);
360
 
361
                 2:
362
                        $sprintf(inst," cfc%d %s,%s\n",op&3,rtn,rdn);
363
 
364
                 4:
365
                        $sprintf(inst," mtc%d %s,%s\n",op&3,rtn,rdn);
366
 
367
                 6:
368
                        $sprintf(inst," ctc%d %s,%s\n",op&3,rtn,rdn);
369
 
370
                 8, 12:
371
                        if(rt&1)
372
                                $sprintf(inst," bc%dt %d,%08h\n",op&3,rs*32+rt,bra);
373
                         else
374
                                $sprintf(inst," bc%df %d,%08h\n",op&3,rs*32+rt,bra);
375
 
376
 
377
                 default:
378
                        $sprintf(inst,"Unknown16 %08h\n",IR);
379
                 endcase
380
                end
381
         32:
382
                $sprintf(inst," lb %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
383
 
384
         33:
385
                $sprintf(inst," lh %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
386
 
387
         34:
388
                $sprintf(inst," lwl %s,$%04h(%s)\n",IR[15:0],rsn);
389
 
390
         35:
391
                $sprintf(inst," lw %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
392
 
393
         36:
394
                $sprintf(inst," lbu %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
395
 
396
         37:
397
                $sprintf(inst," lhu %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
398
 
399
         38:
400
                $sprintf(inst," lwr %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
401
 
402
         40:
403
                $sprintf(inst," sb %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
404
 
405
         41:
406
                $sprintf(inst," sh %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
407
 
408
         42:
409
                $sprintf(inst," swl %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
410
 
411
         43:
412
                $sprintf(inst," sw %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
413
 
414
         46:
415
                $sprintf(inst," swr %s,$%04h(%s)\n",rtn,IR[15:0],rsn);
416
 
417
         48, 49, 50, 51:
418
                $sprintf(inst," lwc%d %s,$%04h(%s)\n",op&3,rtn,IR[15:0],rsn);
419
 
420
         56, 57, 58, 59:
421
                $sprintf(inst," swc%d %s,$%04h(%s)\n",op&3,rtn,IR[15:0],rsn);
422
 
423
        default:
424
                $sprintf(inst,"UnknownOp %08h\n",IR);
425
 
426
 
427
 
428
 
429
        endcase
430
   end
431
 
432
 
433
`endif
434
//
435
                always @ (posedge clock)        sync_resetD1 <=sync_reset;
436
 
437
 
438
//IRD1
439
        always @ (posedge clock) begin
440
                if (sync_resetD1) IRD1 <=32'h00;
441
                else if ((control_state[5:0]==6'b00_0000 && int_req)  ) IRD1<=int_address>>2;
442
                else if (opecode==6'b000_001) IRD1<={IR[31:21],5'b00000,IR[15:0]};//Jul.11.2004 target ‚ªSpecial zero
443
                else IRD1 <=IR;
444
        end
445
 
446
//IRD2
447
        always @ (posedge clock) begin
448
          IRD2 <=IRD1;
449
        end
450
 
451
//RF_input_addr [4:0]
452
        always @ (posedge clock) begin
453
                 case (RF_input_addr_selD1)
454
                        `RF_Ert_sel: RF_input_addr <=target_addrD1;
455
                        `RF_Erd_sel: RF_input_addr <=destination_addrD1;
456
                        `RF_R15_SEL: RF_input_addr <=`Last_Reg;
457
                        `RF_INTR_SEL:RF_input_addr <=`Intr_Reg;
458
                         default   : RF_input_addr <=target_addrD1;
459
                     endcase
460
        end
461
 
462
//int_seqD1     
463
        always @(posedge clock) begin
464
                if (sync_reset) int_seqD1<=0;
465
                else  int_seqD1<=control_state[5:0]==6'b00_0000 && int_req;
466
 
467
        end
468
 
469
 
470
// [1:0] Shift_FuncD1,Shift_FuncD2;
471
        always @ (posedge clock) begin
472
                Shift_FuncD2<=Shift_FuncD1;
473
        end
474
 
475
// [3:0] ALU_FuncD1,ALU_FuncD2;
476
 
477
 
478
 
479
        always @ (posedge clock) begin
480
                M_access_modeD2<=M_access_modeD1;
481
        end
482
 
483
//M_signD1,M_signD2;
484
        always @ (posedge clock) begin
485
                M_signD2<=M_signD1;
486
        end
487
 
488
//takenD4
489
        always @ (posedge clock) begin
490
                if (sync_resetD1) takenD4<=1'b0;
491
                else if (NOP_Signal) takenD4<=1'b0;//TRY
492
                else                  takenD4<=takenD3;
493
        end
494
//takenD5
495
        always @ (posedge clock) begin
496
                if (sync_resetD1) takenD5<=1'b0;
497
                else              takenD5<=takenD4;
498
        end
499
//RegWriteD2,RegWriteD1;
500
        always @ (posedge clock) begin
501
                if (sync_resetD1) begin
502
                        RegWriteD2<=1'b0;
503
                end else if (takenD4 ||takenD5  || NOP_Signal ) RegWriteD2<=1'b0;//NOP
504
                else    RegWriteD2<=RegWriteD1;
505
 
506
        end
507
 
508
 
509
 
510
 
511
//Combination logics
512
//RegWrite;
513
        always @ (posedge clock) begin
514
                if (sync_resetD1)                          RegWriteD1<=1'b0;
515
                else if (control_state[5:0]==6'b00_0000 && int_req) RegWriteD1<=1'b1;
516
                else case (opecode)
517
                        `loadbyte_signed    :      RegWriteD1<=1'b1;
518
                   `loadbyte_unsigned :       RegWriteD1<=1'b1;
519
                   `loadword_signed    :       RegWriteD1<=1'b1;
520
                   `loadword_unsigned :      RegWriteD1<=1'b1;
521
                   `loadlong       :            RegWriteD1<=1'b1;
522
                        `jump_and_link_im:         RegWriteD1<=1'b1;
523
                        `andi             :        RegWriteD1<=1'b1;
524
                   `addi             :     RegWriteD1<=1'b1 ;
525
                        `addiu           :         RegWriteD1<=1'b1;
526
                    `ori              :            RegWriteD1<=1'b1;
527
                        `xori             :        RegWriteD1<=1'b1;
528
                        `lui              :               RegWriteD1<=1'b1;
529
                     `comp_im_signed    : RegWriteD1<=1'b1;
530
                      `comp_im_unsigned : RegWriteD1<=1'b1;
531
                        6'b00_0000:
532
                                         case (opefunc)
533
                                                        `divs: RegWriteD1<=1'b0;
534
                                                        `divu: RegWriteD1<=1'b0;
535
                                                        `muls: RegWriteD1<=1'b0;
536
                                                        `mulu: RegWriteD1<=1'b0;
537
                                                      default:   RegWriteD1<=1'b1;
538
                                         endcase
539
                        default:                   RegWriteD1<=1'b0;
540
                endcase
541
        end
542
//
543
        always @ (posedge clock) begin
544
                if (sync_resetD1)                          mul_div_funcD1<=1'b0;
545
                else if (control_state[5:0]==6'b00_0000 && int_req) mul_div_funcD1<=1'b0;
546
                else case (opecode)
547
 
548
                        6'b00_0000:
549
                                         case (opefunc)
550
                                                        `divs: begin
551
                                                                        mul_div_funcD1<=1'b1;
552
                                                                        div_mode_ff<=1'b1;
553
                                                                   end
554
                                                        `divu: begin
555
                                                                        mul_div_funcD1<=1'b1;
556
                                                                        div_mode_ff<=1'b1;
557
                                                                   end
558
                                                        `muls: begin
559
                                                                        mul_div_funcD1<=1'b1;
560
                                                                        div_mode_ff<=1'b0;
561
                                                                   end
562
                                                        `mulu: begin
563
                                                                        mul_div_funcD1<=1'b1;
564
                                                                        div_mode_ff<=1'b0;
565
                                                                    end
566
                                                      default:   mul_div_funcD1<=1'b0;
567
                                         endcase
568
                        default:                   mul_div_funcD1<=1'b0;
569
                endcase
570
        end
571
 
572
//mu_div_func
573
//mul_alu_selD2/excuting_flag
574
always @ (posedge clock) begin
575
                if (sync_resetD1)       begin
576
                                mul_div_funcD2 <=`mult_nothing;
577
                                mul_alu_selD2<=2'b00;
578
                end else if ( mul_div_funcD2 [3] ) mul_div_funcD2[3]<=1'b0;////
579
 
580
                else if( !NOP_Signal) //
581
                                case (opecodeD1)
582
                               6'b00_0000:
583
                                case   (opefuncD1)
584
                                `divs:  begin
585
                                                mul_div_funcD2<=`mult_signed_divide;
586
 
587
                                                end
588
                                `divu:  begin
589
                                                mul_div_funcD2<=`mult_divide;
590
                                                end
591
                         `muls: begin
592
                                                mul_div_funcD2<=`mult_signed_mult;
593
                                                end
594
                         `mulu: begin
595
                                                mul_div_funcD2<=`mult_mult;
596
                                                end
597
 
598
                                `mfhi : begin
599
                                                        if (!pause_out)mul_div_funcD2<=`mult_read_hi;
600
                                                        mul_alu_selD2<=`MUL_hi_SEL;
601
                                                   end
602
                                `mflo : begin
603
                                                        if(!pause_out) mul_div_funcD2<=`mult_read_lo;
604
                                                        mul_alu_selD2<=`MUL_lo_SEL;
605
                                                   end
606
                                 default:       begin
607
                                                        mul_div_funcD2 <=`mult_read_lo;
608
                                                mul_alu_selD2<=2'b00;
609
                                                end
610
                                endcase
611
                                default:              mul_alu_selD2<=2'b00;
612
                     endcase
613
 
614
end
615
 
616
always @ (posedge clock) begin
617
                if (sync_resetD1) excuting_flagD<=1'b0;
618
                else                  excuting_flagD<=excuting_flag;
619
end
620
 
621
always @ (posedge clock) begin
622
                if (sync_resetD1) excuting_flagDD<=1'b0;
623
                else                  excuting_flagDD<=excuting_flagD;
624
end
625
        assign finish_operation=excuting_flag && !pause_out;
626
 
627
 
628
//MWrite
629
        always @ (posedge clock) begin
630
                if (sync_resetD1)               MWriteD1<=1'b0;
631
 
632
                else case (opecode)
633
                        `storebyte:     MWriteD1<=1'b1;
634
                        `storeword:     MWriteD1<=1'b1;
635
                        `storelong:     MWriteD1<=1'b1;
636
                        default:        MWriteD1<=1'b0;
637
                     endcase
638
     end
639
 
640
        always @ (posedge clock) begin
641
                if (sync_resetD1)               MWriteD2<=1'b0;
642
                else if (  NOP_Signal ) MWriteD2<=1'b0;
643
                else                            MWriteD2<=MWriteD1;//taken NOP 
644
        end
645
 
646
 
647
//M_sign
648
        always @ (posedge clock) begin
649
                if (sync_resetD1)                           M_signD1<=`M_unsigned;
650
                else case (opecode)
651
                             `loadbyte_signed  :     M_signD1<=`M_signed;
652
                        `loadbyte_unsigned :   M_signD1<=`M_unsigned;
653
                        `loadword_signed  :     M_signD1<=`M_signed;
654
                        `loadword_unsigned :  M_signD1<=`M_unsigned;
655
                        `loadlong          :       M_signD1<=`M_unsigned;
656
                             `storebyte:                    M_signD1<=`M_unsigned;
657
                             `storeword:                    M_signD1<=`M_unsigned;
658
                        `storelong:                 M_signD1<=`M_unsigned;
659
                                default:                          M_signD1<=`M_unsigned;
660
                     endcase
661
        end
662
 
663
 
664
 
665
 
666
// [1:0] M_access_mode
667
        always @ (posedge clock) begin
668
                if (sync_resetD1)                         M_access_modeD1<=`LONG_ACCESS;
669
                else case (opecode)
670
                        `loadbyte_signed  :       M_access_modeD1<=`BYTE_ACCESS;
671
                   `loadbyte_unsigned :     M_access_modeD1<=`BYTE_ACCESS;
672
                   `loadword_signed  :       M_access_modeD1<=`WORD_ACCESS;
673
                   `loadword_unsigned :    M_access_modeD1<=`WORD_ACCESS;
674
                   `loadlong       :          M_access_modeD1<=`LONG_ACCESS;
675
                      `storebyte:                      M_access_modeD1<=`BYTE_ACCESS;
676
                        `storeword:                    M_access_modeD1<=`WORD_ACCESS;
677
                   `storelong:                 M_access_modeD1<=`LONG_ACCESS;
678
                        default:                             M_access_modeD1<=`LONG_ACCESS;
679
                     endcase
680
        end
681
 
682
 
683
 
684
 
685
// [2:0] RF_input Shift_Amount_sel
686
        always @ (posedge clock) begin
687
                if (sync_resetD1)               begin
688
                        RF_inputD2 <=`RF_ALU_sel;
689
                        Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
690
                end
691
             else if ((int_seqD1)  || NOP_Signal ) RF_inputD2<=`RF_PC_SEL;//Jul.7.2004
692
             else
693
                 case (opecodeD1)
694
                        `lui    :RF_inputD2     <=`SHIFT16_SEL;
695
                        `jump_and_link_im:      RF_inputD2<=`RF_PC_SEL;
696
 
697
                        6'b00_0000:
698
                                case   (opefuncD1)
699
                                     `jump_and_link_register : RF_inputD2<=`RF_PC_SEL;
700
                                           `lsl              :    begin
701
                                                                                 RF_inputD2<=`RF_Shifter_sel ;
702
                                                                                 Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
703
                                                                                end
704
                                                `sllv           :      begin
705
                                                                                  RF_inputD2<=`RF_Shifter_sel ;
706
                                                                                  Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
707
                                                                                 end
708
                                             `asr                    : begin
709
                                                                                    RF_inputD2<=`RF_Shifter_sel ;
710
                                                                                    Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
711
                                                                                 end
712
                                        `srav                    : begin
713
                                                                                    RF_inputD2<=`RF_Shifter_sel ;
714
                                                                                    Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
715
                                                                                 end
716
 
717
                                     `lsr                    :  begin
718
                                                                                     RF_inputD2<=`RF_Shifter_sel;
719
                                                                                     Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
720
                                                                                 end
721
                                                `srlv                    :  begin
722
                                                                                     RF_inputD2<=`RF_Shifter_sel;
723
                                                                                     Shift_Amount_selD2<=`SHIFT_AMOUNT_REG_SEL;
724
                                                                                 end
725
 
726
 
727
                                                `mfhi           :       RF_inputD2<=`RF_PC_SEL;
728
                                                `mflo           :       RF_inputD2<=`RF_PC_SEL;
729
                                        default              :      begin
730
                                                                        RF_inputD2<=`RF_ALU_sel;
731
                                                                        Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
732
                                                                        end
733
                                endcase
734
                        default: begin
735
                                                RF_inputD2<=`RF_ALU_sel;
736
                                                 Shift_Amount_selD2<=`SHIFT_AMOUNT_IMM_SEL;
737
                                        end
738
                     endcase
739
        end
740
 
741
 
742
//[1:0] A_Right_SEL
743
        always @ (posedge clock) begin
744
                 casex (opecode)
745
                        `storebyte:     A_Right_SELD1<=`A_RIGHT_ERT;
746
                        `storeword:     A_Right_SELD1<=`A_RIGHT_ERT;
747
                        `storelong:     A_Right_SELD1<=`A_RIGHT_ERT;
748
                        `andi     :     A_Right_SELD1<=`Imm_unsigned ;
749
                  `addi     :       A_Right_SELD1<=`Imm_signed  ;
750
                        `addiu    :     A_Right_SELD1<=`Imm_signed;
751
                  `ori      :         A_Right_SELD1<=`Imm_unsigned;
752
                        `xori     :     A_Right_SELD1<=`Imm_unsigned;
753
 
754
                        `beq         :          A_Right_SELD1<=`A_RIGHT_ERT;
755
                        `bgtz        :          A_Right_SELD1<=`A_RIGHT_ERT;
756
                        `blez        :          A_Right_SELD1<=`A_RIGHT_ERT;
757
                        `bne         :          A_Right_SELD1<=`A_RIGHT_ERT;
758
 
759
 
760
                        `comp_im_signed   : A_Right_SELD1<=`Imm_signed;
761
                        `comp_im_unsigned : A_Right_SELD1<=`Imm_signed;
762
 
763
                        //6'b00_0000:
764
                        6'b00_000?://Jul.11.2004 target select
765
                                case   (opefunc)
766
 
767
                                        default           : A_Right_SELD1<=`A_RIGHT_ERT;
768
                                endcase
769
                        default: A_Right_SELD1<=`Imm_signed;
770
                    endcase
771
        end
772
 
773
 
774
//Interim A_Left_SELD1RRegSelD1
775
        always @ (posedge clock) begin
776
                 case (opecode)
777
                        default: A_Left_SELD1<=0;//always Left_latch
778
                    endcase
779
        end
780
 
781
        always @ (posedge clock) begin
782
                if ((control_state[5:0]==6'b00__0000 && int_req)  )  RRegSelD1<=`NREG_SEL;//Jul.13.2004
783
                else case (opecode)
784
                            `loadbyte_signed  : RRegSelD1<=`MOUT_SEL;
785
                        `loadbyte_unsigned :    RRegSelD1<=`MOUT_SEL;
786
                        `loadword_signed  :     RRegSelD1<=`MOUT_SEL;
787
                        `loadword_unsigned :    RRegSelD1<=`MOUT_SEL;
788
                        `loadlong          :    RRegSelD1<=`MOUT_SEL;
789
                        default:                RRegSelD1<=`NREG_SEL;//Interim MULSEL
790
                  endcase
791
        end
792
 
793
// [3:0] ALU_Func[1:0] ;
794
        always @ (posedge clock) begin
795
 
796
                case (opecodeD1)
797
                                `andi    : ALU_FuncD2<=`ALU_AND;
798
                                `addi    : ALU_FuncD2<=`ALU_ADD  ;
799
                                `addiu  :  ALU_FuncD2<=`ALU_ADD;
800
                                `ori     : ALU_FuncD2<=`ALU_OR;
801
                                `xori    : ALU_FuncD2<=`ALU_XOR;
802
                                 `comp_im_signed     : ALU_FuncD2<=`ALU_LESS_THAN_SIGNED;
803
                         `comp_im_unsigned   : ALU_FuncD2<=`ALU_LESS_THAN_UNSIGNED;
804
                                6'b00_0000:
805
                                case   (opefuncD1)
806
                                        `add    : ALU_FuncD2<=`ALU_ADD ;
807
                                        `addu   :        ALU_FuncD2<=`ALU_ADD ;
808
                                `sub     : ALU_FuncD2<=`ALU_SUBTRACT;
809
                                        `subu   : ALU_FuncD2<=`ALU_SUBTRACT;
810
                                        `and     : ALU_FuncD2<=`ALU_AND;
811
                                        `nor     : ALU_FuncD2<=`ALU_NOR;
812
                                        `or      : ALU_FuncD2<=`ALU_OR;
813
                                        `xor     : ALU_FuncD2<=`ALU_XOR;
814
                               `comp_signed      : ALU_FuncD2<=`ALU_LESS_THAN_SIGNED;
815
                              `comp_unsigned     : ALU_FuncD2<=`ALU_LESS_THAN_UNSIGNED;
816
 
817
                                        default           : ALU_FuncD2<=`ALU_NOTHING;//Jul.6.2004 ALU_NOTHING;
818
                                endcase
819
                              default: ALU_FuncD2<=`ALU_NOTHING;//Jul.6.2004 ALU_NOTHING;
820
                endcase
821
        end
822
 
823
 
824
// [1:0] Shift_Func;
825
        always @ (posedge clock) begin
826
                 case (opecode)
827
                        6'b00_0000:
828
                                case   (opefunc)
829
                                        `lsl             : Shift_FuncD1<=`SHIFT_LEFT;
830
                                      `sllv         : Shift_FuncD1<=`SHIFT_LEFT;
831
                                `asr             : Shift_FuncD1<=`SHIFT_RIGHT_SIGNED;
832
                                        `srav           : Shift_FuncD1<=`SHIFT_RIGHT_SIGNED;
833
                                        `lsr             : Shift_FuncD1<=`SHIFT_RIGHT_UNSIGNED;
834
                                        `srlv           : Shift_FuncD1<=`SHIFT_RIGHT_UNSIGNED;
835
                                        default          : Shift_FuncD1<=`SHIFT_LEFT;//Jul.5.2004 `SHIFT_NOTHING;
836
                                endcase
837
                        default: Shift_FuncD1<=`SHIFT_LEFT;//Jul.5.2004`SHIFT_NOTHING;
838
                     endcase
839
        end
840
 
841
 
842
 
843
//RF_input_addr_sel
844
        always @ (posedge clock) begin
845
                 if ((control_state[5:0]==6'b00__0000 && int_req)  ) RF_input_addr_selD1<=`RF_INTR_SEL;
846
                 else
847
                 case (opecode)
848
                                `andi            : RF_input_addr_selD1<=`RF_Ert_sel;
849
                                `addi            : RF_input_addr_selD1<=`RF_Ert_sel;
850
                                `ori             : RF_input_addr_selD1<=`RF_Ert_sel;
851
                                `xori            : RF_input_addr_selD1<=`RF_Ert_sel;
852
                                `jump_and_link_im: RF_input_addr_selD1<=`RF_R15_SEL;
853
                                `lui             : RF_input_addr_selD1<=`RF_Ert_sel;
854
                                `comp_im_signed  : RF_input_addr_selD1<=`RF_Ert_sel;
855
                                `comp_im_unsigned: RF_input_addr_selD1<=`RF_Ert_sel;
856
                        6'b00_0000:
857
                                case   (opefunc)
858
                                        `jump_and_link_register: RF_input_addr_selD1<=`RF_R15_SEL;
859
 
860
                                        default          : RF_input_addr_selD1<=`RF_Erd_sel;
861
                                endcase
862
                        default: RF_input_addr_selD1<=`RF_Ert_sel;
863
                    endcase
864
        end
865
 
866
 
867
 
868
 
869
 
870
//PC_command decoder    
871
//      always @ (posedge clock) begin
872
        always @(opecode,control_state,int_req,opefunc,NOP_Signal,takenD3,takenD4) begin//Jul.2.2004    
873
                 if (takenD3 || takenD4)         PC_commandD1<=`PC_INC;//
874
                   else case (opecode)
875
 
876
                         6'b00_0000:
877
                                        case (opefunc)
878
                                        `jmp_register : PC_commandD1<=`PC_REG;
879
                                         default:         PC_commandD1<=`PC_INC;
880
                                        endcase
881
                         default      : PC_commandD1<=`PC_INC;
882
                endcase
883
        end
884
//unsuppurted command detector Jul.11.2004
885
       always @(posedge clock) begin
886
                case (opecode)
887
                        6'b000_001://Jul.11.2004 simple decode
888
                                case (IR[20:16])
889
 
890
                                        `bltzal  :begin
891
                                                        $display("unsupported command");
892
                                                        $stop;
893
                                                end
894
                                        `bgezal : begin
895
                                                        $display("unsupported command");
896
                                                        $stop;
897
                                                end
898
 
899
                                        `bltzall:begin
900
                                                        $display("unsupported command");
901
                                                        $stop;
902
                                                end
903
                                        `bltzl:begin
904
                                                        $display("unsupported command");
905
                                                        $stop;
906
                                                end
907
                                        `bgezall:begin
908
                                                        $display("unsupported command");
909
                                                        $stop;
910
                                                end
911
                                        `bgezl: begin
912
                                                        $display("unsupported command");
913
                                                        $stop;
914
                                                end
915
                                endcase
916
                endcase
917
 
918
 
919
        end
920
 
921
 
922
 
923
        always @ (posedge clock) begin
924
                   if ((control_state[5:0]==6'b00_0000 && int_req)  ) begin
925
                                                                jumpQ<=1'b1;
926
                                                              branchQ<=1'b0;////Jun.30.2004
927
                   end else if (takenD3)        begin
928
                                                                jumpQ<=1'b0;//inhibit jump at delayed slot2
929
                                                                branchQ<=1'b0;//TRY Jun.30.2004
930
                   end else
931
                     case (opecode)
932
                        `jump:                begin
933
                                                                jumpQ<=1'b1;
934
                                                                branchQ<=1'b0;//Jun.30.2004
935
                                                        end
936
                        `jump_and_link_im:      begin
937
                                                                 jumpQ<=1'b1;
938
                                                                 branchQ<=1'b0;//Jun.30.2004
939
                                                        end
940
                        `beq         :        begin
941
                                                                        jumpQ<=1'b0;//Jun.30.2004
942
                                                                        branchQ<=1'b1;
943
                                                                end
944
                        `bgtz        :        begin
945
                                                                        jumpQ<=1'b0;//Jun.30.2004
946
                                                                        branchQ<=1'b1;
947
                                                                end
948
                        `blez          :        begin
949
                                                                        jumpQ<=1'b0;//Jun.30.2004
950
                                                                        branchQ<=1'b1;
951
                                                                end
952
                  `bne           :              begin
953
                                                                        jumpQ<=1'b0;//Jun.30.2004
954
                                                                        branchQ<=1'b1;
955
                                                                end
956
                        6'b000_001://Jul.11.2004 simple decode
957
                                                begin
958
                                                                jumpQ<=1'b0;
959
                                                                branchQ<=1'b1;
960
                                                end
961
 
962
                         default      : begin
963
                                         jumpQ<=1'b0;
964
                                         branchQ<=1'b0;
965
                                        end
966
                     endcase
967
        end
968
 
969
         always @ (posedge clock) begin
970
                if (NOP_Signal) branchQQ<=1'b0;
971
                else branchQQ<=branchQ;
972
        end
973
 
974
 
975
 
976
//For Critical Path
977
        always @(posedge clock) begin
978
                if (sync_resetD1)    beqQ<=0;
979
                else  if ((control_state[5:0]==6'b00_0000 && int_req)  ) beqQ<=1'b0;
980
                else if (opecode==`beq) beqQ<=1'b1;
981
                else               beqQ<=1'b0;
982
        end
983
 
984
//Jul.11.2004 bltz
985
        always @(posedge clock) begin
986
                if (sync_resetD1)    bltzQ<=0;
987
                else  if ((control_state[5:0]==6'b00_0000 && int_req)  ) bltzQ<=1'b0;
988
                else if (opecode==6'b000_001 && IR[20:16]==`bltz) bltzQ<=1'b1;//Jul.13.2004
989
                else               bltzQ<=1'b0;
990
        end
991
//Jul.11.2004 bgez
992
        always @(posedge clock) begin
993
                if (sync_resetD1)    bgezQ<=0;
994
                else  if ((control_state[5:0]==6'b00_0000 && int_req)  ) bgezQ<=1'b0;
995
                else if (opecode==6'b000_0001 && IR[20:16]==`bgez) bgezQ<=1'b1;//Jul.13.2004
996
                else               bgezQ<=1'b0;
997
        end
998
 
999
 
1000
        always @(posedge clock) begin
1001
                if (sync_resetD1)     bgtzQ<=0;
1002
                else  if ((control_state[5:0]==6'b00_0000 && int_req)  ) bgtzQ<=1'b0;
1003
                else if (opecode==`bgtz) bgtzQ<=1'b1;
1004
                else                bgtzQ<=1'b0;
1005
        end
1006
        always @(posedge clock) begin
1007
                if (sync_resetD1)     blezQ<=0;
1008
                else  if ((control_state[5:0]==6'b00_0000 && int_req)   ) blezQ<=1'b0;
1009
                else if (opecode==`blez) blezQ<=1'b1;
1010
                else                blezQ<=1'b0;
1011
        end
1012
        always @(posedge clock) begin
1013
                if (sync_resetD1)    bneQ<=0;
1014
                else  if ((control_state[5:0]==6'b00_0000 && int_req)  ) bneQ<=1'b0;
1015
                else if (opecode==`bne) bneQ<=1'b1;
1016
                else               bneQ<=1'b0;
1017
        end
1018
 
1019
//
1020
        always @(posedge clock) begin
1021
                if (sync_resetD1)   begin
1022
 
1023
                                                 excuting_flag<=1'b0;//
1024
                end else
1025
                 begin
1026
                        if (!pause_out && excuting_flagDD) excuting_flag<=1'b0;
1027
                        else case (opecode)
1028
                                                6'b00_0000:
1029
                                                        case (opefunc)
1030
                                                                `divs:                   excuting_flag<=1'b1;
1031
                                                                `divu:                   excuting_flag<=1'b1;
1032
                                                        `muls:                   excuting_flag<=1'b1;
1033
                                                        `mulu:                   excuting_flag<=1'b1;
1034
                                                        endcase
1035
                              endcase
1036
                end
1037
        end
1038
 
1039
        always @(posedge clock) begin
1040
                if (sync_resetD1)   begin
1041
                                                 control_state<=6'b00_0000;
1042
                end else
1043
                 begin
1044
                        casex (control_state[5:0])
1045
                        6'b00_0000:
1046
                                begin
1047
                                        if(int_req) control_state<=6'b000_101;//
1048
                                        else
1049
                                                case (opecode)
1050
                                                `jump:                control_state<=6'b100_000;
1051
                                                `jump_and_link_im:    control_state<=6'b100_000;
1052
                                                `beq         :        control_state<=6'b110_000;
1053
                                                `bgtz        :        control_state<=6'b110_000;
1054
                                                `blez        :        control_state<=6'b110_000;
1055
                                        `bne         :        control_state<=6'b110_000;
1056
                                                6'b000_001:             control_state<=6'b110_000;//Jul.11.2004 Special Branch
1057
                                                6'b00_0000:
1058
                                                        case (opefunc)
1059
                                                        `jump_and_link_register: control_state<=6'b101_000;
1060
                                                        `jmp_register :          control_state<=6'b101_000;
1061
 
1062
                                                        `mfhi:                   if (excuting_flag) control_state<=8'b00_000_010;
1063
                                                        `mflo:                   if (excuting_flag) control_state<=8'b00_000_010;
1064
                                                        default:                       control_state<=6'b00_0000;//for safety
1065
                                                        endcase
1066
                                                endcase
1067
 
1068
 
1069
 
1070
                                end
1071
                        6'b???_101:     control_state<=6'b000_000;//interrupt_nop state
1072
                        6'b100_000:     control_state<=6'b000_000;//fixed_jump state
1073
                        6'b101_000:     control_state<=6'b001_100;//jump&link state
1074
                        6'b001_100:   control_state<=6'b000_000;//NOP2 state
1075
                        6'b110_000:     control_state<=6'b000_100;//delayed branch 
1076
                        6'b000_100:    `ifdef RAM4K//Priotiry Area 
1077
                                         if (takenD3)   control_state<=6'b001_100;//NOP1 state
1078
                                                else    case (opecode)
1079
                                                        `jump:                control_state<=6'b100_000;
1080
                                                        `jump_and_link_im:    control_state<=6'b100_000;
1081
                                                        `beq         :        control_state<=6'b110_000;
1082
                                                        `bgtz        :        control_state<=6'b110_000;
1083
                                                        `blez        :        control_state<=6'b110_000;
1084
                                                        `bne         :        control_state<=6'b110_000;
1085
                                                        6'b000_001:             control_state<=6'b110_000;//Jul.11.2004 Special Branch
1086
                                                        6'b00_0000:
1087
                                                                case (opefunc)
1088
                                                                `jump_and_link_register: control_state<=6'b101_000;
1089
                                                                `jmp_register :          control_state<=6'b101_000;
1090
                                                                `mfhi:                   if (excuting_flag) control_state<=8'b00_000_010;
1091
                                                                `mflo:                   if (excuting_flag) control_state<=8'b00_000_010;
1092
                                                                default:                       control_state<=6'b00_0000;//for safety
1093
                                                                endcase
1094
                                                        endcase
1095
                                        `else//Priority Speed
1096
                                                        case (opecode)
1097
                                                        `jump:          if (takenD3)    control_state<=6'b001_100;//NOP1 state      
1098
                                                                        else control_state<=6'b100_000;
1099
                                                        `jump_and_link_im:   if (takenD3)       control_state<=6'b001_100;//NOP1 state 
1100
                                                                             else control_state<=6'b100_000;
1101
                                                        `beq         :       if (takenD3)       control_state<=6'b001_100;//NOP1 state
1102
                                                                             else control_state<=6'b110_000;
1103
                                                        `bgtz        :       if (takenD3)       control_state<=6'b001_100;//NOP1 state
1104
                                                                             else control_state<=6'b110_000;
1105
                                                        `blez        :       if (takenD3)       control_state<=6'b001_100;//NOP1 state
1106
                                                                             else  control_state<=6'b110_000;
1107
                                                        `bne         :       if (takenD3)       control_state<=6'b001_100;//NOP1 state
1108
                                                                             else control_state<=6'b110_000;
1109
                                                        6'b000_001:          if (takenD3)       control_state<=6'b001_100;//NOP1 state
1110
                                                                             else control_state<=6'b110_000;//Jul.11.2004 Special Branch
1111
                                                        6'b00_0000:
1112
                                                                case (opefunc)
1113
                                                                `jump_and_link_register: if (takenD3)   control_state<=6'b001_100;//NOP1 state
1114
                                                                                         else control_state<=6'b101_000;
1115
                                                                `jmp_register :          if (takenD3)   control_state<=6'b001_100;//NOP1 state
1116
                                                                                         else control_state<=6'b101_000;
1117
                                                                `mfhi:                   if (excuting_flag) begin
1118
                                                                                          if (takenD3)  control_state<=6'b001_100;//NOP1 state 
1119
                                                                                          else control_state<=8'b00_000_010;
1120
                                                                                         end else if (takenD3)  control_state<=6'b001_100;//NOP1 state 
1121
                                                                `mflo:                   if (excuting_flag) begin
1122
                                                                                                if (takenD3)    control_state<=6'b001_100;//NOP1 state
1123
                                                                                                else  control_state<=8'b00_000_010;
1124
                                                                                         end else if (takenD3)  control_state<=6'b001_100;//NOP1 state
1125
 
1126
                                                                default:                 if (takenD3)   control_state<=6'b001_100;//NOP1 state
1127
                                                                                         else   control_state<=6'b00_0000;//for safety
1128
                                                                endcase
1129
                                                        default :        if (takenD3)   control_state<=6'b001_100;//NOP1 state  
1130
                                                        endcase
1131
 
1132
 
1133
                                        `endif
1134
                        6'b???_010:     case (control_state[7:6])
1135
                                                2'b00:   control_state<=8'b01_000_010;
1136
                                                2'b01:   if (!pause_out) control_state<=8'b11_000_010;//mul/div
1137
                                                2'b11:   control_state<=8'b10_000_010;
1138
                                                2'b10:   control_state<=8'b00_000_110;//NOP
1139
                                                default: control_state<=8'h00;
1140
                                              endcase
1141
                        6'b???_110:     control_state<=8'h01;//Jul.12.2004 PCC=save_pc;
1142
                        6'b???_001:   control_state<=8'h00;     //Jul.12.2004 MUL IDLE avoid interrupt                                  
1143
                        default:        control_state<=8'h00;//for safety       
1144
                 endcase
1145
                end
1146
        end
1147
 
1148
        assign clear_int=control_state[2:0]==3'b101;//Jul.12.2004 interrupt_nop_state
1149
 
1150
        always @(posedge clock) begin
1151
                if (sync_reset) nop_bit<=1'b0;
1152
                else if (6'b000_100==control_state[5:0] && !takenD3) nop_bit<=1'b0;//Not taken
1153
                else              nop_bit<=control_state[2];
1154
        end
1155
        assign NOP_Signal=nop_bit |  control_state[1];//Jul.7.2004 int_bit mul_bit
1156
 
1157
 
1158
         ram_module_altera
1159
 
1160
 
1161
 
1162
`ifdef RAM4K
1163
 
1164
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
1165
             .Paddr(PC[11:0]),.Daddr(DAddress[11:0]),.wren(MWriteD2),
1166
             .datain(memory_indata),.access_mode(M_access_modeD2),
1167
             .M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
1168
`endif
1169
`ifdef RAM16K
1170
 
1171
        ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
1172
             .Paddr(PC[13:0]),.Daddr(DAddress[13:0]),.wren(MWriteD2),
1173
             .datain(memory_indata),.access_mode(M_access_modeD2),
1174
             .M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
1175
 
1176
 
1177
 
1178
`endif
1179
 
1180
`ifdef RAM32K
1181
ram(.clock(clock),.sync_reset(sync_reset),.IR(IR),.MOUT(MOUT),
1182
             .Paddr(PC[14:0]),.Daddr(DAddress[14:0]),.wren(MWriteD2),
1183
             .datain(memory_indata),.access_mode(M_access_modeD2),
1184
             .M_signed(M_signD2),.uread_port(uread_port),.write_busy(write_busy));
1185
`endif
1186
 
1187
 
1188
 
1189
 
1190
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.