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[/] [yacc/] [trunk/] [rtl/] [mul_div_module5.v] - Blame information for rev 5

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//Jun.2.2004
//Jun.27.2004
//Jun.28.2004
//Jun.30.2004 mulfunc output bug fix
//                         still 16x16 sign extension
//Jul.2.2004  mul 32x32=>64bit w/ w/o sign
//Jul.2.2004  address MUL_WIDTH==1
//Jul.4.2004  input critical path : => add carry_ff;
//Jul.5.2004                             :=> less fanout 
//Jul.13.2004 signed mul bug fix
//Jul.15.2004 32/32 div 
//Jul.16.2004 diet
//Jul.17.2004 add `ifdef less path delay for interface port
//Apr.7.2005 ADDRESS to XILINX Specific problem 
//Apr.14.2005 Add Stratix2
 
// mul/div module
 
// a[31:0] /b[31:0]  =>  
//   mul_div_out[15:0]  <=a/b
//   mul_div_out[31:16] <=a%b
// No detection of overflow
// Algorithm
//  answer_reg = (answer_reg << 1);
// multout_reg<={sum,a_reg[31]};
//    if (multout_reg >= b_reg) {
//       answer_reg += 1;
//       multout_reg -= b_reg;
//    }
//    a_reg <= a_reg << 1;
`include "define.h"
module mul_div(clock,sync_reset,a,b,mul_div_out,mul_div_sign,mul_div_word,mul_div_mode,state,stop_state,mul_div_enable,lohi);
`ifdef RAM4K
 
         `ifdef XILINX
                parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
                // XILINX fails using ISE7.1 if MUL_WIDTH==1,2
                // if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
            // if MULWIDTH==2 synthesis fails;
            // MUL_WIDTH==16 shows good.
 
         `else
                        parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                        parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
         `endif
`else
        `ifdef XILINX
                parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
                // XILINX fails using ISE7.1 if MUL_WIDTH==1,2
                // if MULWIDTH==1 synthesis is possible but post synthesis simulation fails
                 // if MULWIDTH==2 synthesis fails;
             // MUL_WIDTH==16 shows good.
 
         `else
                `ifdef Stratix2
                                        parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                                        parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;
                        `else
                                        parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster
                                        parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;
                        `endif
                `endif
`endif
        input clock,sync_reset;
        input [31:0] a,b;
        input [7:0] state;
        input lohi;
        input mul_div_enable,mul_div_sign,mul_div_word,mul_div_mode;
        output stop_state;
        output [31:0] mul_div_out;
 
        reg [31:0] a_reg;
        reg [31:0] b_reg;
        reg [31:0] answer_reg;
 
        reg stop_state_reg;// For state control
        reg [5:0] counter;
        reg mul_div_sign_ff,mul_div_mode_ff;
        reg a31_latch,b31_latch;
        reg breg31;
//mult64
        wire [63:0] ab62={1'b0,a_reg[31]*breg31,62'h0};//Jul.5.2004
        wire [63:0] shift_a31=mul_div_sign_ff  ? ~{2'b0,a_reg[30:0],31'h0}+1'b1: {2'b0,a_reg[30:0],31'h0} ;//Jul.13.2004 Jul.2.2004
        wire [63:0] shift_b31=mul_div_sign_ff  ? ~{2'b0,b_reg[30:0],31'h0}+1'b1: {2'b0,b_reg[30:0],31'h0};//Jul.13.2004 Jul.2.2004
 
        wire [30:0] init_lower  =breg31*shift_a31[30:0] +a_reg[31]*shift_b31[30:0]+ab62[30:0];//Jul.5.2004
        wire [63:31] init_upper=breg31*shift_a31[63:31]+a_reg[31]*shift_b31[63:31]+ab62[63:31];//+carry;Jul.5.2004
        wire [63:0] init_val={init_upper,init_lower};
        wire [MUL_WIDTH+30    :0] mult32x4out_temp=a_reg[30:0]*b_reg[MUL_WIDTH-1:0];//Jul.5.2004           
        wire [MUL_WIDTH+31 :0] mult32x4out={1'b0,mult32x4out_temp};
        reg [63:0] mult64_reg;
        reg [31:0] multout_reg;
        wire [63:0] mult64_out;
        wire  [63:0] mult64=a_reg* b_reg;
        reg  [MUL_WIDTH+31-1+1 :0] mult32x4out_reg;
 
 
        wire finish_operation;
        wire pre_stop;
        wire [32:0] sum;
        wire [31:0] answer_inc;
        wire [31:0] aminus=-a;
        wire [31:0] div_out,div_out_tmp;
 
 
        wire mul_div_mode_w;
        reg mul_state_reg;
        reg div_msb_ff;
 
        assign mul_div_mode_w=pre_stop ? mul_div_mode: mul_div_mode_ff;
 
`ifdef RAM4K
//less area
 
        assign mul_div_out=!lohi ?  !mul_div_mode_ff ?  mult64_out[31:0] : div_out  :
                                          !mul_div_mode_ff ? mult64_out[63:32]  :       div_out;//Jul.16.2004   
 
        assign div_out_tmp=!lohi ? answer_reg: {div_msb_ff,multout_reg[31:1]};
        assign div_out= (!lohi && (a31_latch ^ b31_latch)  &&  mul_div_sign_ff) ||
                                           (lohi && mul_div_sign_ff && a31_latch) ? ~div_out_tmp+1'b1 : div_out_tmp;
 
`else
 
// faster
        reg [31:0] div_out_multout_latch,answer_reg_latch;//
 
        assign mul_div_out=!lohi ?  !mul_div_mode_ff ? mult64_out[31:0]   : answer_reg_latch  :
                                    !mul_div_mode_ff ? mult64_out[63:32]  : div_out_multout_latch;//Jul.16.2004 
 
 
 
        always @(posedge clock) begin
                if ( (a31_latch ^ b31_latch)  &&  mul_div_sign_ff)
                        answer_reg_latch<=~answer_reg+1'b1;
                else    answer_reg_latch<= answer_reg;
 
                if  ( mul_div_sign_ff && a31_latch)
                        div_out_multout_latch<=~{div_msb_ff,multout_reg[31:1]}+1'b1;
                else div_out_multout_latch<={div_msb_ff,multout_reg[31:1]};
 
 
        end
 
 
`endif
 
//mul64
        //mul_state 
        always @(posedge clock) begin
                 breg31<=b[31];
        end
        always @(posedge clock) begin
                mult32x4out_reg<=mult32x4out;
        end
 
//Jul.16.2004
        always @(posedge clock) begin
                if (sync_reset) mul_state_reg<=0;
                else if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) mul_state_reg<=1;
                else if (finish_operation) mul_state_reg<=0;
        end
 
        //mult64_reg multout_reg
        always @(posedge clock) begin
                if (mul_state_reg && counter==0 )begin
                                mult64_reg<=init_val;//Jul.13.2004 Jul.5.2004 Jul.4.2004
                end
                else
                        if (mul_state_reg) begin
                                                {mult64_reg,multout_reg[31:31-MUL_WIDTH+1]}<={{MUL_WIDTH {1'b0}},mult64_reg+mult32x4out_reg};
                                                multout_reg[31-MUL_WIDTH:0] <=multout_reg[31:MUL_WIDTH];
 
                //Division
                end  else if (pre_stop && counter==0 ) multout_reg<=0; //First
                else if (mul_div_mode_ff && stop_state_reg ) begin
                                if (sum[32]==1'b0) begin //if (a_reg >=b_reg)
                                        if (finish_operation) div_msb_ff<=sum[31];
                                                        multout_reg<={sum,a_reg[31]};
                                end else begin
                                        if (finish_operation) div_msb_ff<=multout_reg[31];
                                        multout_reg[0]<=a_reg[31];
                                        multout_reg[31:1] <=multout_reg[30:0];
                                end
                end
        end
 
        assign mult64_out={mult64_reg[31:0],multout_reg[31:0]};
//input FFs
 
        always @(posedge clock) begin
                if (sync_reset) begin
                        mul_div_sign_ff<=0;
                        mul_div_mode_ff<=0;
 
 
                end else if (pre_stop) begin
                        mul_div_sign_ff<=mul_div_sign;
                        a31_latch<=a[31];
                        b31_latch<=b[31];
                        mul_div_mode_ff<=mul_div_mode;
                end
        end
 
 
 
//state_machine
        assign pre_stop=mul_div_enable ;
        assign finish_operation=(mul_div_mode_ff && counter==32) || (mul_state_reg && counter==MUL_STATE_MSB) ;//Jul.2.2004
 
 
        always @(posedge clock) begin
                if (sync_reset) stop_state_reg <=0;
                else if (pre_stop && !stop_state_reg )  stop_state_reg<=1;
                else if (stop_state_reg && finish_operation) stop_state_reg<=0;
        end
 
        assign stop_state=stop_state_reg;
 
        always @(posedge clock) begin
                if (sync_reset) counter <=0;
                else if (!stop_state_reg) counter <=0;
                else if (stop_state_reg ) counter <=counter+1;
        end
 
//a_reg
        always @(posedge clock) begin
                if(mul_div_mode_w==`MUL_DIV_MUL_SEL && pre_stop)  a_reg <=a;//
                        else if(mul_div_mode_w !=`MUL_DIV_MUL_SEL )begin//
                        if (!stop_state_reg && !pre_stop) a_reg <=a_reg;//
                        else if (pre_stop && counter==0  ) begin //
                                if (mul_div_sign) begin//
                                        if (a[31])       a_reg <=aminus;//
                                                        else a_reg <=a;
                                end else  a_reg <=a;//
                        end else begin//div 
                                                        a_reg <={a_reg[30:0],1'b0};// a_reg <<=1;
                        end
 
                end
        end
 
//b_reg
        always @(posedge clock) begin
                if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL )      b_reg<={1'b0,b[30:0]};
                else if ( mul_state_reg) b_reg<=b_reg[31:MUL_WIDTH];
                                else if( mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
                        if (!stop_state_reg && !pre_stop ) b_reg <=b_reg;//
                        else if (pre_stop && counter==0 ) begin //
                                if (mul_div_sign) begin//
                                        if ( b[31])  b_reg <=-b[31:0];//
                                                        else  b_reg <=b[31:0];//
                                end else begin
                                        b_reg <=b[31:0];//
                                end
                        end else begin//div 
                                        b_reg <=b_reg;//;
                        end
                end
         end
 
//answer_reg
        always @(posedge clock) begin
 
                if (mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
                        if (!stop_state_reg && !pre_stop) answer_reg <=answer_reg;//
                        else if (pre_stop && counter==0  ) answer_reg<=0; //
                        else  begin//div 
                                if ( !sum[32] ) begin//
                                                if (finish_operation) answer_reg <=answer_inc;
                                                else answer_reg <={answer_inc[30:0],1'b0};   //Jun.7.2004  a_reg -= b_reg
                                end else begin
                                                if  (finish_operation ) begin
                                                        answer_reg <=answer_reg;
                                         end else answer_reg <={answer_reg[30:0],1'b0};   // answer_reg <<=1;
                                end
                        end
                end
         end
 
 
        assign sum={1'b0,multout_reg}+~{1'b0,b_reg}+1'b1;//
        assign answer_inc=answer_reg+1'b1;//Jun.7.2004
 
endmodule
 

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[/] [yacc/] [trunk/] [rtl/] [mul_div_module5.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	tak.sugawa	`//Jun.2.2004`
2			`//Jun.27.2004`
3			`//Jun.28.2004`
4			`//Jun.30.2004 mulfunc output bug fix`
5			`// still 16x16 sign extension`
6			`//Jul.2.2004 mul 32x32=>64bit w/ w/o sign`
7			`//Jul.2.2004 address MUL_WIDTH==1`
8			`//Jul.4.2004 input critical path : => add carry_ff;`
9			`//Jul.5.2004 :=> less fanout`
10			`//Jul.13.2004 signed mul bug fix`
11			`//Jul.15.2004 32/32 div`
12			`//Jul.16.2004 diet`
13			//Jul.17.2004 add `ifdef less path delay for interface port
14			`//Apr.7.2005 ADDRESS to XILINX Specific problem`
15			`//Apr.14.2005 Add Stratix2`
16
17			`// mul/div module`
18
19			`// a[31:0] /b[31:0] =>`
20			`// mul_div_out[15:0] <=a/b`
21			`// mul_div_out[31:16] <=a%b`
22			`// No detection of overflow`
23			`// Algorithm`
24			`// answer_reg = (answer_reg << 1);`
25			`// multout_reg<={sum,a_reg[31]};`
26			`// if (multout_reg >= b_reg) {`
27			`// answer_reg += 1;`
28			`// multout_reg -= b_reg;`
29			`// }`
30			`// a_reg <= a_reg << 1;`
31			`include "define.h"
32			`module mul_div(clock,sync_reset,a,b,mul_div_out,mul_div_sign,mul_div_word,mul_div_mode,state,stop_state,mul_div_enable,lohi);`
33			`ifdef RAM4K
34
35			`ifdef XILINX
36			`parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
37			`parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;`
38			`// XILINX fails using ISE7.1 if MUL_WIDTH==1,2`
39			`// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails`
40			`// if MULWIDTH==2 synthesis fails;`
41			`// MUL_WIDTH==16 shows good.`
42
43			`else
44			`parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
45			`parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;`
46			`endif
47			`else
48			`ifdef XILINX
49			`parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
50			`parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;`
51			`// XILINX fails using ISE7.1 if MUL_WIDTH==1,2`
52			`// if MULWIDTH==1 synthesis is possible but post synthesis simulation fails`
53			`// if MULWIDTH==2 synthesis fails;`
54			`// MUL_WIDTH==16 shows good.`
55
56			`else
57			`ifdef Stratix2
58			`parameter MUL_WIDTH=16;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
59			`parameter MUL_STATE_MSB=2;//should be 32/MUL_WIDTH-1+1;`
60			`else
61			`parameter MUL_WIDTH=1;//Must be 2,4,8,16 2=> less area less speed 16=> greater area but faster`
62			`parameter MUL_STATE_MSB=32;//should be 32/MUL_WIDTH-1+1;`
63			`endif
64			`endif
65			`endif
66			`input clock,sync_reset;`
67			`input [31:0] a,b;`
68			`input [7:0] state;`
69			`input lohi;`
70			`input mul_div_enable,mul_div_sign,mul_div_word,mul_div_mode;`
71			`output stop_state;`
72			`output [31:0] mul_div_out;`
73
74			`reg [31:0] a_reg;`
75			`reg [31:0] b_reg;`
76			`reg [31:0] answer_reg;`
77
78			`reg stop_state_reg;// For state control`
79			`reg [5:0] counter;`
80			`reg mul_div_sign_ff,mul_div_mode_ff;`
81			`reg a31_latch,b31_latch;`
82			`reg breg31;`
83			`//mult64`
84			`wire [63:0] ab62={1'b0,a_reg[31]*breg31,62'h0};//Jul.5.2004`
85			`wire [63:0] shift_a31=mul_div_sign_ff ? ~{2'b0,a_reg[30:0],31'h0}+1'b1: {2'b0,a_reg[30:0],31'h0} ;//Jul.13.2004 Jul.2.2004`
86			`wire [63:0] shift_b31=mul_div_sign_ff ? ~{2'b0,b_reg[30:0],31'h0}+1'b1: {2'b0,b_reg[30:0],31'h0};//Jul.13.2004 Jul.2.2004`
87
88			`wire [30:0] init_lower =breg31shift_a31[30:0] +a_reg[31]shift_b31[30:0]+ab62[30:0];//Jul.5.2004`
89			`wire [63:31] init_upper=breg31shift_a31[63:31]+a_reg[31]shift_b31[63:31]+ab62[63:31];//+carry;Jul.5.2004`
90			`wire [63:0] init_val={init_upper,init_lower};`
91			`wire [MUL_WIDTH+30 :0] mult32x4out_temp=a_reg[30:0]*b_reg[MUL_WIDTH-1:0];//Jul.5.2004`
92			`wire [MUL_WIDTH+31 :0] mult32x4out={1'b0,mult32x4out_temp};`
93			`reg [63:0] mult64_reg;`
94			`reg [31:0] multout_reg;`
95			`wire [63:0] mult64_out;`
96			`wire [63:0] mult64=a_reg* b_reg;`
97			`reg [MUL_WIDTH+31-1+1 :0] mult32x4out_reg;`
98
99
100			`wire finish_operation;`
101			`wire pre_stop;`
102			`wire [32:0] sum;`
103			`wire [31:0] answer_inc;`
104			`wire [31:0] aminus=-a;`
105			`wire [31:0] div_out,div_out_tmp;`
106
107
108			`wire mul_div_mode_w;`
109			`reg mul_state_reg;`
110			`reg div_msb_ff;`
111
112			`assign mul_div_mode_w=pre_stop ? mul_div_mode: mul_div_mode_ff;`
113
114			`ifdef RAM4K
115			`//less area`
116
117			`assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : div_out :`
118			`!mul_div_mode_ff ? mult64_out[63:32] : div_out;//Jul.16.2004`
119
120			`assign div_out_tmp=!lohi ? answer_reg: {div_msb_ff,multout_reg[31:1]};`
121			`assign div_out= (!lohi && (a31_latch ^ b31_latch) && mul_div_sign_ff) \|\|`
122			`(lohi && mul_div_sign_ff && a31_latch) ? ~div_out_tmp+1'b1 : div_out_tmp;`
123
124			`else
125
126			`// faster`
127			`reg [31:0] div_out_multout_latch,answer_reg_latch;//`
128
129			`assign mul_div_out=!lohi ? !mul_div_mode_ff ? mult64_out[31:0] : answer_reg_latch :`
130			`!mul_div_mode_ff ? mult64_out[63:32] : div_out_multout_latch;//Jul.16.2004`
131
132
133
134			`always @(posedge clock) begin`
135			`if ( (a31_latch ^ b31_latch) && mul_div_sign_ff)`
136			`answer_reg_latch<=~answer_reg+1'b1;`
137			`else answer_reg_latch<= answer_reg;`
138
139			`if ( mul_div_sign_ff && a31_latch)`
140			`div_out_multout_latch<=~{div_msb_ff,multout_reg[31:1]}+1'b1;`
141			`else div_out_multout_latch<={div_msb_ff,multout_reg[31:1]};`
142
143
144			`end`
145
146
147			`endif
148
149			`//mul64`
150			`//mul_state`
151			`always @(posedge clock) begin`
152			`breg31<=b[31];`
153			`end`
154			`always @(posedge clock) begin`
155			`mult32x4out_reg<=mult32x4out;`
156			`end`
157
158			`//Jul.16.2004`
159			`always @(posedge clock) begin`
160			`if (sync_reset) mul_state_reg<=0;`
161			else if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) mul_state_reg<=1;
162			`else if (finish_operation) mul_state_reg<=0;`
163			`end`
164
165			`//mult64_reg multout_reg`
166			`always @(posedge clock) begin`
167			`if (mul_state_reg && counter==0 )begin`
168			`mult64_reg<=init_val;//Jul.13.2004 Jul.5.2004 Jul.4.2004`
169			`end`
170			`else`
171			`if (mul_state_reg) begin`
172			`{mult64_reg,multout_reg[31:31-MUL_WIDTH+1]}<={{MUL_WIDTH {1'b0}},mult64_reg+mult32x4out_reg};`
173			`multout_reg[31-MUL_WIDTH:0] <=multout_reg[31:MUL_WIDTH];`
174
175			`//Division`
176			`end else if (pre_stop && counter==0 ) multout_reg<=0; //First`
177			`else if (mul_div_mode_ff && stop_state_reg ) begin`
178			`if (sum[32]==1'b0) begin //if (a_reg >=b_reg)`
179			`if (finish_operation) div_msb_ff<=sum[31];`
180			`multout_reg<={sum,a_reg[31]};`
181			`end else begin`
182			`if (finish_operation) div_msb_ff<=multout_reg[31];`
183			`multout_reg[0]<=a_reg[31];`
184			`multout_reg[31:1] <=multout_reg[30:0];`
185			`end`
186			`end`
187			`end`
188
189			`assign mult64_out={mult64_reg[31:0],multout_reg[31:0]};`
190			`//input FFs`
191
192			`always @(posedge clock) begin`
193			`if (sync_reset) begin`
194			`mul_div_sign_ff<=0;`
195			`mul_div_mode_ff<=0;`
196
197
198			`end else if (pre_stop) begin`
199			`mul_div_sign_ff<=mul_div_sign;`
200			`a31_latch<=a[31];`
201			`b31_latch<=b[31];`
202			`mul_div_mode_ff<=mul_div_mode;`
203			`end`
204			`end`
205
206
207
208			`//state_machine`
209			`assign pre_stop=mul_div_enable ;`
210			`assign finish_operation=(mul_div_mode_ff && counter==32) \|\| (mul_state_reg && counter==MUL_STATE_MSB) ;//Jul.2.2004`
211
212
213			`always @(posedge clock) begin`
214			`if (sync_reset) stop_state_reg <=0;`
215			`else if (pre_stop && !stop_state_reg ) stop_state_reg<=1;`
216			`else if (stop_state_reg && finish_operation) stop_state_reg<=0;`
217			`end`
218
219			`assign stop_state=stop_state_reg;`
220
221			`always @(posedge clock) begin`
222			`if (sync_reset) counter <=0;`
223			`else if (!stop_state_reg) counter <=0;`
224			`else if (stop_state_reg ) counter <=counter+1;`
225			`end`
226
227			`//a_reg`
228			`always @(posedge clock) begin`
229			if(mul_div_mode_w==`MUL_DIV_MUL_SEL && pre_stop) a_reg <=a;//
230			else if(mul_div_mode_w !=`MUL_DIV_MUL_SEL )begin//
231			`if (!stop_state_reg && !pre_stop) a_reg <=a_reg;//`
232			`else if (pre_stop && counter==0 ) begin //`
233			`if (mul_div_sign) begin//`
234			`if (a[31]) a_reg <=aminus;//`
235			`else a_reg <=a;`
236			`end else a_reg <=a;//`
237			`end else begin//div`
238			`a_reg <={a_reg[30:0],1'b0};// a_reg <<=1;`
239			`end`
240
241			`end`
242			`end`
243
244			`//b_reg`
245			`always @(posedge clock) begin`
246			if (pre_stop && mul_div_mode_w==`MUL_DIV_MUL_SEL ) b_reg<={1'b0,b[30:0]};
247			`else if ( mul_state_reg) b_reg<=b_reg[31:MUL_WIDTH];`
248			else if( mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
249			`if (!stop_state_reg && !pre_stop ) b_reg <=b_reg;//`
250			`else if (pre_stop && counter==0 ) begin //`
251			`if (mul_div_sign) begin//`
252			`if ( b[31]) b_reg <=-b[31:0];//`
253			`else b_reg <=b[31:0];//`
254			`end else begin`
255			`b_reg <=b[31:0];//`
256			`end`
257			`end else begin//div`
258			`b_reg <=b_reg;//;`
259			`end`
260			`end`
261			`end`
262
263			`//answer_reg`
264			`always @(posedge clock) begin`
265
266			if (mul_div_mode_w !=`MUL_DIV_MUL_SEL) begin//
267			`if (!stop_state_reg && !pre_stop) answer_reg <=answer_reg;//`
268			`else if (pre_stop && counter==0 ) answer_reg<=0; //`
269			`else begin//div`
270			`if ( !sum[32] ) begin//`
271			`if (finish_operation) answer_reg <=answer_inc;`
272			`else answer_reg <={answer_inc[30:0],1'b0}; //Jun.7.2004 a_reg -= b_reg`
273			`end else begin`
274			`if (finish_operation ) begin`
275			`answer_reg <=answer_reg;`
276			`end else answer_reg <={answer_reg[30:0],1'b0}; // answer_reg <<=1;`
277			`end`
278			`end`
279			`end`
280			`end`
281
282
283			`assign sum={1'b0,multout_reg}+~{1'b0,b_reg}+1'b1;//`
284			`assign answer_inc=answer_reg+1'b1;//Jun.7.2004`
285
286			`endmodule`
287