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[/] [yacc/] [trunk/] [rtl/] [ram_module_altera.v] - Blame information for rev 4

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Line No. Rev Author Line
1 2 tak.sugawa 
//Jun.29.2004 w0,w1,w2,w3 bug fix
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//Jun.30.2004 endian bug fix
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//Jul.1.2004 endian bug fix
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//Apr.2.2005 Change Port Address
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`include "define.h"
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`define COMB_MOUT
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`define COMB_MOUT_IR
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`define NO_SIGNED_MOUT
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module ram_module_altera(clock,sync_reset,IR,MOUT,Paddr,Daddr,wren,datain,access_mode,M_signed,
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         uread_port,write_busy);
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        input clock,sync_reset;
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        input wren;
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        input [31:0] datain;
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        input M_signed;
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        input [7:0] uread_port;
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        input write_busy;//Apr.2.2005
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`ifdef RAM32K
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        input [14:0] Paddr,Daddr;//4KB address
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        reg  [14:0] DaddrD;
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`endif
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`ifdef  RAM16K
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        input [13:0] Paddr,Daddr;//4KB address
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        reg  [13:0] DaddrD;
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`endif
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`ifdef RAM4K
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        input [11:0] Paddr,Daddr;//4KB address
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      reg  [11:0] DaddrD;
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`endif
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        output [31:0] IR;//Instrcuntion Register
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        output [31:0] MOUT;//data out
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        input [1:0] access_mode;
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        reg [31:0] IR;
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        reg [31:0] MOUT;
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        reg [1:0] access_modeD;
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        wire [7:0] a0,a1,a2,a3;
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        wire [7:0] b0,b1,b2,b3;
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        wire [7:0] dport0,dport1,dport2,dport3;
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        wire w0,w1,w2,w3;
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        wire uread_port_access=`UART_PORT_ADDRESS==Daddr;
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        reg  uread_access_reg;
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        assign dport0=datain[7:0] ;
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        assign dport1=access_mode !=`BYTE_ACCESS ? datain[15:8] : datain[7:0];
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        assign dport2=access_mode==`LONG_ACCESS ? datain[23:16] : datain[7:0];
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        assign dport3=access_mode==`LONG_ACCESS ? datain[31:24] :
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                      access_mode==`WORD_ACCESS ? datain[15:8]  : datain[7:0];
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`ifdef RAM32K
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ram8192x8_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
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                      .data_b(dport0),.address_b(Daddr[14:2]),.wren_b(w0),.clock(clock),
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                      .q_a(a0),.q_b(b0));
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ram8192x8_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
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                      .data_b(dport1),.address_b(Daddr[14:2]),.wren_b(w1),.clock(clock),
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                      .q_a(a1),.q_b(b1));
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ram8192x8_1  ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
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                      .data_b(dport2),.address_b(Daddr[14:2]),.wren_b(w2),.clock(clock),
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                      .q_a(a2),.q_b(b2));
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ram8192x8_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
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                      .data_b(dport3),.address_b(Daddr[14:2]),.wren_b(w3),.clock(clock),
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                      .q_a(a3),.q_b(b3));
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`endif
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`ifdef  RAM16K
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`ifdef ALTERA
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ram4096x8_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
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                      .data_b(dport0),.address_b(Daddr[13:2]),.wren_b(w0),.clock(clock),
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                      .q_a(a0),.q_b(b0));
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ram4096x8_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
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                      .data_b(dport1),.address_b(Daddr[13:2]),.wren_b(w1),.clock(clock),
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                      .q_a(a1),.q_b(b1));
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ram4092x8_1  ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
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                      .data_b(dport2),.address_b(Daddr[13:2]),.wren_b(w2),.clock(clock),
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                      .q_a(a2),.q_b(b2));
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ram4092x8_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[13:2]),
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                      .data_b(dport3),.address_b(Daddr[13:2]),.wren_b(w3),.clock(clock),
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                      .q_a(a3),.q_b(b3));
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`else
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                ram1k3 ram0(.addra(Paddr[13:2]),
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                      .dinb(dport0),.addrb(Daddr[13:2]),.web(w0),.clka(clock),.clkb(clock),
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                      .douta(a0),.doutb(b0));
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                ram1k2 ram1(.addra(Paddr[13:2]),
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                      .dinb(dport1),.addrb(Daddr[13:2]),.web(w1),.clka(clock),.clkb(clock),
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                      .douta(a1),.doutb(b1));
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                ram1k1 ram2(.addra(Paddr[13:2]),
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                      .dinb(dport2),.addrb(Daddr[13:2]),.web(w2),.clka(clock),.clkb(clock),
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                      .douta(a2),.doutb(b2));
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                ram1k0 ram3(.addra(Paddr[13:2]),
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                      .dinb(dport3),.addrb(Daddr[13:2]),.web(w3),.clka(clock),.clkb(clock),
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                      .douta(a3),.doutb(b3));
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`endif
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`endif
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`ifdef RAM4K
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ram_1k_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
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                      .data_b(dport0),.address_b(Daddr[11:2]),.wren_b(w0),.clock(clock),
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                      .q_a(a0),.q_b(b0));
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ram_1k_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
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                      .data_b(dport1),.address_b(Daddr[11:2]),.wren_b(w1),.clock(clock),
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                      .q_a(a1),.q_b(b1));
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ram_1k_1 ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
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                      .data_b(dport2),.address_b(Daddr[11:2]),.wren_b(w2),.clock(clock),
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                      .q_a(a2),.q_b(b2));
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ram_1k_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
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                      .data_b(dport3),.address_b(Daddr[11:2]),.wren_b(w3),.clock(clock),
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                      .q_a(a3),.q_b(b3));
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`endif
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        wire temp=( access_mode==`BYTE_ACCESS &&  Daddr[1:0]==2'b00);
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        assign w3= wren &&
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                   (  access_mode==`LONG_ACCESS ||
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                   (  access_mode==`WORD_ACCESS && !Daddr[1]    ) ||
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                   (  access_mode==`BYTE_ACCESS &&  Daddr[1:0]==2'b00));
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        assign w2= wren &&
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                   (  access_mode==`LONG_ACCESS ||
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                   (  access_mode==`WORD_ACCESS && !Daddr[1])  ||
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                   ( Daddr[1:0]==2'b01));
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        assign w1= wren &&
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                   (  access_mode==`LONG_ACCESS ||
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                   (  access_mode==`WORD_ACCESS && Daddr[1]) ||
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                   (  Daddr[1:0]==2'b10));
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        assign w0= wren &&
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                   (  access_mode==`LONG_ACCESS ||
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                   (  access_mode==`WORD_ACCESS && Daddr[1]) ||
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                   (  Daddr[1:0]==2'b11));
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//IR
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`ifdef COMB_MOUT_IR
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        always @(*) IR={a3,a2,a1,a0};
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`else
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        always @(posedge clock) begin
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                if (sync_reset)      IR <=0;
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                else  IR <={a3,a2,a1,a0};
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        end
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`endif
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        always @(posedge clock) begin
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                if (access_modeD==`LONG_ACCESS) begin
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                                if(uread_access_reg) begin
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                                                        MOUT <={23'h00_0000,write_busy,uread_port};
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                                end else
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                                                        MOUT <={b3,b2,b1,b0};
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                end else if (access_modeD==`WORD_ACCESS) begin
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                     case (DaddrD[1])
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                                                1'b0: if(M_signed) MOUT <={{16{b3[7]}},b3,b2};//Jul.1.2004
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                                                      else MOUT <={16'h0000,b3,b2};
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                                                1'b1: if(M_signed) MOUT <={{16{b1[7]}},b1,b0};//Jul.1.2004
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                                                      else MOUT <={16'h0000,b1,b0};
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                     endcase
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                end else  begin//BYTE ACCESSS
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                        case (DaddrD[1:0])
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                                                        2'b00:if(M_signed) MOUT <={{24{b3[7]}},b3};
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                                                                                else MOUT <={16'h0000,8'h00,b3};
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                                                2'b01:if(M_signed) MOUT <={{24{b2[7]}},b2};
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                                                                    else MOUT <={16'h0000,8'h00,b2};
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                                                        2'b10:if(M_signed) MOUT <={{24{b1[7]}},b1};
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                                                                          else MOUT <={16'h0000,8'h00,b1};
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                                                        2'b11:if(M_signed) MOUT <={{24{b0[7]}},b0};
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                                                                                else MOUT <={16'h0000,8'h00,b0};
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                        endcase
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                end
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        end
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        always @(posedge clock) begin
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                access_modeD<=access_mode;
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                DaddrD<=Daddr;
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                uread_access_reg<=uread_port_access;//Jul.7.2004
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        end
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endmodule
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