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[/] [yacc/] [trunk/] [rtl/] [uart_read.v] - Blame information for rev 4

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`include "define.h"
 
 
 
 
 
module  uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
        input sync_reset;
        input   clk, rxd;
        output  [7:0] buffer_reg;
        output  int_req;
 
 
//________|-|______int_req (This module,, posedge interrupt)
//
//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...
//
//No error handling (overrun ) is supported.
 
        reg             rxq1;
        reg             [8:0] clk_ctr;
        reg             [2:0] bit_ctr;
        reg             [2:0] ua_state;
        reg             [7:0] rx_sr;             //.,tx_sr;
        reg             int_req;
        reg             [7:0] buffer_reg;
 
        wire     clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,
                           clk_ctr_enable_state, bit_ctr_enable_state  ;
        wire    clk_ctr_equ0;
 
 
 
 
//sync_reset
 
//synchronization
        always @(posedge clk ) begin
                rxq1 <=rxd ;
        end
 
// 7bit counter
        always @(posedge clk ) begin
                if (sync_reset)
                        clk_ctr <= 0;
                else if (clk_ctr_enable_state && clk_ctr_equ31)  clk_ctr<=0;
                else if (clk_ctr_enable_state)                   clk_ctr <= clk_ctr + 1;
                else    clk_ctr <= 0;
        end
        assign  clk_ctr_equ15 =  (clk_ctr==`COUNTER_VALUE1)  ;//
        assign  clk_ctr_equ31 =  (clk_ctr==`COUNTER_VALUE2) ;//
        assign  clk_ctr_equ0=    (clk_ctr==`COUNTER_VALUE3);    //
 
 
        // 3bit counter
        always @(posedge clk) begin
                if (sync_reset)
                        bit_ctr <= 0;
                else if (bit_ctr_enable_state) begin
                        if (clk_ctr_equ15)
                                bit_ctr <= bit_ctr + 1;
                end
                else
                        bit_ctr <= 0;
        end
 
        assign  bit_ctr_equ7 = (bit_ctr==7);
 
 
        assign  clk_ctr_enable_state =  ua_state !=3'b000  && ua_state<=3'b011;
        assign  bit_ctr_enable_state = ua_state==3'h2;
 
//      
        always @(posedge clk ) begin
                if (sync_reset) ua_state <= 3'h0;
                else begin
                        case (ua_state)
                                3'h0:   if (rxq1==0) ua_state <= 3'h1;  // if rxd==0 then goto next state and enable clock                                               // start bit search
                                3'h1:   if (clk_ctr_equ15) ua_state <= 3'h2;                                    // start bit receive
                                3'h2:   if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;
                                3'h3:   if (clk_ctr_equ15)     ua_state <=3'h4;                                                                 // stop bit receive
                                3'h4:   ua_state <= 3'b000;
                                default: ua_state <= 3'b000;
                        endcase
                end
        end
 
 
//reg_we
        always @(posedge clk ) begin
                if (sync_reset)                            buffer_reg<=8'h00;
                else if (ua_state==3'h3 && clk_ctr_equ0)  buffer_reg<=rx_sr;
        end
 
//int_req
        always @(posedge clk ) begin
                if (sync_reset)                             int_req<=1'b0;
                else if (ua_state==3'h4 )   int_req<=1'b1;      //
                else                                        int_req<=1'b0;
        end
 
 
// rx shift reg.
        always @(posedge clk ) begin
                if (sync_reset) rx_sr <= 0;
                else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	tak.sugawa	`include "define.h"
2
3
4
5
6
7			`module uart_read( sync_reset, clk, rxd,buffer_reg, int_req);`
8			`input sync_reset;`
9			`input clk, rxd;`
10			`output [7:0] buffer_reg;`
11			`output int_req;`
12
13
14			`//________\|-\|______int_req (This module,, posedge interrupt)`
15			`//`
16			`//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time...`
17			`//`
18			`//No error handling (overrun ) is supported.`
19
20			`reg rxq1;`
21			`reg [8:0] clk_ctr;`
22			`reg [2:0] bit_ctr;`
23			`reg [2:0] ua_state;`
24			`reg [7:0] rx_sr; //.,tx_sr;`
25			`reg int_req;`
26			`reg [7:0] buffer_reg;`
27
28			`wire clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7,`
29			`clk_ctr_enable_state, bit_ctr_enable_state ;`
30			`wire clk_ctr_equ0;`
31
32
33
34
35			`//sync_reset`
36
37			`//synchronization`
38			`always @(posedge clk ) begin`
39			`rxq1 <=rxd ;`
40			`end`
41
42			`// 7bit counter`
43			`always @(posedge clk ) begin`
44			`if (sync_reset)`
45			`clk_ctr <= 0;`
46			`else if (clk_ctr_enable_state && clk_ctr_equ31) clk_ctr<=0;`
47			`else if (clk_ctr_enable_state) clk_ctr <= clk_ctr + 1;`
48			`else clk_ctr <= 0;`
49			`end`
50			assign clk_ctr_equ15 = (clk_ctr==`COUNTER_VALUE1) ;//
51			assign clk_ctr_equ31 = (clk_ctr==`COUNTER_VALUE2) ;//
52			assign clk_ctr_equ0= (clk_ctr==`COUNTER_VALUE3); //
53
54
55			`// 3bit counter`
56			`always @(posedge clk) begin`
57			`if (sync_reset)`
58			`bit_ctr <= 0;`
59			`else if (bit_ctr_enable_state) begin`
60			`if (clk_ctr_equ15)`
61			`bit_ctr <= bit_ctr + 1;`
62			`end`
63			`else`
64			`bit_ctr <= 0;`
65			`end`
66
67			`assign bit_ctr_equ7 = (bit_ctr==7);`
68
69
70			`assign clk_ctr_enable_state = ua_state !=3'b000 && ua_state<=3'b011;`
71			`assign bit_ctr_enable_state = ua_state==3'h2;`
72
73			`//`
74			`always @(posedge clk ) begin`
75			`if (sync_reset) ua_state <= 3'h0;`
76			`else begin`
77			`case (ua_state)`
78			`3'h0: if (rxq1==0) ua_state <= 3'h1; // if rxd==0 then goto next state and enable clock // start bit search`
79			`3'h1: if (clk_ctr_equ15) ua_state <= 3'h2; // start bit receive`
80			`3'h2: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;`
81			`3'h3: if (clk_ctr_equ15) ua_state <=3'h4; // stop bit receive`
82			`3'h4: ua_state <= 3'b000;`
83			`default: ua_state <= 3'b000;`
84			`endcase`
85			`end`
86			`end`
87
88
89			`//reg_we`
90			`always @(posedge clk ) begin`
91			`if (sync_reset) buffer_reg<=8'h00;`
92			`else if (ua_state==3'h3 && clk_ctr_equ0) buffer_reg<=rx_sr;`
93			`end`
94
95			`//int_req`
96			`always @(posedge clk ) begin`
97			`if (sync_reset) int_req<=1'b0;`
98			`else if (ua_state==3'h4 ) int_req<=1'b1; //`
99			`else int_req<=1'b0;`
100			`end`
101
102
103			`// rx shift reg.`
104			`always @(posedge clk ) begin`
105			`if (sync_reset) rx_sr <= 0;`
106			`else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};`
107			`end`
108
109			`endmodule`

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[/] [yacc/] [trunk/] [rtl/] [uart_read.v] - Blame information for rev 4