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// megafunction wizard: %RAM: 3-PORT%

// GENERATION: STANDARD

// VERSION: WM1.0

// MODULE: alt3pram 

// ============================================================

// File Name: ram_regfile32xx32.v

// Megafunction Name(s):

//                      alt3pram

// ============================================================

// ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition

// ************************************************************

//Copyright (C) 1991-2005 Altera Corporation

//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),

//support information,  device programming or simulation file,  and any other

//associated  documentation or information  provided by  Altera  or a partner

//under  Altera's   Megafunction   Partnership   Program  may  be  used  only

//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any

//other  use  of such  megafunction  design,  netlist,  support  information,

//device programming or simulation file,  or any other  related documentation

//or information  is prohibited  for  any  other purpose,  including, but not

//limited to  modification,  reverse engineering,  de-compiling, or use  with

//any other  silicon devices,  unless such use is  explicitly  licensed under

//a separate agreement with  Altera  or a megafunction partner.  Title to the

//intellectual property,  including patents,  copyrights,  trademarks,  trade

//secrets,  or maskworks,  embodied in any such megafunction design, netlist,

//support  information,  device programming or simulation file,  or any other

//related documentation or information provided by  Altera  or a megafunction

//partner, remains with Altera, the megafunction partner, or their respective

//licensors. No other licenses, including any licenses needed under any third

//party's intellectual property, are provided herein.

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module ram_regfile32xx32 (

        data,

        wraddress,

        rdaddress_a,

        rdaddress_b,

        wren,

        clock,

        qa,

        qb);

        input   [31:0]  data;

        input   [4:0]  wraddress;

        input   [4:0]  rdaddress_a;

        input   [4:0]  rdaddress_b;

        input     wren;

        input     clock;

        output  [31:0]  qa;

        output  [31:0]  qb;

        wire [31:0] sub_wire0;

        wire [31:0] sub_wire1;

        wire [31:0] qa = sub_wire0[31:0];

        wire [31:0] qb = sub_wire1[31:0];

        alt3pram        alt3pram_component (

                                .wren (wren),

                                .inclock (clock),

                                .data (data),

                                .rdaddress_a (rdaddress_a),

                                .wraddress (wraddress),

                                .rdaddress_b (rdaddress_b),

                                .qa (sub_wire0),

                                .qb (sub_wire1)

                                // synopsys translate_off

                                ,

                                .aclr (),

                                .inclocken (),

                                .outclock (),

                                .outclocken (),

                                .rden_a (),

                                .rden_b ()

                                // synopsys translate_on

                                );

        defparam

                alt3pram_component.intended_device_family = "Cyclone",

                alt3pram_component.width = 32,

                alt3pram_component.widthad = 5,

                alt3pram_component.indata_reg = "INCLOCK",

                alt3pram_component.write_reg = "INCLOCK",

                alt3pram_component.rdaddress_reg_a = "INCLOCK",

                alt3pram_component.rdaddress_reg_b = "INCLOCK",

                alt3pram_component.rdcontrol_reg_a = "UNREGISTERED",

                alt3pram_component.rdcontrol_reg_b = "UNREGISTERED",

                alt3pram_component.outdata_reg_a = "UNREGISTERED",

                alt3pram_component.outdata_reg_b = "UNREGISTERED",

                alt3pram_component.indata_aclr = "OFF",

                alt3pram_component.write_aclr = "OFF",

                alt3pram_component.rdaddress_aclr_a = "OFF",

                alt3pram_component.rdaddress_aclr_b = "OFF",

                alt3pram_component.rdcontrol_aclr_a = "OFF",

                alt3pram_component.rdcontrol_aclr_b = "OFF",

                alt3pram_component.outdata_aclr_a = "OFF",

                alt3pram_component.outdata_aclr_b = "OFF",

                alt3pram_component.lpm_type = "alt3pram",

                alt3pram_component.lpm_hint = "USE_EAB=ON";

endmodule

// ============================================================

// CNX file retrieval info

// ============================================================

// Retrieval info: PRIVATE: WidthData NUMERIC "32"

// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"

// Retrieval info: PRIVATE: Clock NUMERIC "0"

// Retrieval info: PRIVATE: rden_a NUMERIC "0"

// Retrieval info: PRIVATE: rden_b NUMERIC "0"

// Retrieval info: PRIVATE: REGdata NUMERIC "1"

// Retrieval info: PRIVATE: REGwrite NUMERIC "1"

// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1"

// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1"

// Retrieval info: PRIVATE: REGrren_a NUMERIC "0"

// Retrieval info: PRIVATE: REGrren_b NUMERIC "0"

// Retrieval info: PRIVATE: REGqa NUMERIC "0"

// Retrieval info: PRIVATE: REGqb NUMERIC "0"

// Retrieval info: PRIVATE: enable NUMERIC "0"

// Retrieval info: PRIVATE: CLRdata NUMERIC "0"

// Retrieval info: PRIVATE: CLRwrite NUMERIC "0"

// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0"

// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0"

// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0"

// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0"

// Retrieval info: PRIVATE: CLRqa NUMERIC "0"

// Retrieval info: PRIVATE: CLRqb NUMERIC "0"

// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"

// Retrieval info: PRIVATE: MIFfilename STRING ""

// Retrieval info: PRIVATE: UseLCs NUMERIC "0"

// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"

// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"

// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"

// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"

// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

// Retrieval info: CONSTANT: WIDTH NUMERIC "32"

// Retrieval info: CONSTANT: WIDTHAD NUMERIC "5"

// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK"

// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK"

// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK"

// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK"

// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED"

// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED"

// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"

// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"

// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF"

// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF"

// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF"

// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF"

// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF"

// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF"

// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF"

// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF"

// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram"

// Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON"

// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]

// Retrieval info: USED_PORT: qa 0 0 32 0 OUTPUT NODEFVAL qa[31..0]

// Retrieval info: USED_PORT: qb 0 0 32 0 OUTPUT NODEFVAL qb[31..0]

// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]

// Retrieval info: USED_PORT: rdaddress_a 0 0 5 0 INPUT NODEFVAL rdaddress_a[4..0]

// Retrieval info: USED_PORT: rdaddress_b 0 0 5 0 INPUT NODEFVAL rdaddress_b[4..0]

// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren

// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0

// Retrieval info: CONNECT: qa 0 0 32 0 @qa 0 0 32 0

// Retrieval info: CONNECT: qb 0 0 32 0 @qb 0 0 32 0

// Retrieval info: CONNECT: @wraddress 0 0 5 0 wraddress 0 0 5 0

// Retrieval info: CONNECT: @rdaddress_a 0 0 5 0 rdaddress_a 0 0 5 0

// Retrieval info: CONNECT: @rdaddress_b 0 0 5 0 rdaddress_b 0 0 5 0

// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0

// Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0

// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.v TRUE

// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.inc FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.cmp FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.bsf FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_inst.v FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_bb.v TRUE