Subversion Repositories yacc

# Copyright (C) 1991-2005 Altera Corporation

# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),

# support information,  device programming or simulation file,  and any other

# associated  documentation or information  provided by  Altera  or a partner

# under  Altera's   Megafunction   Partnership   Program  may  be  used  only

# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any

# other  use  of such  megafunction  design,  netlist,  support  information,

# device programming or simulation file,  or any other  related documentation

# or information  is prohibited  for  any  other purpose,  including, but not

# limited to  modification,  reverse engineering,  de-compiling, or use  with

# any other  silicon devices,  unless such use is  explicitly  licensed under

# a separate agreement with  Altera  or a megafunction partner.  Title to the

# intellectual property,  including patents,  copyrights,  trademarks,  trade

# secrets,  or maskworks,  embodied in any such megafunction design, netlist,

# support  information,  device programming or simulation file,  or any other

# related documentation or information provided by  Altera  or a megafunction

# partner, remains with Altera, the megafunction partner, or their respective

# licensors. No other licenses, including any licenses needed under any third

# party's intellectual property, are provided herein.

# The default values for assignments are stored in the file

#               yacc_assignment_defaults.qdf

# If this file doesn't exist, and for assignments not listed, see file

#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus II software

# and any changes you make may be lost or overwritten.

# Project-Wide Assignments

# ========================

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.2 SP1"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:15:56  APRIL 09, 2005"

set_global_assignment -name LAST_QUARTUS_VERSION "4.2 SP1"

set_global_assignment -name VERILOG_FILE ram_regfile32xx32.v

set_global_assignment -name VERILOG_FILE fifo512_cyclone.v

set_global_assignment -name VERILOG_FILE ram4092x8_0.v

set_global_assignment -name VERILOG_FILE ram4092x8_1.v

set_global_assignment -name VERILOG_FILE ram4096x8_2.v

set_global_assignment -name VERILOG_FILE ram4096x8_3.v

set_global_assignment -name VERILOG_FILE ../../rtl/yacc2.v

set_global_assignment -name VERILOG_FILE ../../rtl/alu.v

set_global_assignment -name VERILOG_FILE ../../rtl/decoder.v

set_global_assignment -name VERILOG_FILE ../../rtl/mul_div_module5.v

set_global_assignment -name VERILOG_FILE ../../rtl/pc_module.v

set_global_assignment -name VERILOG_FILE ../../rtl/pipelined_rfile.v

set_global_assignment -name VERILOG_FILE ../../rtl/ram_module_altera.v

set_global_assignment -name VERILOG_FILE ../../rtl/shifter.v

set_global_assignment -name VERILOG_FILE ../../rtl/uart_read.v

set_global_assignment -name VERILOG_FILE ../../rtl/uart_write_cyclone.v

# Pin & Location Assignments

# ==========================

set_location_assignment PIN_240 -to Async_Reset

set_location_assignment PIN_28 -to clock

set_location_assignment PIN_113 -to RXD

set_location_assignment PIN_114 -to TXD

# Timing Assignments

# ==================

set_global_assignment -name IGNORE_CLOCK_SETTINGS ON

set_global_assignment -name FMAX_REQUIREMENT "100.0 MHz"

# Analysis & Synthesis Assignments

# ================================

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST

set_global_assignment -name FAMILY Cyclone

set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON

set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON

set_global_assignment -name TOP_LEVEL_ENTITY yacc

set_global_assignment -name USER_LIBRARIES "F:\\yacc\\syn\\altera"

# Fitter Assignments

# ==================

set_global_assignment -name DEVICE EP1C12Q240C6

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

set_global_assignment -name FITTER_EFFORT "FAST FIT"

set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# EDA Netlist Writer Assignments

# ==============================

set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"

# ---------------------------------------

# start EDA_TOOL_SETTINGS(eda_simulation)

        # EDA Netlist Writer Assignments

        # ==============================

        set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation

        set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)

# -------------------------------------