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[/] [yacc/] [trunk/] [syn/] [altra_stratix2/] [define.h] - Blame information for rev 2

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//Jul.11.2004
 
`define LONG_ACCESS 2'b00
`define WORD_ACCESS 2'b01
`define BYTE_ACCESS 2'b10
 
 
 
//Shift
 
//`define SHIFT_NOTHING 2'b00
`define SHIFT_LEFT 2'b01
`define SHIFT_RIGHT_UNSIGNED 2'b10
`define SHIFT_RIGHT_SIGNED 2'b11
 
//ALU
`define   ALU_NOTHING 4'b0000
`define   ALU_ADD     4'b0001
`define   ALU_SUBTRACT 4'b0010
`define   ALU_LESS_THAN_UNSIGNED 4'b0101 //Jul.5.2004
`define   ALU_LESS_THAN_SIGNED   4'b0100 //Jul.5.2004
`define   ALU_OR  4'b0011
`define   ALU_AND 4'b0110
`define   ALU_XOR 4'b0111
`define   ALU_NOR 4'b1000
//`define   ALU_NOR 4'b0000 //Jul.6.2004
 
//PC
`define    PC_INC   3'b000
`define    PC_HOLD  3'b001
`define    PC_IMM   3'b010
`define    PC_IMM_PLUS 3'b011
`define    PC_REG 3'b100
//`define    FLAG_SEL 3'b101
`define    PC_FLAG_SEL16 3'b101
`define    PC_DEC 3'b110
 
//ALU Right SEL
`define    Imm_signed  2'b00
`define    Imm_unsigned 2'b01
`define    A_RIGHT_ERT  2'b10
`define    IMM_26_SEL   2'b11
 
//ALU_LEFT_SEL
`define    PC_SEL 1'b1
 
//Shift amount Sel
`define   A_sel 1'b0
`define   Ers_d2_sel
 
//Memory_Signed_extenstion
`define M_unsigned 1'b0
`define M_signed   1'b1
 
//RRegSel
`define MOUT_SEL 2'b00
`define NREG_SEL 2'b01
 
//AREG ALU/MUL_SEL
//2'b00 => ALU_SEL 
`define MUL_hi_SEL  2'b10
`define MUL_lo_SEL  2'b11
 
//RF_INPUT SEL
`define RF_ALU_sel 2'b00
`define RF_Shifter_sel 2'b01
`define RF_PC_SEL       2'b010
`define SHIFT16_SEL 2'b11
 
//MUX
//`define STRAIGHT  2'b00
//`define AREG_SEL 2'b01
//`define RREG_SEL 2'b11
 
 
//RF INPUT ADDRESS
`define RF_Ert_sel 2'b00
`define RF_Erd_sel 2'b01
`define RF_R15_SEL 2'b10
`define RF_INTR_SEL 2'b11
 
`define Last_Reg 31
`define Intr_Reg 26 // Jul.7.2004 TRY FOR OS,, Use R26 as Interrput Return address.
//OPCODE
 
`define add  6'b100000
`define addu 6'b100001
`define addi 6'b001000
`define addiu 6'b001001
`define sub  6'b100010
`define subu 6'b100011
 
`define and  6'b100100
`define andi 6'b001100
`define nor  6'b100111
`define or   6'b100101
`define ori  6'b001101
 
`define lsl  6'b000000
`define asr  6'b000011
`define lsr  6'b000010
`define sllv 6'b000100
`define srav 6'b000111
`define srlv 6'b000110
 
`define xor  6'b100110
`define xori 6'b001110
 
`define lui  6'b001111
 
 
 
`define comp_signed             6'b101010
`define comp_unsigned           6'b101011  //Jun.29.2004    
`define comp_im_signed          6'b001010
`define comp_im_unsigned        6'b001011  //Jun.29.2004    
 
`define beq   6'b000100
`define bgtz  6'b000111
`define blez  6'b000110
`define bne   6'b000101
 
//opecode "000001" =>   [20:16] Special Opecode
`define bltzal  5'b10000  //unsupported
`define bltz 5'b00000
`define bgezal 5'b10001  //unsupported�@
`define bgez    5'b00001
`define bltzall 5'b10010 //unsupprted
`define bltzl   5'b00010 //unsupported
`define bgezall 5'b10011 //unsupported
`define bgezl   5'b00011 //unsupported
 
`define jump                    6'b000010
`define jump_and_link_im        6'b000011
`define jump_and_link_register  6'b001001
`define jmp_register            6'b001000
 
//Load Instructions      
 
`define loadbyte_signed         6'b100000
`define loadbyte_unsigned       6'b100100
`define loadword_signed         6'b100001
`define loadword_unsigned       6'b100101
`define loadlong                    6'b100011
 
//Store Instructions
 
`define storebyte  6'b101000
`define storeword  6'b101001
`define storelong  6'b101011
 
//Exception and Interrupt Instructions      
 
`define softwave_interrupt  6'b011010
`define divs    6'b011010
`define divu    6'b011011
`define muls    6'b011000
`define mulu    6'b011001
 
`define mfhi    6'b010000
`define mflo    6'b010010
 
`define MUL_DIV_WORD_ACCESS 1'b1
`define MUL_DIV_BYTE_ACCESS 1'b0
`define MUL_DIV_MUL_SEL 1'b0
 
 
`define mult_nothing   4'b0000
`define mult_read_lo   4'b0000
`define mult_read_hi   4'b0001
`define mult_write_lo  4'b0011
`define mult_write_hi  4'b0100
`define mult_mult      4'b1000
`define mult_signed_mult   4'b1010
`define mult_divide        4'b1100
`define mult_signed_divide 4'b1110
 
`define SHIFT_AMOUNT_IMM_SEL 1'b0
`define SHIFT_AMOUNT_REG_SEL 1'b1
 
 
//`define RAM4K
`define RAM16K
//`define RAM32K
 
 
 
//UART PORT RATE SELECT
`define COUNTER_VALUE1 216  //115.2kbps for clock=50MHz
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
 
 
`define RTL_SIMULATION  //comment out for synthesis
`define ALTERA //comment out if XILINX is used
`define Stratix2 //if Stratix2 is used
 
//IO  Map
// All access must be 32bit word
//3f80  usuall SP address (set by program)
//16KRAM
// 3fc0-3fef : AES reserved
// 3ff0 : debug port
// 3ff4 : debug port long
// 3ff8 : interrupt set address
// 3ffc : uart port
// 3ffc : [7:0] write_port/read_port
//                [8] write_busy
//                [31:9] :reserved
 
 
 
          `define Print_Port_Address      16'h3ff0  //ATMEL Big Endian
      `define Print_CAHR_Port_Address 16'h3ff1
      `define Print_INT_Port_Address  16'h3ff2  //First ADDRESS
      `define Print_LONG_Port_Address 16'h3ff4  //First ADDRESS
 
        `define UART_PORT_ADDRESS 16'h3ffc //
        `define INTERUPPT_ADDRESS 16'h3ff8 //

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[/] [yacc/] [trunk/] [syn/] [altra_stratix2/] [define.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tak.sugawa	`//Jul.11.2004`
2
3			`define LONG_ACCESS 2'b00
4			`define WORD_ACCESS 2'b01
5			`define BYTE_ACCESS 2'b10
6
7
8
9			`//Shift`
10
11			//`define SHIFT_NOTHING 2'b00
12			`define SHIFT_LEFT 2'b01
13			`define SHIFT_RIGHT_UNSIGNED 2'b10
14			`define SHIFT_RIGHT_SIGNED 2'b11
15
16			`//ALU`
17			`define ALU_NOTHING 4'b0000
18			`define ALU_ADD 4'b0001
19			`define ALU_SUBTRACT 4'b0010
20			`define ALU_LESS_THAN_UNSIGNED 4'b0101 //Jul.5.2004
21			`define ALU_LESS_THAN_SIGNED 4'b0100 //Jul.5.2004
22			`define ALU_OR 4'b0011
23			`define ALU_AND 4'b0110
24			`define ALU_XOR 4'b0111
25			`define ALU_NOR 4'b1000
26			//`define ALU_NOR 4'b0000 //Jul.6.2004
27
28			`//PC`
29			`define PC_INC 3'b000
30			`define PC_HOLD 3'b001
31			`define PC_IMM 3'b010
32			`define PC_IMM_PLUS 3'b011
33			`define PC_REG 3'b100
34			//`define FLAG_SEL 3'b101
35			`define PC_FLAG_SEL16 3'b101
36			`define PC_DEC 3'b110
37
38			`//ALU Right SEL`
39			`define Imm_signed 2'b00
40			`define Imm_unsigned 2'b01
41			`define A_RIGHT_ERT 2'b10
42			`define IMM_26_SEL 2'b11
43
44			`//ALU_LEFT_SEL`
45			`define PC_SEL 1'b1
46
47			`//Shift amount Sel`
48			`define A_sel 1'b0
49			`define Ers_d2_sel
50
51			`//Memory_Signed_extenstion`
52			`define M_unsigned 1'b0
53			`define M_signed 1'b1
54
55			`//RRegSel`
56			`define MOUT_SEL 2'b00
57			`define NREG_SEL 2'b01
58
59			`//AREG ALU/MUL_SEL`
60			`//2'b00 => ALU_SEL`
61			`define MUL_hi_SEL 2'b10
62			`define MUL_lo_SEL 2'b11
63
64			`//RF_INPUT SEL`
65			`define RF_ALU_sel 2'b00
66			`define RF_Shifter_sel 2'b01
67			`define RF_PC_SEL 2'b010
68			`define SHIFT16_SEL 2'b11
69
70			`//MUX`
71			//`define STRAIGHT 2'b00
72			//`define AREG_SEL 2'b01
73			//`define RREG_SEL 2'b11
74
75
76			`//RF INPUT ADDRESS`
77			`define RF_Ert_sel 2'b00
78			`define RF_Erd_sel 2'b01
79			`define RF_R15_SEL 2'b10
80			`define RF_INTR_SEL 2'b11
81
82			`define Last_Reg 31
83			`define Intr_Reg 26 // Jul.7.2004 TRY FOR OS,, Use R26 as Interrput Return address.
84			`//OPCODE`
85
86			`define add 6'b100000
87			`define addu 6'b100001
88			`define addi 6'b001000
89			`define addiu 6'b001001
90			`define sub 6'b100010
91			`define subu 6'b100011
92
93			`define and 6'b100100
94			`define andi 6'b001100
95			`define nor 6'b100111
96			`define or 6'b100101
97			`define ori 6'b001101
98
99			`define lsl 6'b000000
100			`define asr 6'b000011
101			`define lsr 6'b000010
102			`define sllv 6'b000100
103			`define srav 6'b000111
104			`define srlv 6'b000110
105
106			`define xor 6'b100110
107			`define xori 6'b001110
108
109			`define lui 6'b001111
110
111
112
113			`define comp_signed 6'b101010
114			`define comp_unsigned 6'b101011 //Jun.29.2004
115			`define comp_im_signed 6'b001010
116			`define comp_im_unsigned 6'b001011 //Jun.29.2004
117
118			`define beq 6'b000100
119			`define bgtz 6'b000111
120			`define blez 6'b000110
121			`define bne 6'b000101
122
123			`//opecode "000001" => [20:16] Special Opecode`
124			`define bltzal 5'b10000 //unsupported
125			`define bltz 5'b00000
126			`define bgezal 5'b10001 //unsupported�@
127			`define bgez 5'b00001
128			`define bltzall 5'b10010 //unsupprted
129			`define bltzl 5'b00010 //unsupported
130			`define bgezall 5'b10011 //unsupported
131			`define bgezl 5'b00011 //unsupported
132
133			`define jump 6'b000010
134			`define jump_and_link_im 6'b000011
135			`define jump_and_link_register 6'b001001
136			`define jmp_register 6'b001000
137
138			`//Load Instructions`
139
140			`define loadbyte_signed 6'b100000
141			`define loadbyte_unsigned 6'b100100
142			`define loadword_signed 6'b100001
143			`define loadword_unsigned 6'b100101
144			`define loadlong 6'b100011
145
146			`//Store Instructions`
147
148			`define storebyte 6'b101000
149			`define storeword 6'b101001
150			`define storelong 6'b101011
151
152			`//Exception and Interrupt Instructions`
153
154			`define softwave_interrupt 6'b011010
155			`define divs 6'b011010
156			`define divu 6'b011011
157			`define muls 6'b011000
158			`define mulu 6'b011001
159
160			`define mfhi 6'b010000
161			`define mflo 6'b010010
162
163			`define MUL_DIV_WORD_ACCESS 1'b1
164			`define MUL_DIV_BYTE_ACCESS 1'b0
165			`define MUL_DIV_MUL_SEL 1'b0
166
167
168			`define mult_nothing 4'b0000
169			`define mult_read_lo 4'b0000
170			`define mult_read_hi 4'b0001
171			`define mult_write_lo 4'b0011
172			`define mult_write_hi 4'b0100
173			`define mult_mult 4'b1000
174			`define mult_signed_mult 4'b1010
175			`define mult_divide 4'b1100
176			`define mult_signed_divide 4'b1110
177
178			`define SHIFT_AMOUNT_IMM_SEL 1'b0
179			`define SHIFT_AMOUNT_REG_SEL 1'b1
180
181
182			//`define RAM4K
183			`define RAM16K
184			//`define RAM32K
185
186
187
188			`//UART PORT RATE SELECT`
189			`define COUNTER_VALUE1 216 //115.2kbps for clock=50MHz
190			`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
191			`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
192
193
194			`define RTL_SIMULATION //comment out for synthesis
195			`define ALTERA //comment out if XILINX is used
196			`define Stratix2 //if Stratix2 is used
197
198			`//IO Map`
199			`// All access must be 32bit word`
200			`//3f80 usuall SP address (set by program)`
201			`//16KRAM`
202			`// 3fc0-3fef : AES reserved`
203			`// 3ff0 : debug port`
204			`// 3ff4 : debug port long`
205			`// 3ff8 : interrupt set address`
206			`// 3ffc : uart port`
207			`// 3ffc : [7:0] write_port/read_port`
208			`// [8] write_busy`
209			`// [31:9] :reserved`
210
211
212
213			`define Print_Port_Address 16'h3ff0 //ATMEL Big Endian
214			`define Print_CAHR_Port_Address 16'h3ff1
215			`define Print_INT_Port_Address 16'h3ff2 //First ADDRESS
216			`define Print_LONG_Port_Address 16'h3ff4 //First ADDRESS
217
218			`define UART_PORT_ADDRESS 16'h3ffc //
219			`define INTERUPPT_ADDRESS 16'h3ff8 //