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[/] [yacc/] [trunk/] [syn/] [altra_stratix2/] [ram4092x8_1_bb.v] - Blame information for rev 2

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1 2 tak.sugawa 
// megafunction wizard: %RAM: 2-PORT%VBB%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: ram4092x8_1.v
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// Megafunction Name(s):
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//                      altsyncram
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2005 Altera Corporation
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//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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//support information,  device programming or simulation file,  and any other
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//associated  documentation or information  provided by  Altera  or a partner
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//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
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//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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//other  use  of such  megafunction  design,  netlist,  support  information,
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//device programming or simulation file,  or any other  related documentation
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//or information  is prohibited  for  any  other purpose,  including, but not
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//limited to  modification,  reverse engineering,  de-compiling, or use  with
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//any other  silicon devices,  unless such use is  explicitly  licensed under
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//a separate agreement with  Altera  or a megafunction partner.  Title to the
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//intellectual property,  including patents,  copyrights,  trademarks,  trade
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//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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//support  information,  device programming or simulation file,  or any other
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//related documentation or information provided by  Altera  or a megafunction
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//partner, remains with Altera, the megafunction partner, or their respective
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//licensors. No other licenses, including any licenses needed under any third
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//party's intellectual property, are provided herein.
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module ram4092x8_1 (
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        data_a,
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        wren_a,
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        address_a,
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        data_b,
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        address_b,
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        wren_b,
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        clock,
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        q_a,
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        q_b);
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        input   [7:0]  data_a;
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        input     wren_a;
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        input   [11:0]  address_a;
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        input   [7:0]  data_b;
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        input   [11:0]  address_b;
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        input     wren_b;
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        input     clock;
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        output  [7:0]  q_a;
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        output  [7:0]  q_b;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
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// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
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// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
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// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
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// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
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// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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// Retrieval info: PRIVATE: REGwren NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: REGrren NUMERIC "0"
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// Retrieval info: PRIVATE: REGq NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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// Retrieval info: PRIVATE: CLRq NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "code1.hex"
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// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
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// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
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// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
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// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
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// Retrieval info: CONSTANT: INIT_FILE STRING "code1.hex"
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// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
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// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
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// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
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// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
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// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
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// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
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// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
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// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
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// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
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// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
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// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
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// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
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// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
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// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
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// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_bb.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_waveforms.html TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram4092x8_1_wave*.jpg FALSE

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