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[/] [yacc/] [trunk/] [syn/] [altra_stratix2/] [ram_regfile32xx32.v] - Blame information for rev 2

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1 2 tak.sugawa 
// megafunction wizard: %RAM: 3-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: alt3pram
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// ============================================================
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// File Name: ram_regfile32xx32.v
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// Megafunction Name(s):
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//                      alt3pram
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 4.2 Build 178 01/19/2005 SP 1 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2005 Altera Corporation
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//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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//support information,  device programming or simulation file,  and any other
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//associated  documentation or information  provided by  Altera  or a partner
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//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
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//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
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//other  use  of such  megafunction  design,  netlist,  support  information,
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//device programming or simulation file,  or any other  related documentation
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//or information  is prohibited  for  any  other purpose,  including, but not
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//limited to  modification,  reverse engineering,  de-compiling, or use  with
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//any other  silicon devices,  unless such use is  explicitly  licensed under
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//a separate agreement with  Altera  or a megafunction partner.  Title to the
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//intellectual property,  including patents,  copyrights,  trademarks,  trade
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//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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//support  information,  device programming or simulation file,  or any other
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//related documentation or information provided by  Altera  or a megafunction
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//partner, remains with Altera, the megafunction partner, or their respective
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//licensors. No other licenses, including any licenses needed under any third
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//party's intellectual property, are provided herein.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module ram_regfile32xx32 (
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        data,
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        wraddress,
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        rdaddress_a,
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        rdaddress_b,
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        wren,
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        clock,
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        qa,
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        qb);
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        input   [31:0]  data;
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        input   [4:0]  wraddress;
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        input   [4:0]  rdaddress_a;
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        input   [4:0]  rdaddress_b;
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        input     wren;
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        input     clock;
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        output  [31:0]  qa;
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        output  [31:0]  qb;
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        wire [31:0] sub_wire0;
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        wire [31:0] sub_wire1;
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        wire [31:0] qa = sub_wire0[31:0];
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        wire [31:0] qb = sub_wire1[31:0];
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        alt3pram        alt3pram_component (
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                                .wren (wren),
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                                .inclock (clock),
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                                .data (data),
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                                .rdaddress_a (rdaddress_a),
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                                .wraddress (wraddress),
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                                .rdaddress_b (rdaddress_b),
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                                .qa (sub_wire0),
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                                .qb (sub_wire1)
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                                // synopsys translate_off
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                                ,
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                                .aclr (),
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                                .inclocken (),
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                                .outclock (),
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                                .outclocken (),
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                                .rden_a (),
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                                .rden_b ()
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                                // synopsys translate_on
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                                );
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        defparam
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                alt3pram_component.intended_device_family = "Stratix II",
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                alt3pram_component.width = 32,
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                alt3pram_component.widthad = 5,
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                alt3pram_component.indata_reg = "INCLOCK",
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                alt3pram_component.write_reg = "INCLOCK",
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                alt3pram_component.rdaddress_reg_a = "INCLOCK",
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                alt3pram_component.rdaddress_reg_b = "INCLOCK",
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                alt3pram_component.rdcontrol_reg_a = "UNREGISTERED",
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                alt3pram_component.rdcontrol_reg_b = "UNREGISTERED",
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                alt3pram_component.outdata_reg_a = "UNREGISTERED",
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                alt3pram_component.outdata_reg_b = "UNREGISTERED",
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                alt3pram_component.outdata_aclr_a = "OFF",
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                alt3pram_component.outdata_aclr_b = "OFF",
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                alt3pram_component.lpm_type = "alt3pram",
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                alt3pram_component.lpm_hint = "USE_EAB=ON";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: WidthData NUMERIC "32"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: rden_a NUMERIC "0"
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// Retrieval info: PRIVATE: rden_b NUMERIC "0"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGwrite NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1"
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// Retrieval info: PRIVATE: REGrren_a NUMERIC "0"
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// Retrieval info: PRIVATE: REGrren_b NUMERIC "0"
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// Retrieval info: PRIVATE: REGqa NUMERIC "0"
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// Retrieval info: PRIVATE: REGqb NUMERIC "0"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwrite NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0"
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// Retrieval info: PRIVATE: CLRqa NUMERIC "0"
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// Retrieval info: PRIVATE: CLRqb NUMERIC "0"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "32"
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// Retrieval info: CONSTANT: WIDTHAD NUMERIC "5"
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// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK"
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// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK"
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// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK"
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// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK"
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// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram"
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// Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON"
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// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
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// Retrieval info: USED_PORT: qa 0 0 32 0 OUTPUT NODEFVAL qa[31..0]
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// Retrieval info: USED_PORT: qb 0 0 32 0 OUTPUT NODEFVAL qb[31..0]
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// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
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// Retrieval info: USED_PORT: rdaddress_a 0 0 5 0 INPUT NODEFVAL rdaddress_a[4..0]
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// Retrieval info: USED_PORT: rdaddress_b 0 0 5 0 INPUT NODEFVAL rdaddress_b[4..0]
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
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// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
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// Retrieval info: CONNECT: qa 0 0 32 0 @qa 0 0 32 0
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// Retrieval info: CONNECT: qb 0 0 32 0 @qb 0 0 32 0
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// Retrieval info: CONNECT: @wraddress 0 0 5 0 wraddress 0 0 5 0
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// Retrieval info: CONNECT: @rdaddress_a 0 0 5 0 rdaddress_a 0 0 5 0
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// Retrieval info: CONNECT: @rdaddress_b 0 0 5 0 rdaddress_b 0 0 5 0
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// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_regfile32xx32_bb.v TRUE

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